WO2012100541A1 - Procédé et dispositif pour une communication de données entre deux caméras - Google Patents

Procédé et dispositif pour une communication de données entre deux caméras Download PDF

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Publication number
WO2012100541A1
WO2012100541A1 PCT/CN2011/079527 CN2011079527W WO2012100541A1 WO 2012100541 A1 WO2012100541 A1 WO 2012100541A1 CN 2011079527 W CN2011079527 W CN 2011079527W WO 2012100541 A1 WO2012100541 A1 WO 2012100541A1
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WO
WIPO (PCT)
Prior art keywords
chip
slave
master chip
works
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2011/079527
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English (en)
Inventor
Lixin Zhao
Qing MENG
Xiaomei Ma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GALAXYCORE Inc
Galaxycore Shanghai Ltd Corp
Original Assignee
GALAXYCORE Inc
Galaxycore Shanghai Ltd Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GALAXYCORE Inc, Galaxycore Shanghai Ltd Corp filed Critical GALAXYCORE Inc
Publication of WO2012100541A1 publication Critical patent/WO2012100541A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/66—Remote control of cameras or camera parts, e.g. by remote control devices
    • H04N23/661—Transmitting camera control signals through networks, e.g. control via the Internet
    • H04N23/662—Transmitting camera control signals through networks, e.g. control via the Internet by using camera arrangements where one camera controls another camera to affect the control of camera image capture, e.g. placing the camera in a desirable condition to capture a desired image
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices

Definitions

  • This invention is generally related to image processing field, and particularly to a method and a device for data communication between two cameras.
  • the camera chip is widely used in digital products such as mobile phones, PDAs and laptops.
  • digital products such as mobile phones, PDAs and laptops.
  • the two cameras may communicate with a receiving chip separately by using their own dedicated data buses or communicate with a receiving chip alternatively by sharing one data bus. If the two cameras communicate with a receiving chip alternatively by sharing one data bus, the two cameras can not work and drive the data bus at the same time, wherein each of the two cameras has dedicated functional blocks including an image area, analog circuits and an image processing unit.
  • An object of the present invention is to simplify internal structure and to reduce cost of a two-camera device by sharing only one image processing unit.
  • an embodiment of the present invention provides a method for data communication between two cameras, including: providing a two-camera device, wherein a master chip is arranged in a camera and a slave chip is arranged in the other camera; configuring an alternate working mechanism between the master chip and the slave chip.
  • the master chip when the master chip is working in a horizontal scan state, the slave chip is working in a horizontal blanking state, and when the master chip works in the horizontal blanking state, the slave chip works in the horizontal scan state; and configuring the slave chip to send out digital signals when the slave chip is in the horizontal scan state and the master chip to receive the digital signals which is sent from the slave chip when the master chip is in the horizontal blanking state.
  • another embodiment of the present invention further provides a device for data communication between two cameras which includes a mater chip and a slave chip
  • the slave chip includes: a first image sensor unit for acquiring first analog image signals; a first reading unit for reading the first analog image signals from the first image sensor unit; a first analog to digital conversion unit for converting the first analog image signals to first digital signals; and an output unit which includes output interfaces for sending out the first digital signals
  • the master chip includes: a second image sensor unit for acquiring second analog image signals; a second reading unit for reading the second analog image signals from the second image sensor unit; a second analog to digital conversion unit for converting the second analog image signals to second digital signals; a processing unit for converting the first digital signals and the second digital signals to image data; and an input/output unit including data interfaces, wherein the data interfaces are adopted for sending the image data to a receiving chip and receiving the first digital signals from the slave chip when the master chip works in the horizontal blanking state.
  • the master chip works in the horizontal scan state when the slave chip works in the horizontal blanking state
  • the master chip works in the horizontal blanking state when the slave chip works in the horizontal scan state
  • the embodiments of the present invention have the following advantages: the embodiments of the present invention not only can simplify internal structure of the two-camera devices but also can make it practicable that only one image processing unit is used to control and manage two camera chips in different work states alternately. Therefore, size of the two-camera device becomes smaller and the cost of the two-camera devices is reduced.
  • FIG. 1 is a schematic structural view of a camera in a two-camera device in prior art
  • FIG. 2 is a schematic structural view of a two-camera device according to an embodiment of the present invention.
  • FIG. 3 is a schematic view for showing timing comparison between a master chip and a slave chip in a two-camera device according to the embodiment of the present invention
  • each camera of the two-camera device has a same internal structure, including: an image sensor unit 101 for acquiring analog image signals; a reading unit 102 for reading the analog image signals from the image sensor unit 101; an analog to digital conversion unit 103 for converting the analog image signals to digital signals; a processing unit 104 for processing the digital signals such as noise removal, interpolating, edge enhancement, grayscale correction, color correction; and an input/output unit 105 including data interfaces for sending image information from the processing unit 104 to a receiving chip.
  • the data interfaces are idle in some time slices when the two-camera device is working.
  • the time slices are defined as idle time periods of the two-camera device. Specifically, in a scan process of a scanning head in a camera which converts optical signals to electric signals, a scanning head always starts from an upper-left corner of an image, and proceeds horizontally. After the scanning head arrives at a right edge of the image, the scanning head returns to the left side again and starts to scan a next line.
  • the state when the scanning head is scanning is defined as a horizontal scan state, and the state when the scanning head is returning from right edge to left edge is defined as a horizontal blanking state.
  • the camera stops sending out data and makes output interfaces idle. Therefore, the horizontal blanking state is an idle time period of the camera.
  • data interfaces of one camera in a two-camera device can receive external image data when the camera works in the horizontal blanking state, and send out processed image information when the camera works in the horizontal scan state.
  • one processing unit of the other camera in the two-camera device can be removed and only one processing unit is used to process image signals for both of the two cameras in the two-camera device, which not only can ensure signal processing quality but also can reduce the cost and size of the two-camera device.
  • the inventor provides a method for data communication between two cameras in a two-camera device, including: providing a two-camera device, wherein a master chip is arranged in a camera and a slave chip is arranged in the other camera; configuring an alternate working mechanism between the master chip and the slave chip, wherein when the mast chip works in a horizontal scan state, the slave chip works in a horizontal blanking state; and when the mast chip works in the horizontal blanking state, the slave chip works in the horizontal scan state; and configuring the slave chip to send out digital signals when the slave chip works in the horizontal scan state and the master chip to receive digital signals sent from the slave chip when the master chip works in the horizontal blanking state.
  • the present invention further provides a device for data communication between two cameras, including a mater chip 100 and a slave chip 200.
  • the slave chip 200 includes: an image sensor unit 201 for acquiring first analog image signals; a reading unit 202 for reading the first analog image signals from the image sensor unit 201; an analog to digital conversion unit 203 for converting the first analog image signals to first digital signals; and an output unit 204 which includes output interfaces for sending out the first digital signals.
  • the master chip 100 includes: an image sensor unit 101 for acquiring second analog image signals; a reading unit 102 for reading the second analog image signals from the image sensor unit 101; an analog to digital conversion unit 103 for converting the second analog image signals to second digital signals; a processing unit 104 for converting the first digital signals and the second digital signals to image data; and an input/output unit 105 including data interfaces, wherein the data interfaces are adopted for sending out the image data to a receiving chip, and receiving the first digital signals from the slave chip when the master chip works in the horizontal blanking state.
  • the slave chip 200 includes: an image sensor unit 201 for first acquiring analog image signals; a reading unit 202 for reading the first analog image signals from the image sensor unit 201; an analog to digital conversion unit
  • the master chip 100 includes: an image sensor unit 101 for acquiring second analog image signals; a reading unit 102 for reading the second analog image signals from the image sensor unit 101; an analog to digital conversion unit 103 for converting the second analog image signals to second digital signals; a processing unit 104 for converting the first digital signals and the second digital signals to image data; and an input/output unit 105 including data interfaces, wherein the data interfaces are adopted for sending the image data to a receiving chip, and receiving the first digital signals from the slave chip 200 when the master chip works in the horizontal blanking state.
  • the master chip 100 communicates with a receiving chip in a DVP parallel port mode.
  • the output unit 204 of the slave chip 200 includes 1 clock output pin, 1 data output pin and some other pins
  • the input/output unit of the master chip 100 includes 8 data output pins and some other pins, wherein one of the 8 data output pins in the master chip 100 works as a clock input pin and is connected with the clock output pin of the slave chip 200, and one of the rest data output pins in the master chip 100 is connected with the data output pin of the slave chip 200.
  • the master chip 100 communicates with a receiving chip in DVP parallel port mode.
  • the output unit 204 of the slave chip 200 includes 1 clock output pin,
  • the input/output unit of the master chip 100 includes 8 data output pins and some other pins, wherein one of the 8 data output pins in the master chip 100 works as a clock input pin and is connected with the clock output pin of the slave chip 200, and two of the rest data output pins in the master chip 100 is connected with the data output pins of the slave chip 200.
  • the master chip 100 communicates with a receiving chip in DVP parallel port mode.
  • the output unit 204 of the slave chip 200 includes 1 clock output pin,
  • the input/output unit of the master chip 100 includes 8 data output pins and some other pins, wherein one of the 8 data output pins in the master chip 100 works as a clock input pin and is connected with the clock output pin of the slave chip 200, and three of the rest data output pins in the master chip 100 is connected with the data output pins of the slave chip 200.
  • the master chip 100 communicates with a receiving chip in DVP parallel port mode.
  • the output unit 204 of the slave chip 200 includes 1 clock output pin, 4 data output pin and some other pins
  • the input/output unit of the master chip 100 includes 8 data output pins and some other pins, wherein one of the 8 data output pins in the master chip 100 works as a clock input pin and is connected with the clock output pin of the slave chip 200, and four of the rest data output pins in the master chip 100 is connected with the data output pins of the slave chip 200.
  • the master chip 100 communicates with a receiving chip in a SPI mode.
  • the output unit 204 of the slave chip 200 includes 1 clock output pin, 1 data output pin and some other pins
  • the input/output unit of the master chip 100 includes 8 data output pins and some other pins, wherein one of the 8 data output pins in the master chip 100 works as a clock input pin and is connected with the clock output pin of the slave chip 200, another one of the 8 data output pins in the master chip 100 is connected with the receiving chip as a SPI data pin, and one of the rest data output pins in the master chip 100 is connected with the data output pin of the slave chip 200.
  • the master chip 100 communicates with a receiving chip in SPI mode.
  • the output unit 204 of the slave chip 200 includes 1 clock output pin, 2 data output pin and some other pins
  • the input/output unit of the master chip 100 includes 8 data output pins and some other pins, wherein one of the 8 data output pins in the master chip 100 works as a clock input pin and is connected with the clock output pin of the slave chip 200, another one of the 8 data output pins in the master chip 100 is connected with the receiving chip as a SPI data pin, and two of the rest data output pins in the master chip 100 is connected with the data output pins of the slave chip 200.
  • the master chip 100 communicates with a receiving chip in SPI mode.
  • the output unit 204 of the slave chip 200 includes 1 clock output pin, 3 data output pin and some other pins
  • the input/output unit of the master chip 100 includes 8 data output pins and some other pins, wherein one of the 8 data output pins in the master chip 100 works as a clock input pin and is connected with the clock output pin of the slave chip 200, another one of the 8 data output pins in the master chip 100 is connected with the receiving chip as a SPI data pin, and three of the rest data output pins in the master chip 100 is connected with the data output pins in the slave chip 200.
  • the master chip 100 communicates with a receiving chip in SPI mode.
  • the output unit 204 of the slave chip 200 includes 1 clock output pin, 4 data output pin and some other pins
  • the input/output unit of the master chip 100 includes 8 data output pins and some other pins, wherein one of the 8 data output pins in the master chip 100 works as a clock input pin and is connected with the clock output pin of the slave chip 200, another one of the 8 data output pins in the master chip 100 is connected with the receiving chip as a SPI data pin, and four of the rest data output pins in the master chip 100 is connected with the data output pins of the slave chip 200.
  • the master chip and the slave chip are configured to work under an alternate working mechanism.
  • the master chip 100 and the slave chip 200 are configured to work with a same clock frequency.
  • the master chip 100 works in the horizontal blanking state when the slave chip 200 works in the horizontal scan state, and, in contrast, the master chip 100 works in the horizontal scan state when the slave chip 200 works in the horizontal blanking state.
  • the slave chip 200 sends digital image signals to the master chip 100, and the master chip 100 receives the digital image signals from the slave chip 200.
  • the two-camera device may work in two modes: a stand-alone mode in which the master chip works alone and a master- slave mode in which the master chip and the slave chip both work.
  • the master chip 100 communicates with a receiving chip in DVP parallel port mode.
  • the slave chip 200 acquires first image signals through the image sensor unit 201; After that, the reading unit 202 of the slave chip reads the first image signals and sends the first image signals to the analog to digital conversion unit 203; then the analog to digital conversion unit 203 converts the first analog image signals to first digital signals and sends the first digital signals to the output unit 204; further, when the master chip works in the horizontal blanking state and the slave chip works in the horizontal scan state, the first digital signals in the output unit 204 is sent to the processing unit 104 trough the input/output unit 105 of the master chip, so that the processing unit 104 can receive and process the first digital image signals from the slave chip 200; finally, the processed image information can be sent from the processing unit 104 to DVP interfaces of the receiving chip through the input/output unit 105 when the master chip works in the horizontal scan state and the slave chip works in the horizontal blanking state.
  • the communication mode between the master chip 100 and the slave chip 200 includes a parallel communication mode and a serial communication mode.
  • the master chip 100 communicates with the slave chip 200 in the serial communication mode, wherein the serial communication mode supports not only unspecified number data bits but also flag bits which is used for marking by the master chip 100.
  • the master chip 100 acquires second image signals through the image sensor unit 101; after that, the reading unit 102 of the master chip reads the second image signals and sends the second image signals to the analog to digital conversion unit 103; then, the analog to digital conversion unit 103 converts the second analog image signals to second digital signals and sends the second digital signals to the processing unit 104; finally, the processing unit 104 processes the second digital signals, and sends the processed image information to the interfaces of an receiving chip through the input/output unit 105.
  • the two-camera device may work in two modes: a stand-alone mode in which the master chip works alone and a master- slave mode in which the master chip and the slave chip both work.
  • the master chip 100 communicates with a receiving chip in a SPI parallel port mode.
  • the slave chip 200 acquires first image signals through the image sensor unit 201; After that, the reading unit 202 of the slave chip reads the first image signals and sends the first image signals to the analog to digital conversion unit 203; then the analog to digital conversion unit 203 converts the first analog image signals to first digital signals and sends the first digital signals to the output unit 204; further, when the master chip works in the horizontal blanking state and the slave chip works in the horizontal scan state, the first digital signals in the output unit 204 is sent to the processing unit 104 trough the input/output unit 105 of the master chip, so that the processing unit 104 can receive and process the first digital image signals from the slave chip 200; finally, the processed image information can be sent from the processing unit 104 to SPI interfaces of the receiving chip through the input/output unit 105 when the master chip works in the horizontal scan state and the slave chip works in the horizontal blanking state.
  • the communication mode between the master chip 100 and the slave chip 200 includes a parallel communication mode and a serial communication mode.
  • the master chip 100 communicates with the slave chip 200 in the serial communication mode, wherein the serial communication mode supports not only unspecified number data bits but also flag bits which is used for marking by the master chip 100.
  • the master chip 100 acquires second image signals through the image sensor unit 101; after that, the reading unit 102 of the master chip reads the second image signals and sends the second image signals to the analog to digital conversion unit 103; then, the analog to digital conversion unit 103 converts the second analog image signals to second digital signals and sends the second digital signals to the processing unit 104; finally, the processing unit 104 processes the second digital signals, and sends the processed image information to the interfaces of an receiving chip through the input/output unit 105.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)

Abstract

La présente invention se rapporte à un procédé et à un dispositif pour une communication de données entre deux caméras. Le procédé selon l'invention consiste : à fournir un dispositif à deux caméras caractérisé en ce qu'une puce maîtresse est placée dans l'une des caméras tandis qu'une puce asservie est placée dans l'autre caméra ; à configurer un mécanisme de fonctionnement en alternance entre la puce maîtresse et la puce asservie caractérisé en ce que, quand la puce maîtresse fonctionne dans un état de balayage horizontal, la puce asservie fonctionne dans un état d'occultation horizontal et en ce que, quand la puce maîtresse fonctionne dans l'état d'occultation horizontal, la puce asservie fonctionne dans l'état de balayage horizontal ; et à configurer la puce asservie de façon à ce qu'elle envoie des signaux numériques quand elle fonctionne dans l'état de balayage horizontal et à configurer la puce maîtresse de façon à ce qu'elle reçoive les signaux numériques quand elle fonctionne dans l'état d'occultation horizontal. La présente invention permet de simplifier la structure interne d'un dispositif à deux caméras. Elle permet en outre de réduire la taille ainsi que le coût du dispositif à deux caméras.
PCT/CN2011/079527 2011-01-25 2011-09-09 Procédé et dispositif pour une communication de données entre deux caméras Ceased WO2012100541A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110027450.6 2011-01-25
CN201110027450 2011-01-25

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WO2012100541A1 true WO2012100541A1 (fr) 2012-08-02

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060024047A1 (en) * 2004-07-27 2006-02-02 Lg Electronics Inc. Image signal processing apparatus and method thereof in mobile communications terminal
CN101001388A (zh) * 2006-01-11 2007-07-18 松下电器产业株式会社 摄影系统
JP2009260916A (ja) * 2008-03-17 2009-11-05 Sony Corp 撮像装置、および信号処理方法、並びにコンピュータ・プログラム
CN101849408A (zh) * 2007-11-30 2010-09-29 柯达公司 具有共享处理的多图像传感器系统
CN102164232A (zh) * 2011-01-30 2011-08-24 格科微电子（上海）有限公司 一种双摄像头之间数据通讯的方法及其实现装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060024047A1 (en) * 2004-07-27 2006-02-02 Lg Electronics Inc. Image signal processing apparatus and method thereof in mobile communications terminal
CN101001388A (zh) * 2006-01-11 2007-07-18 松下电器产业株式会社 摄影系统
CN101849408A (zh) * 2007-11-30 2010-09-29 柯达公司 具有共享处理的多图像传感器系统
JP2009260916A (ja) * 2008-03-17 2009-11-05 Sony Corp 撮像装置、および信号処理方法、並びにコンピュータ・プログラム
CN102164232A (zh) * 2011-01-30 2011-08-24 格科微电子（上海）有限公司 一种双摄像头之间数据通讯的方法及其实现装置

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