WO2012107985A1 - Dispositif de traitement de signaux d'image et procédé de traitement de signaux d'image - Google Patents

Dispositif de traitement de signaux d'image et procédé de traitement de signaux d'image Download PDF

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Publication number
WO2012107985A1
WO2012107985A1 PCT/JP2011/007062 JP2011007062W WO2012107985A1 WO 2012107985 A1 WO2012107985 A1 WO 2012107985A1 JP 2011007062 W JP2011007062 W JP 2011007062W WO 2012107985 A1 WO2012107985 A1 WO 2012107985A1
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Prior art keywords
frame
output
video
frame rate
synchronization
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Ceased
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PCT/JP2011/007062
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English (en)
Japanese (ja)
Inventor
進吾 宮内
英俊 武田
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0442—Handling or displaying different aspect ratios, or changing the aspect ratio
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Definitions

  • the present invention relates to a video signal processing apparatus and a video signal processing method for displaying a plurality of videos having different frame rates in synchronization.
  • DTV digital television
  • video content it has become common to view a plurality of video contents simultaneously by helping to increase the screen size and resolution.
  • a viewer can view videos of different channels at the same time.
  • video content from a plurality of video sources such as TV broadcast video, video from a recording device, or video obtained from an external network.
  • sub-video video
  • a PC or the like determines a frame rate with reference to a free-run generated vertical synchronization signal, and displays all videos in synchronization with the determined frame rate.
  • frame synchronization processing is adjustment processing for excess or deficiency in the number of frames.
  • the frame synchronization process if the frame rate of the sub-video is larger than the frame rate of the main video, the sub-video frames are thinned out at a constant period (skip process) and displayed. Also, when the frame rate of the sub-video is smaller than the frame rate of the main video, the same frame of the sub-video is displayed repeatedly (repeat processing) at a constant period.
  • the sub video frame is displayed every time about 1000 frames (about 16.7 seconds) are displayed. One frame is skipped. (For example, see Patent Document 1 and Patent Document 2).
  • the sub-picture frames are thinned out at regular intervals, or the same frame is repeatedly displayed, which may give the viewer a sense of discomfort.
  • the judder of the video is likely to be perceived by the viewer. That is, the problem is that the viewer feels uncomfortable by the frame sync processing and the viewing quality is impaired.
  • an object of the present invention is to provide a video signal processing apparatus capable of displaying a smooth and high-definition video with little discomfort for a viewer when a plurality of videos with different frame rates are displayed in synchronization.
  • a video signal processing apparatus is a video signal processing apparatus that outputs a plurality of input videos having different input frame rates in synchronization with each other.
  • a video acquisition unit that sequentially acquires the frames included in the corresponding input frame rate, an output frame rate determination unit that determines an output frame rate, and a frame of each of the plurality of input videos acquired by the video acquisition unit
  • a frame synchronizer that sequentially outputs in synchronism with the output frame rate, and a video output that sequentially outputs a synthesized frame obtained by synthesizing each frame output from the frame synchronizer in synchronism with the output frame rate.
  • the frame synchronization unit includes a corresponding input frame of the plurality of input images. Mureto respect asynchronous video different from the output frame rate, the adjustment process to eliminate the deviation between the output frame rate to the input frame rate, executes during which it can be determined as a hard period noticeable to the viewer.
  • the frame synchronization unit detects the adjustment processing period in which the uncomfortable feeling generated in the composite frame by executing the adjustment process on the asynchronous video is a period in which the viewer who views the composite frame is not easily noticed. It is preferable to include a detection unit and a control unit that executes the adjustment process on the asynchronous video during the adjustment process period detected by the synchronization timing detection unit.
  • the synchronization timing detection unit detects a motion amount of the asynchronous video, a period in which the motion amount is smaller than a first threshold value, and a second threshold value in which the motion amount is larger than the first threshold value. Is detected as the adjustment process period, or the synchronization timing detection unit detects a change in the scene of the asynchronous video, and a period corresponding to the change in the scene of the video is set as the adjustment process period. It may be detected.
  • the frame adjustment process is performed during a period in which there is little video movement, a period in which there is a lot of video movement, and a period corresponding to the switching of the video scene.
  • the frame synchronization unit as the adjustment process, outputs a part of a frame when the input frame rate of the asynchronous video is larger than the output frame rate, and the input frame rate of the asynchronous video is If the output frame rate is smaller than the same, the same frame is repeatedly output.
  • the frame synchronization unit uses the M (M is an integer of 2 or more) original frames included in the asynchronous video as a frame between the M original frames as the adjustment process.
  • Corresponding N (M ⁇ N) interpolation frames may be generated, and the generated N interpolation frames may be output as the asynchronous video frame in the predetermined period.
  • the frame synchronization unit detects a motion vector between original frames located before and after the generated interpolation frame, and obtains the detected motion vector in proportion to the original frame with a temporal distance of the interpolation frame.
  • the interpolation frame may be generated assuming that the interpolation motion vector to be obtained is a motion vector for the original frame of the interpolation frame.
  • the output frame rate determining unit may determine any one of the plurality of input videos as the output frame rate, and the output frame rate determining unit may determine the plurality of input videos. A frame rate different from any of the input frame rates may be determined as the output frame rate.
  • the present invention is also a video signal processing method for outputting a plurality of input videos having different input frame rates in synchronization with each other, and sequentially including the frames included in each of the plurality of input videos at the corresponding input frame rate.
  • a video acquisition step for acquiring, an output frame rate determination step for determining an output frame rate, and a frame synchronization step for sequentially outputting frames of each of the plurality of input videos acquired by the video acquisition unit at the output frame rate;
  • a video output step for sequentially outputting a synthesized frame obtained by synthesizing each frame output in synchronization with the output frame rate from the frame synchronization step.
  • the frame synchronization step the plurality of input videos Among these, the corresponding input frame rate is the output.
  • An adjustment process for eliminating a difference between the input frame rate and the output frame rate is performed on an asynchronous video different from a frame rate so as not to be noticeable to a viewer, and the frame synchronization step includes a frame of the asynchronous video.
  • the synchronization timing detection step for detecting an adjustment processing period in which the uncomfortable feeling generated in the composite frame due to the adjustment process being applied to the viewer who views the composite frame is difficult to detect is detected in the synchronization timing detection step.
  • the video signal processing method of the present invention is a video signal processing method for outputting a plurality of input videos having different input frame rates in synchronization with each other, and corresponding to the frames included in each of the plurality of input videos.
  • An image acquisition step for sequentially acquiring at an input frame rate, an output frame rate determination step for determining an output frame rate, and a frame of each of the plurality of input images acquired by the image acquisition unit is sequentially output at the output frame rate
  • a frame synchronization step and a video output step for sequentially outputting a synthesized frame obtained by synthesizing each frame output in synchronization with the output frame rate from the frame synchronization step.
  • the corresponding input frame Using M (M is an integer of 2 or more) original frames included in a predetermined period of asynchronous video whose frame rate is different from the output frame rate, N (M ⁇ ) corresponding to a frame between the M original frames N) interpolation frames may be generated, and the generated N interpolation frames may be output as the asynchronous video frames in the predetermined period.
  • the video signal processing apparatus can display a smooth and high-quality video in which a viewer does not feel uncomfortable when a plurality of videos with different frame rates are displayed in synchronization.
  • FIG. 1 is a block diagram showing a configuration of a video signal processing apparatus according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of the operation of the video signal processing apparatus according to Embodiment 1 of the present invention.
  • FIG. 3 is a block diagram showing the configuration of the frame synchronization unit in the first embodiment of the present invention.
  • FIG. 4 is a diagram for explaining conventional frame skip processing.
  • FIG. 5 is a diagram for explaining a conventional frame repeat process.
  • FIG. 6 is a diagram for explaining frame skip processing according to Embodiment 1 of the present invention.
  • FIG. 7 is a diagram illustrating frame repeat processing according to Embodiment 1 of the present invention.
  • FIG. 8 is a flowchart of the adjustment process of the frame synchronization unit in the first embodiment of the present invention.
  • FIG. 9 is a block diagram showing the configuration of the frame synchronization unit in the second embodiment of the present invention.
  • FIG. 10 is a diagram for explaining the adjustment process of the frame synchronization unit in the second embodiment of the present invention.
  • FIG. 11 is a diagram for explaining the adjustment process of the frame synchronization unit in the second embodiment of the present invention.
  • FIG. 12 is a flowchart of the adjustment process of the frame synchronization unit according to the second embodiment of the present invention.
  • FIG. 13 is a diagram showing an application example of the video signal processing apparatus according to Embodiments 1 and 2 of the present invention.
  • Embodiment 1 of the present invention will be described with reference to FIGS. 1 and 2.
  • FIG. 1 is a block diagram showing the configuration of the video signal processing apparatus according to Embodiment 1 of the present invention.
  • FIG. 2 is a flowchart of the operation of the video signal processing apparatus according to Embodiment 1 of the present invention.
  • the video signal processing device 10 includes a video acquisition unit 100, an output frame rate determination unit 200, a frame synchronization unit 300, and a video output unit 500.
  • a frame memory 400 and a video display unit 600 are also shown.
  • the video acquisition unit 100 sequentially acquires frames included in each of the plurality of input videos at a corresponding input frame rate (S10). In addition, the video acquisition unit 100 outputs each frame of the input video signal acquired according to the input frame rate to the frame synchronization unit 300.
  • the output frame rate determining unit 200 determines the output frame rate. Specifically, one of the input frame rates corresponding to the plurality of video signals input to the video acquisition unit 100 is determined as the output frame rate (S20).
  • the output frame rate determination unit 200 may determine the output frame rate from the free-run vertical synchronization signal.
  • the free-run vertical synchronization signal is a signal that realizes a predetermined frequency (for example, 60 Hz) using a clock generated by a clock generator having a variable clock frequency.
  • the frame synchronization unit 300 sequentially outputs the frames of each of the plurality of input videos acquired by the video acquisition unit 100 at the output frame rate determined by the output frame rate determination unit 200 (S30). Specifically, the frames of the plurality of input videos acquired by the video acquisition unit 100 are temporarily stored in the frame memory 400, read at the output frame rate, and output to the video output unit 500.
  • the frame synchronization unit 300 adjusts the number of frames and outputs each frame of an asynchronous video having a corresponding input frame rate different from the output frame rate among a plurality of input videos. A more specific configuration of the frame synchronization unit 300 and details of the adjustment process will be described later.
  • the frame memory 400 is a storage unit that temporarily stores frames of a plurality of input videos.
  • the specific configuration of the storage unit is not particularly limited.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • flash memory ferroelectric memory
  • HDD HardDisc Data
  • the video output unit 500 sequentially outputs combined frames obtained by combining the frames output from the frame sync unit 300 in synchronization with the output frame rate to the video display unit 600 (S40).
  • the video display unit 600 displays a video composed of the composite frame output from the video output unit 500 (S50).
  • the video display unit 600 is an LCD (Liquid Crystal Display), for example. Not only this but PDP (Plasma Display Panel) and an organic electroluminescent display (OLED: Organic Light Emitting Display) may be sufficient.
  • FIG. 3 is a configuration diagram of the frame synchronization unit 300 according to the first embodiment.
  • the frame synchronization unit 300 includes a synchronization timing detection unit 310 and an address control unit 320 (control unit).
  • the synchro timing detection unit 310 detects an adjustment processing period in which the uncomfortable feeling generated in the composite frame by performing the adjustment process on the frame of the asynchronous video is less noticeable to the viewer who views the composite frame.
  • the synchronization timing detection unit 310 adjusts a period in which the video motion is small, the video motion is intense, or the video scene changes and a blackout or whiteout occurs when the scene changes. Detect as period.
  • SAD is a parameter obtained by calculating an absolute value of a luminance difference between corresponding pixels of a frame that is temporally continuous with the frame for each pixel constituting the frame, and summing the absolute values of the calculated luminance differences of the pixels. is there.
  • a method for detecting the amount of motion of an image using SAD will be described.
  • the synchronization timing detection unit 310 divides each frame into several small areas for temporally continuous frames constituting the asynchronous video.
  • the synchronization timing detection unit 310 obtains the SAD of each divided small area of one frame with the corresponding small area of the previous frame or the subsequent frame. That is, the synchronization timing detection unit 310 calculates the sum of absolute values of the luminance differences of the pixels constituting the small area and the corresponding pixels in the previous frame or the subsequent frame. As a result, the same number of SADs as the number of small regions is obtained.
  • the synchronization timing detection unit 310 obtains the sum of SADs corresponding to each small area.
  • the synchronization timing detection unit 310 sets a threshold for the sum of the SADs, and detects a period in which the video motion is small and a period in which the video motion is intense.
  • the synchronization timing detection unit 310 detects a period corresponding to the frame as a period in which the motion of the video is small for a frame in which the total SAD is smaller than the first threshold. In addition, the synchronization timing detection unit 310 detects a period corresponding to the frame as a period in which the motion of the video is intense for a frame in which the sum of SADs is larger than the second threshold, which is larger than the first threshold.
  • the synchronization timing detection unit 310 may detect a period in which the video motion is small and a period in which the video motion is intense depending on the number of small regions where the SAD exceeds a predetermined value.
  • the synchronization timing detection unit 310 detects a period corresponding to a frame in which the number of small areas exceeding a predetermined value is smaller than the first threshold as a period in which video motion is small.
  • the synchronization timing detection unit 310 detects a period corresponding to a frame in which the number of small areas exceeding a predetermined value is larger than the second threshold and larger than the second threshold as a period in which video motion is intense.
  • the period during which the video scene changes is detected by, for example, APL (Average Picture Level) which is the average luminance of the entire frame.
  • APL Average Picture Level
  • the synchronization timing detection unit 310 calculates the APL for the frame of the asynchronous video, and for the frame in which the difference from the average of the APLs of a plurality of consecutive frames before the frame is large, the frame The period corresponding to is detected as the period during which the video scene changes.
  • 4 and 5 are diagrams for explaining conventional adjustment processing.
  • the address control unit 320 sets a write address representing a frame stored in the frame memory 400 when a frame included in the input video (asynchronous video) is stored in the frame memory 400 according to the input frame rate.
  • the write address is counted up according to the frame output timing of the input frame rate.
  • the write address is reset to “0” when the number of frames that can be stored in the frame memory is exceeded.
  • the number of frames that can be stored in the frame memory 400 is eight frames. Therefore, any of the numbers “0” to “7” is set as the address.
  • the address control unit 320 reads the frame from the frame memory 400 in synchronization with the output frame rate and outputs it. At this time, the address control unit 320 reads a frame from the frame memory 400 by designating the write address set at the time of storing the frame as a read address. The read address is counted up according to the frame output timing of the output frame rate.
  • phase difference the difference between the write address, the read address and the number of frames at the timing when the read address is counted up.
  • phase difference when the phase difference is “1”, it means that the read address is an address representing a frame one frame before the write address at the same timing.
  • the address control unit 320 performs frame skip processing based on whether the phase difference at the frame output timing of the output frame rate is a predetermined phase difference.
  • the predetermined phase difference is “1”.
  • the address control unit 320 When the input frame rate of asynchronous video is larger than the output frame rate, the address control unit 320 thins out a part of the frame and outputs it. Specifically, the address control unit 320 thins out and reads out the frames of the asynchronous video stored in the frame memory 400 and outputs them to the video output unit 500 in synchronization with the output frame rate. This process is called a frame skip process.
  • FIG. 4 is a diagram for explaining a conventional frame skip process.
  • Timing (1) in FIG. 4 is the first timing at which the address control unit 320 starts outputting a frame.
  • the address control unit 320 sets the address “0” at which the phase difference is “1” which is a predetermined phase difference as the read address, A frame corresponding to the address “0” is read from the frame memory 400 and output.
  • the read address is set to “2” with respect to the write address “3”.
  • the read address counted up from the state at the timing (1) is “2” with respect to the write address “4”. That is, at the timing (3), the phase difference is “2” with respect to the predetermined phase difference “1”, and the phase difference is larger than the predetermined phase difference.
  • the address control unit 320 performs frame skip processing at timing (3). Specifically, the address control unit 320 skips the address “2”, sets “3” as a read address, reads the frame corresponding to the address “3” from the frame memory 400, and outputs the frame. That is, the frame corresponding to the address “2” is skipped.
  • the phase difference at the timing (4) in FIG. 5 is “1”, which is equal to the predetermined phase difference “1”.
  • the address control unit 320 outputs each frame of the asynchronous video according to the output frame rate by performing a frame skip process at a timing when the phase difference is larger than the predetermined phase difference.
  • the address control unit 320 when the input frame rate of asynchronous video is smaller than the output frame rate, the address control unit 320 repeatedly outputs the same frame. Specifically, the address control unit 320 repeatedly reads out the frame of the asynchronous video stored in the frame memory 400 and outputs it to the video output unit 500 in synchronization with the output frame rate. This process is called a frame repeat process.
  • FIG. 5 is a diagram for explaining a conventional frame repeat process.
  • Timing (1) in FIG. 5 is the first timing at which the address control unit 320 starts outputting a frame.
  • the address control unit 320 sets the address “0” at which the phase difference is “1” which is a predetermined phase difference as the read address, A frame corresponding to the address “0” is read from the frame memory 400 and output.
  • the read address is set to “2” with respect to the write address “3”.
  • the read address counted up from the state at the timing (2) is “3” with respect to the write address “3”. That is, at the timing (3), the phase difference is “0” with respect to the predetermined phase difference “1”, and the phase difference is smaller than the predetermined phase difference.
  • the address control unit 320 performs frame repeat processing at timing (3). Specifically, the address control unit 320 sets the address “2” as the read address again at the timing (3), reads the frame corresponding to the address “2” from the frame memory 400, and outputs it. That is, the frame corresponding to the address “2” is repeatedly output.
  • the phase difference at the timing (4) in FIG. 6 is “1”, which is equal to the predetermined phase difference “1”.
  • the address control unit 320 outputs each frame of the asynchronous video according to the output frame rate by performing a frame repeat process at a timing when the phase difference is smaller than the predetermined phase difference.
  • the address control unit 320 performs adjustment processing (frame skip processing and frame repeat) processing at regular intervals based on the phase difference, and synchronizes the input frame with the output frame rate. Output. For this reason, depending on the video displayed at the timing when the adjustment process is performed, the viewer may feel uncomfortable with the video.
  • the address control unit 320 performs an adjustment process (frame skip process, frame repeat process) on each frame of the asynchronous video during the adjustment process period detected by the synchronization timing detection unit 310 and outputs it. To do.
  • the address control unit 320 When the asynchronous video input frame rate is higher than the output frame rate, the address control unit 320 performs the frame skip processing as described above.
  • FIG. 6 is a diagram for explaining frame skip processing of the address control unit 320 according to Embodiment 1 of the present invention.
  • the address control unit 320 adjusts the frame output timing in addition to the conventional control for detecting whether or not the phase difference is a predetermined phase difference. Frame skip processing is performed based on whether or not it is included in the processing period.
  • the predetermined phase difference is “4”
  • the number of frames that can be stored in the frame memory 400 is eight frames.
  • the timing (1) of the period (a) in FIG. 6 is the first timing at which the address control unit 320 starts outputting a frame.
  • the address control unit 320 since the write address is “4”, the address control unit 320 reads the address “0” where the phase difference is “4” which is a predetermined phase difference.
  • the frame is set as an address, and the frame corresponding to the address “0” is read from the frame memory 400 and output.
  • the write address is counted up according to the input frame rate, and the read address is counted up according to the output frame rate.
  • the phase difference is “4” at any of the timings (1) to (3), and the address control unit 320 does not need to perform the frame skip process.
  • the input frame rate is larger than the output frame rate. Accordingly, when the time elapses without the address controller 320 performing frame skip processing, the phase difference between the write address and the read address increases.
  • the period (b) in FIG. 6 represents a state in which several frames have elapsed from the state of the period (a) in FIG. 6 and the phase difference between the write address and the read address has expanded.
  • the period (b) in FIG. 6 includes the adjustment process period detected by the synchronization timing detection unit 310, and the address control unit 320 performs the frame skip process in the adjustment process period.
  • the read address is set to “6” with respect to the write address “4”. That is, the phase difference is “6” with respect to the predetermined phase difference “4”, and the phase difference is larger than the predetermined phase difference.
  • the write address is “5”, and the read address counted up from the state of the timing (1) in the period (b) in FIG. 6 is “7”. . That is, the phase difference at timing (2) is “6”, which is larger than the predetermined phase difference “4”, and the timing (2) in the period (b) in FIG. It is included in the period detected as a period.
  • the address control unit 320 performs frame skip processing at the timing (2) of the period (b) in FIG. Specifically, the address control unit 320 skips the address “7”, sets “0” as a read address, reads the frame corresponding to the address “0” from the frame memory 400, and outputs the frame. That is, the frame corresponding to the address “7” is skipped.
  • the write address is “6”
  • the read address counted up from the state of the timing (2) in the period (b) in FIG. 6 is “1”.
  • the phase difference is “5”, which is larger than the predetermined phase difference “4”, and the timing (3) in the period (b) in FIG. Included in the adjustment process period. Therefore, at the timing (3) of the period (b) in FIG. 6, the address control unit 320 performs a frame skip process as the adjustment process. Specifically, the address control unit 320 skips the address “1”, sets the address “2” as a read address, reads out the frame corresponding to the address “2” from the frame memory 400, and outputs it. That is, the frame corresponding to the address “1” is skipped.
  • the phase difference at the timing (4) in the period (b) in FIG. 6 is “4”, and the predetermined phase difference “4”. Is equal to
  • the address control unit 320 performs frame skip processing to output each frame of the asynchronous video as an output frame. Output according to the rate.
  • the address control unit 320 skips and outputs one frame at a time as frame skip processing, but the address control unit 320 skips a plurality of frames at a time. May be output. That is, at the timing (2) of the period (b) in FIG. 6, the address control unit 320 skips the addresses “7” and “0”, sets “1” as the read address, and corresponds to the address “2”. A frame to be output may be output. In this case, two frames of addresses “7” and “0” are skipped at a time.
  • the number of frames that can be stored in the frame memory 400 is finite, and in the example of FIG. 6, it is 8 frames as described above. Therefore, when the adjustment process period is not detected for a long time and the frame skip process cannot be performed, the address control unit 320 may inevitably perform the frame skip process during a period other than the adjustment process period.
  • the period (c) in FIG. 6 is a diagram showing such a case.
  • the write address is “7”, and the read address is counted up from the state of the timing (1) and should be “7” originally.
  • the frame corresponding to the read address “7” does not exist in the frame memory 400 because a new frame is stored at the timing when the write address is counted up to “7”.
  • the address control unit 320 performs the frame skip process at the timing (2) of the period (c) in FIG. 6 that is not included in the adjustment process period. Specifically, the address control unit 320 skips the address “7”, sets the address “0” as the read address, reads out the frame corresponding to the address “0” from the frame memory 400, and outputs it.
  • the address control unit 320 When the input frame rate of asynchronous video is smaller than the output frame rate, the address control unit 320 performs frame repeat processing.
  • FIG. 7 is a diagram for explaining frame repeat processing of the address control unit 320 according to Embodiment 1 of the present invention.
  • the address control unit 320 has a frame output timing in the adjustment processing period in addition to the conventional control for detecting whether or not the phase difference is a predetermined phase difference. Frame repeat processing is performed based on whether or not it is included.
  • the predetermined phase difference is “4”, and the number of frames that can be stored in the frame memory 400 is eight frames.
  • the timing (1) of the period (a) in FIG. 7 is the first timing at which the address control unit 320 starts to output a frame.
  • the address control unit 320 since the write address is “4”, the address control unit 320 reads the address “0” where the phase difference is “4” which is a predetermined phase difference.
  • the frame is set as an address, and the frame corresponding to the address “0” is read from the frame memory 400 and output.
  • the write address is counted up according to the input frame rate, and the read address is counted up according to the output frame rate.
  • the phase difference is “4” at any timing of (1) to (3), and the address control unit 320 does not need to perform frame repeat processing.
  • the input frame rate is smaller than the output frame rate. Accordingly, when the time elapses without the address control unit 320 performing the frame repeat process, the phase difference between the write address and the read address becomes small.
  • the period (b) in FIG. 7 represents a state in which the frame repeat process is not performed from the state in the period (a) in FIG. 7 and a time of several frames elapses and the phase difference between the write address and the read address is reduced.
  • the read address is set to “1” with respect to the write address “4”. That is, the phase difference is “3” with respect to the predetermined phase difference “4”, and the phase difference is smaller than the predetermined phase difference.
  • the write address is “5”, and the read address counted up from the timing (1) in the period (b) in FIG. 7 is “2”. That is, the phase difference is “3” at the timing (2), which is smaller than the predetermined phase difference “4”, and the synchronization timing detection unit 310 performs the adjustment process at the timing (2) in FIG. It is included in the period detected as a period. Therefore, the address control unit 320 performs a frame repeat process at the timing (2) of the period (b) in FIG. Specifically, the address control unit 320 sets the address “1” as the read address again, reads out the frame corresponding to the address “1” from the frame memory 400, and outputs the frame. That is, the frame corresponding to the address “1” is output again.
  • the phase difference at the timing (3) of the period (b) is “4”, which is equal to the predetermined phase difference “4”.
  • the address control unit 320 performs frame repeat processing to output each frame of the asynchronous video as an output frame. Output according to the rate.
  • the address control unit 320 repeatedly outputs a frame once as a frame repeat process, but the address control unit 320 outputs a plurality of the same frames. You may output continuously.
  • the number of frames that can be stored in the frame memory 400 is finite, and in the example of FIG. 7, it is 8 frames as described above. Therefore, when the adjustment process period is not detected for a long time and the frame repeat process cannot be performed, the address control unit 320 may inevitably perform the frame repeat process during a period other than the adjustment process period.
  • FIG. 7 (C) of FIG. 7 is a figure which shows such a case.
  • the frame repeat process is not performed, and the phase difference between the write address and the read address is small. Since the write address is “4” while the read address is “4”, the phase difference is “0”.
  • the write address is “4”, and the read address is counted up from the state of the timing (1) and should be “5” originally.
  • the write address is not counted up to “5”. That is, the frame corresponding to the address “5” at the timing (2) is not yet stored, and the frame corresponding to the read address “5” does not exist in the frame memory 400.
  • the address control unit 320 performs the frame repeat process at the timing (2) of the period (c) in FIG. 7 that is not included in the adjustment process period. Specifically, the address control unit 320 sets the address “4” as the read address again, reads out the frame corresponding to the address “4” from the frame memory 400, and outputs it.
  • FIG. 8 is a flowchart of the adjustment process of the frame synchronization unit 300 according to the first embodiment.
  • the adjustment process of the frame synchronization unit 300 that eliminates the difference between the input frame rate and the output frame rate in the first embodiment is as follows.
  • the frame synchronization unit 300 acquires the input frame of the input video acquired by the video acquisition unit 100 (S110).
  • the frame synchronization unit 300 acquires the output frame rate determined by the output frame rate determination unit 200 (S120).
  • the synchronization timing detection unit 310 detects an adjustment process period, which is a period during which the adjustment process performed by the address control unit 320 is difficult for the viewer to perceive the asynchronous video (S130).
  • the address control unit 320 outputs the input frame according to the output frame rate based on the phase difference.
  • the address control unit 320 performs the adjustment process to display the frame. Output (S160).
  • the address control unit 320 When the timing at which the deviation occurs is not included in the adjustment processing period (No in S140), the address control unit 320 outputs the frame as it is without performing the adjustment processing (S160).
  • the frame adjustment processing for eliminating the deviation between the input frame rate and the output frame rate is performed during the period when the video motion is small. It is performed in a period corresponding to the switching of video scenes. As a result, a smooth and high-definition video display is realized in which the viewer does not feel a sense of discomfort in the video.
  • the configuration and operation of the video signal processing apparatus 10 according to the second embodiment of the present invention are different from the first embodiment only in the configuration and operation of the frame synchronization unit 300. Therefore, the configuration and adjustment processing of the frame synchronization unit 300 according to Embodiment 2 will be described in detail below.
  • FIG. 9 is a block diagram showing the configuration of the frame synchronization unit 300 according to Embodiment 2 of the present invention.
  • the frame synchronization unit 300 includes an address control unit 320 and an interpolation frame generation unit 360.
  • the address control unit 320 performs a frame skip process or a frame repeat process on the input frame, which is each frame of the asynchronous video, for a predetermined period, and outputs it to the interpolation frame generation unit 360 as a read frame.
  • the address control unit 320 also outputs to the interpolation frame generation unit 360 the preceding and following frames that are temporally preceding and following the read frame.
  • the interpolation frame generation unit 360 generates an interpolation frame using the read frame and the previous and next frames output from the address control unit 320. In addition, the interpolation frame generation unit 360 replaces a frame included in a predetermined period of the read frame with the interpolation frame and outputs it as an output frame. Details of the interpolation frame generation method of the interpolation frame generation unit 360 will be described later.
  • FIG. 10 is a diagram for explaining adjustment processing of the address control unit 320 and the interpolation frame generation unit 360 when the input frame rate is smaller than the output frame rate.
  • the basic operation of storing a frame in the frame memory 400 of the address control unit 320 is as described in the first embodiment. As shown in FIG. 10, the write address is counted up according to the input frame rate, and the read address is counted up according to the output frame rate.
  • the address control unit 320 detects the timing for performing the frame repeat process based on whether or not the phase difference at the frame output timing of the output frame rate is a predetermined phase difference.
  • the predetermined phase difference is “1”
  • the number of frames that can be stored in the frame memory 400 is eight frames.
  • the frame corresponding to the input frame address “0” is expressed as frame [0].
  • the frame [1] is a frame corresponding to the address “1” of the input frame
  • the frame [2] is a frame corresponding to the address “2” of the input frame.
  • the interpolation frame generation unit 360 uses the interpolation frame to mitigate changes in the time distance between frames. Specifically, for example, the interpolation frame generation unit 360 outputs timings (4), (5), (() that are output timings of output frames corresponding to the frames [2], [2], [3] of the read frame. In 6), interpolation frames [1.8], [2.5], and [3.2] are output, respectively.
  • the output frame uses the interpolation frame, and the frames [0], [1], [1.8], [2.5], [3.2], [4], [5]. It becomes. Thereby, since the change of the time distance between frames is relieved, the video display which a viewer does not feel uncomfortable is realized.
  • the address control unit 320 detects a replacement frame to be replaced with an interpolation frame in advance from the read frame from the input frame rate and the output frame rate of the asynchronous video.
  • the frame [2] output by the frame repeat process and the immediately preceding and immediately following frames are set as the replacement frame. That is, the replacement frame is the frames [2], [2], and [3] of the read frame.
  • the address control unit 320 determines an interpolation frame generated by the interpolation frame generation unit 360.
  • the interpolated frames are set to frames [1.8], [2.5], and [3.2] in order to mitigate changes in the temporal distance between frames.
  • Timing (1) in FIG. 10 is the first timing at which the address control unit 320 starts to output a read frame.
  • the write address is “1” and the predetermined phase difference is “1”. Therefore, the address control unit 320 sets the read address to “0”, reads the frame [0] corresponding to the address “0” from the frame memory 400 as a read frame, and outputs it to the interpolation frame generation unit 360.
  • the read address is counted up to “1”, and the phase difference is equal to the predetermined phase difference. For this reason, the frame repeat process is not performed, and the output read frame is frame [1].
  • Timing (2) is a timing at which the interpolation frame generation unit 360 starts to output an output frame.
  • the interpolation frame generation unit 360 outputs the frame [0] output from the address control unit 320 at timing (1) to the video output unit 500 as an output frame.
  • the read address is counted up to “2”, and the phase difference is “1” equal to a predetermined phase difference. Therefore, the read frame output at timing (3) is frame [2].
  • the frame [2] output from the address control unit 320 at timing (3) is a frame to be replaced.
  • the readout frame at timing (3) is replaced with the interpolation frame [1.8] by the interpolation frame generation unit 360.
  • the interpolation frame [1.8] is generated from the frames [1] and [2] by linear interpolation described later.
  • the address control unit 320 sets the address “1” corresponding to the immediately preceding frame as the front and rear addresses in addition to the address “2”.
  • the front-rear address is an address for the address control unit 320 to read a frame from the frame memory 400 so that the interpolation frame generation unit 360 generates an interpolation frame.
  • frame [1] is output to the interpolated frame generation unit 360 as the previous and subsequent frames.
  • the interpolation frame generation unit 360 outputs the frame [1] output from the address control unit 320 at timing (2).
  • the phase difference expands to “2” at timing (4). Therefore, at the timing (4), the frame synchronization unit 300 performs the frame repeat process, sets the address “2” as the read address again, and outputs the frame [2] as the read frame.
  • the read frame output at timing (4) is a frame to be replaced and is replaced with frame [2.5]. Therefore, the address control unit 320 sets the next address “3” after the address “2” as the previous and next addresses, and outputs the frame [3] to the interpolated frame generation unit 360 as the previous and next frames.
  • the interpolation frame generation unit 360 linearly interpolates the frames [1] and [2] output from the address control unit 320 at timing (3). 8 "is generated and output as an output frame. The linear interpolation will be described later.
  • the read address is counted up to “3”, and the phase difference is “1” equal to a predetermined phase difference. Therefore, frame [3] is output as a read frame.
  • the read frame is a frame to be replaced, and is replaced with the frame [3.2]. Therefore, frame [4.5] is output as the previous and subsequent frames.
  • the interpolation frame generation unit 360 generates the interpolation frame [2.5] from the frames [2] and [3] output from the address control unit 320 at timing (4), and outputs the output frame. Output as.
  • the read address is counted up to “3”, and the phase difference is “1” equal to a predetermined phase difference. Therefore, frame [3] is output as a read frame. Further, since the read frame is not a frame to be replaced, the preceding and following addresses are not set.
  • the interpolation frame generation unit 360 generates an interpolation frame [3.2] from the frames [3] and [4] output from the address control unit 320 at timing (5), and outputs an output frame. Output as.
  • the address control unit 320 outputs only the read frame at the timing when the normal read frame is output, and the read frame (replaced frame) and the preceding and following frames at the timing when the replaced frame is output. Is output.
  • the interpolation frame generation unit 360 outputs the read frame as it is as an output frame at the timing after one frame.
  • the interpolation frame generation unit 360 generates and outputs an interpolation frame from the read frame and the previous and next frames at a timing one frame later.
  • the interpolation frame is generated by performing linear interpolation using two frames.
  • the interpolation frame [1.8] is generated by linear interpolation using the motion vector obtained from the frame [1] and the frame [2].
  • the interpolation frame generation unit 360 divides, for example, the frame [1] and the frame [2] of the read frame into several small regions.
  • the interpolation frame generation unit 360 obtains the SAD between one small area of the frame [2] (hereinafter referred to as a small area A) and each small area of the frame [1]. Subsequently, the interpolation frame generation unit 360 obtains a small area (hereinafter, referred to as a small area A ′) of the frame [1] corresponding to the smallest SAD value among the SADs obtained by the number of small areas. Further, the interpolation frame generation unit 360 uses the small area A and the small area A ′ to obtain a motion vector A that represents a change in position from the small area A to the small area A ′.
  • the interpolation frame generation unit 360 includes a small area (hereinafter, a small area) at a position obtained by the motion vector A ⁇ 0.2 from the position of the small area A among the small areas included in the interpolation frame [1.8]. Region A ′′).
  • the luminance of each pixel in the small area A ′′ is obtained by proportionally distributing the luminance of each pixel in the small area A and the luminance of each pixel in the small area A ′.
  • the luminance of the small area A ′′ of the interpolation frame [1.8] is obtained.
  • the luminance of the other small areas of the interpolation frame [1.8] is obtained by obtaining the motion vectors. As a result, an interpolation frame [1.8] is generated.
  • the interpolation frame [2.5] is generated by linearly interpolating from the frame [2] and the frame [3] using a motion vector.
  • the interpolation frame [3.2] is generated by linearly interpolating from the frame [3] and the frame [4] using a motion vector.
  • FIG. 11 is a diagram for explaining the adjustment processing of the address control unit 320 and the interpolation frame generation unit 360 when the input frame rate is larger than the output frame rate.
  • the interpolation frame generation unit 360 performs interpolation at each timing of outputting frames [3] and [4] of the read frame among the output timings of the output frame. Frames [2.3] and [3.7] are output.
  • the output frames are frames [0], [1], [2.3], [3.7], [5], [6],... Using the interpolation frame.
  • the frame control procedure of the address control unit 320 and the interpolation frame generation method are the same as when the input frame rate is smaller than the output frame rate.
  • FIG. 12 is a flowchart showing the elimination of the synchronization error in the second embodiment.
  • the adjustment process of the frame synchronization unit 300 in the second embodiment is as follows.
  • the frame synchronization unit 300 acquires the input frame of the input video acquired by the video acquisition unit 100 (S210).
  • the frame synchronization unit 300 acquires the output frame rate determined by the output frame rate determination unit 200 (S220).
  • the address control unit 320 detects a frame to be replaced based on the input frame rate and the output frame rate (S230).
  • the address control unit 320 outputs the input frame as a read frame according to the output frame rate based on the phase difference (S240).
  • the address control unit 320 When the read frame is a frame to be replaced (YES in S250), the address control unit 320 outputs the previous and next frames (S260).
  • the interpolation frame generation unit 360 generates an interpolation frame and outputs it as an output frame when the read frame and the preceding and following frames are acquired (S270).
  • the interpolation frame generation unit 360 outputs the read frame as an output frame as it is (S280).
  • the frame synchronization unit 300 does not output a frame specified by a read address as it is, but generates an interpolated frame, performs replacement processing, and outputs the interlaced frames. Improves temporal continuity of Thereby, smooth and high-quality video display is realized. Also, since not all frames are replaced with interpolation frames, but only necessary portions are replaced with interpolation frames, the load on signal processing is small, and synchronization deviation can be corrected effectively.
  • Each of the above devices is specifically a computer system including a microprocessor, a ROM, a RAM, a hard disk unit, a display unit, a keyboard, a mouse, and the like.
  • a computer program is stored in the RAM or hard disk unit.
  • Each device achieves its functions by the microprocessor operating according to the computer program.
  • the computer program is configured by combining a plurality of instruction codes indicating instructions for the computer in order to achieve a predetermined function.
  • a part or all of the components constituting each of the above devices may be configured by one system LSI (Large Scale Integration).
  • the system LSI is a super multifunctional LSI manufactured by integrating a plurality of components on a single chip, and specifically, a computer system including a microprocessor, a ROM, a RAM, and the like. .
  • a computer program is stored in the RAM.
  • the system LSI achieves its functions by the microprocessor operating according to the computer program.
  • a part or all of the constituent elements constituting each of the above devices may be constituted by an IC card or a single module that can be attached to and detached from each device.
  • the IC card or the module is a computer system including a microprocessor, a ROM, a RAM, and the like.
  • the IC card or the module may include the super multifunctional LSI described above.
  • the IC card or the module achieves its function by the microprocessor operating according to the computer program. This IC card or this module may have tamper resistance.
  • the present invention may be the method described above. Further, the present invention may be a computer program that realizes these methods by a computer, or may be a digital signal composed of the computer program.
  • the present invention also provides a computer-readable recording medium such as a flexible disk, hard disk, CD-ROM, MO, DVD, DVD-ROM, DVD-RAM, BD (Blu-ray Disc). ), Recorded in a semiconductor memory or the like. Further, the digital signal may be recorded on these recording media.
  • a computer-readable recording medium such as a flexible disk, hard disk, CD-ROM, MO, DVD, DVD-ROM, DVD-RAM, BD (Blu-ray Disc).
  • the computer program or the digital signal may be transmitted via an electric communication line, a wireless or wired communication line, a network represented by the Internet, a data broadcast, or the like.
  • the present invention may be a computer system including a microprocessor and a memory, the memory storing the computer program, and the microprocessor operating according to the computer program.
  • the program or the digital signal is recorded on the recording medium and transferred, or the program or the digital signal is transferred via the network or the like, and executed by another independent computer system. It is good.
  • the video signal processing device has been described based on the embodiment and the modifications thereof.
  • the frame adjustment processing for eliminating the difference between the input frame rate and the output frame rate is performed during the period when the video motion is low, the video motion is high, and the video scene is switched. Is performed in a period corresponding to.
  • interpolated frames are generated, replaced and output, thereby improving temporal continuity between frames.
  • the video signal processing apparatus 10 is realized as the television 700 shown in FIG.
  • the specific configuration of the video display unit 600 is not particularly limited, and is, for example, a liquid crystal display, a plasma display, an organic EL (Electro Luminescence) display, or the like.
  • the video acquisition unit 100 acquires a video from a television broadcast, a DVD (Digital Versatile Disc) player 710 and a set top box 720 shown in FIG.
  • the video signal processing apparatus 10 may be realized as a DVD player 710.
  • the video acquisition unit 100 acquires video from the inserted DVD.
  • the acquisition source of the video is not limited to the DVD, and can be acquired from any recording medium such as Blu-ray Disc, HDD (Hard Disk Drive) and the like.
  • the video signal processing apparatus 10 may be realized as a set top box 720.
  • the video acquisition unit 100 acquires video from cable television broadcasting or the like.
  • this invention is not limited to these embodiment or its modification. Unless it deviates from the gist of the present invention, various modifications conceived by those skilled in the art are applied to the present embodiment or the modification thereof, or a form constructed by combining different embodiments or components in the modification. It is included within the scope of the present invention.
  • the viewer when a plurality of images with different frame rates are displayed in synchronization, the viewer can feel smooth and high-quality images without feeling uncomfortable, and has a function of displaying a plurality of images.
  • the present invention is useful as a video signal processing device and a video signal processing method used for a display device such as a television or a personal computer.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

L'invention concerne un dispositif de traitement de signaux d'image comprenant une unité d'acquisition d'image (100) permettant d'acquérir séquentiellement une pluralité de trames contenues dans des images d'entrée respectives à une fréquence de trame d'entrée correspondante, une unité de détermination de fréquence de trame de sortie (200) destinée à déterminer une fréquence de trame de sortie, une unité de synchronisation de trames (300) destinée à fournir séquentiellement en sortie la pluralité de trames pour des images d'entrée respectives obtenues par l'unité d'acquisition d'images à la fréquence de trame de sortie, et une unité de sortie d'images (500) destinée à fournir séquentiellement en sortie une trame composite obtenue en composant chaque trame fournie en sortie de manière synchrone à la fréquence de trame de sortie en provenance de l'unité de synchronisation de trames (300), l'unité de synchronisation de trames (300) effectuant un traitement de réconciliation qui élimine l'écart entre la fréquence de trame d'entrée et la fréquence de trame de sortie afin que cette différence ne soit pas décelable par un observateur, par rapport à des images synchrones, la fréquence de trame d'entrée correspondante entre la pluralité d'images d'entrée étant différente de la fréquence de trame de sortie.
PCT/JP2011/007062 2011-02-10 2011-12-19 Dispositif de traitement de signaux d'image et procédé de traitement de signaux d'image Ceased WO2012107985A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113067960A (zh) * 2021-03-16 2021-07-02 合肥合芯微电子科技有限公司 影像插补方法、装置和存储介质

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6336083B2 (ja) * 2014-07-29 2018-06-06 三菱電機株式会社 映像情報再生装置及び再生方法
KR101553846B1 (ko) 2014-12-16 2015-09-17 연세대학교 산학협력단 영상 합성을 위한 프레임 동기화 장치 및 그 방법
KR101687104B1 (ko) * 2015-06-03 2016-12-16 어드밴인터내셔널코프 수직 동기 지연 계산 방법 및 장치
GB2547438B (en) * 2016-02-17 2019-07-03 Insync Tech Limited Method and apparatus for generating a video field/frame
JP7658442B2 (ja) * 2021-08-11 2025-04-08 日本電信電話株式会社 映像信号を合成する装置、方法及びプログラム
KR20230055506A (ko) 2021-10-19 2023-04-26 삼성전자주식회사 디스플레이 장치 및 그 제어 방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004048530A (ja) * 2002-07-15 2004-02-12 Matsushita Electric Ind Co Ltd フレームレート変換装置、及び変換情報多重装置
JP2005124167A (ja) * 2003-09-25 2005-05-12 Canon Inc フレームレート変換装置、それに用いられる追い越し予測方法、表示制御装置及び映像受信表示装置
JP2005341132A (ja) * 2004-05-26 2005-12-08 Toshiba Corp 映像データ処理装置及び処理方法
JP2006050230A (ja) * 2004-08-04 2006-02-16 Hitachi Ltd フレームレート変換方法、変換装置、画像信号記録装置および再生装置
JP2007318193A (ja) * 2006-05-23 2007-12-06 Hitachi Ltd 画像処理装置
JP2008236098A (ja) * 2007-03-19 2008-10-02 Hitachi Ltd 映像処理装置及び映像表示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004048530A (ja) * 2002-07-15 2004-02-12 Matsushita Electric Ind Co Ltd フレームレート変換装置、及び変換情報多重装置
JP2005124167A (ja) * 2003-09-25 2005-05-12 Canon Inc フレームレート変換装置、それに用いられる追い越し予測方法、表示制御装置及び映像受信表示装置
JP2005341132A (ja) * 2004-05-26 2005-12-08 Toshiba Corp 映像データ処理装置及び処理方法
JP2006050230A (ja) * 2004-08-04 2006-02-16 Hitachi Ltd フレームレート変換方法、変換装置、画像信号記録装置および再生装置
JP2007318193A (ja) * 2006-05-23 2007-12-06 Hitachi Ltd 画像処理装置
JP2008236098A (ja) * 2007-03-19 2008-10-02 Hitachi Ltd 映像処理装置及び映像表示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113067960A (zh) * 2021-03-16 2021-07-02 合肥合芯微电子科技有限公司 影像插补方法、装置和存储介质
CN113067960B (zh) * 2021-03-16 2022-08-12 合肥合芯微电子科技有限公司 影像插补方法、装置和存储介质

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