WO2012113645A1 - Ensemble boîtier de puce semi-conductrice et procédé de fabrication - Google Patents

Ensemble boîtier de puce semi-conductrice et procédé de fabrication Download PDF

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Publication number
WO2012113645A1
WO2012113645A1 PCT/EP2012/052057 EP2012052057W WO2012113645A1 WO 2012113645 A1 WO2012113645 A1 WO 2012113645A1 EP 2012052057 W EP2012052057 W EP 2012052057W WO 2012113645 A1 WO2012113645 A1 WO 2012113645A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
encapsulation
contact surface
lead frame
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2012/052057
Other languages
German (de)
English (en)
Inventor
Michael Zitzlsperger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of WO2012113645A1 publication Critical patent/WO2012113645A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/8506—Containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H10W70/427—Bent parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present invention relates to a package shape for a semiconductor chip, particularly an LED package having a semiconductor package
  • Connection contacts of the chip are connected by means of so-called bonding wires with the associated conductors of the lead frame.
  • This arrangement is in a potting compound or
  • terminal pads of a chip are usually all located on the same main side of the chip. Instead, at least one terminal pad on the
  • Rear side which is usually formed by the underside of a semiconductor substrate, and arranged there with a leading through the chip conductive connection
  • Main opposite sides of a chip are mainly used in stacking semiconductor chips to three-dimensional
  • connection pins which have a corresponding number of connection pins outside the housing and within of the housing have electrical connection surfaces
  • a heat conductor which has a connection pin outside the housing and within the housing a thermal
  • the chip is connected to one of its main surfaces with the thermal pad, and the electrical connections of the chip are connected by means of bonding wires to the electrical pads.
  • the object of the invention is a cost
  • the semiconductor chip package assembly includes a chip provided with electrical connection pads including at least a bottom terminal pad and an upper terminal pad.
  • Terminal contact surface is on one of the lower
  • Terminal contact surface opposite top of the chip arranged.
  • the chip is mounted on a lead frame having a lower part and an upper part electrically separated therefrom. In a lower contact, the lower terminal pad of the chip is electrically connected to the lower part of the lead frame, and in an upper contact, the upper terminal pad of the chip is electrically connected to the upper part of the lead frame.
  • the contacting of the chip takes place in particular bond wire free.
  • the chip is in direct contact with the parts of the lead frame.
  • the chip can then be clamped between the two parts and be mechanically fixed in this way.
  • a connection material such as a solder or an electrically conductive adhesive to be present between the parts of the leadframe and the chip.
  • Semiconductor chip package assembly is a share of
  • Lead frame arranged in an encapsulation of a potting compound and the contact surface is free of the encapsulation.
  • Semiconductor chip package assembly is a share of
  • Lead frame arranged in an encapsulation of a potting compound and the encapsulation points over the top of the Chips an opening so that at least a portion of the top of the chip is not covered by the encapsulation.
  • the encapsulation in particular
  • radiopaque for example, radiation-reflecting or radiation-absorbing.
  • the chip can then be covered on its upper side, in the region of the opening, by another, radiation-permeable potting material which in places can border directly on the radiopaque encapsulation.
  • Potting material and encapsulation may be formed from the same base material into which filler particles are incorporated.
  • the base material is a silicone or the like
  • Base material contains silicone. Encapsulation and
  • the upper part of the lead frame leaves an uncovered from the encapsulation region of the top of the chip.
  • the upper part of the lead frame encloses a not covered by the encapsulation region of the top of the chip frame-shaped. This makes it possible in particular for an electric current to be impressed particularly uniformly in the chip. The electric current is then not only impressed into this via a single bonding pad, which is arranged, for example, in a corner of the chip, but an impression is made along the entire chip edge.
  • Semiconductor chip package assembly is the chip Optoelectronic device and the opening of the encapsulation is for entry or exit of
  • the chip is a light-emitting diode chip, a photodiode chip or a laser diode chip.
  • Semiconductor chip package arrangement corresponds to a vertical dimension of the encapsulant, measured perpendicular to the terminal pads, of the sum of the thicknesses of the chip, the bottom portion of the leadframe, and the top portion of the package
  • the thickness of the semiconductor chip package arrangement is then predetermined essentially by the thickness of the chip.
  • the thickness of the semiconductor chip package assembly can be made extremely small.
  • a substrateless diode is a substrateless diode
  • LED chip which is neither a growth substrate for
  • the LED chip still has a carrier.
  • the LED chip then consists of the epitaxially grown layers and eventual
  • Terminal contact surface and an upper
  • Terminal contact surface is provided for electrical connection, wherein the upper terminal contact surface is disposed on a lower terminal contact surface opposite the top of the chip. It also becomes a ladder frame provided, which has a lower part and a separate upper part. An electrically conductive lower contact is between the lower
  • Terminal contact surface of the chip and the lower part of the lead frame made and an electrically conductive upper contact is made between the upper terminal contact surface of the chip and the upper part of the lead frame.
  • an encapsulation is produced by providing the leadframe with a potting compound.
  • An area of the upper side of the chip or a contact area on the lower part of the leadframe can hereby be left free.
  • Contact surface may be provided in particular on the side remote from the chip and from the lower contact side of the lower part of the lead frame.
  • FIG. 1 shows a schematic representation of a
  • FIG. 2 shows a schematic illustration of a further exemplary embodiment in a cross section according to FIG. 1.
  • FIG. 3 shows a schematic representation of another
  • Figure 4 shows a schematic plan view of the
  • FIG. 1 shows a schematic cross section through an embodiment of the semiconductor chip package arrangement.
  • the chip 1 is arranged on a lower part 5 of the leadframe.
  • a lower terminal contact surface 2 of the chip 1 is connected in an electrically conductive manner to the lower part 5 of the leadframe by means of a lower contact 11.
  • the upper side 4 of the chip 1 may in particular be a main side of the chip 1, on which one or more components or functional elements or components of an integrated circuit
  • the opposite main side of the chip 1, which is provided with the lower terminal contact surface 2 may for example be the back side of the chip 1, in particular the underside of a semiconductor substrate.
  • a portion of the leadframe 5, 6 is in an encapsulation 7 arranged.
  • the encapsulation 7 forms a protective and mechanically stabilizing housing and is therefore
  • the encapsulation 7 may consist of a
  • Lead frame 5, 6 and the chip 1 are at least partially surrounded.
  • Such encapsulation 7 is of
  • Semiconductor chip packages known per se and can be prepared for example by an injection molding process.
  • connecting conductor 9 of the lead frame 5, 6 are located outside the encapsulation 7 and are kept free in the manufacture of the encapsulation 7 of the potting compound or molding compound.
  • the undersides of the encapsulation 7 and the connection conductor 9 are flat and within the same plane
  • connection conductors 9 may differ from the examples shown in the figures.
  • the connection conductors 9 may be bent or angled several times, for example, or point in different directions.
  • the encapsulation 7 may have an opening 8 in which the upper side 4 of the chip 1 is at least partially free. If the upper part 6 of the lead frame as in the
  • Embodiment of Figure 1 is recessed in the region of this opening 8, a corresponding area remains the
  • Top 4 of the chip 1 uncovered. If the chip 1 contains an optoelectronic component, the free area of the top 4 for entry or exit
  • electromagnetic radiation in particular for incident light or light emission, be provided.
  • LED light emitting diodes
  • Encapsulation 7 perpendicular to the plane occupied by the chip 1 and perpendicular to its terminal pads 2, 3 located. This dimension D is in the
  • the dimension D extends from the underside of the connecting conductor 9 to beyond the upper part 6 of the lead frame.
  • the encapsulation 7 thus partially covers the upper side of the upper part 6 of the
  • Lead frame and the opening 8 of the encapsulation 7 is deeper than the thickness of the upper part 6 of the lead frame.
  • FIG. 2 shows a further exemplary embodiment in a cross-section according to FIG. 1.
  • the vertical dimension D is lower than in the embodiment according to the figure 1. Die
  • Bottom of the encapsulation 7 connects to the side facing away from the chip 1 underside of the lower part 5 of the lead frame, so that the lower part 5 of the lead frame has a free contact surface 10 which is not covered by the encapsulation 7.
  • This contact surface 10 can be used, for example, to thermally conductively connect the lower part 5 of the leadframe to a heat sink.
  • the encapsulation 7 towers over here similar to the one
  • FIG. 3 shows a further exemplary embodiment in a cross section according to FIG. 1 or 2.
  • the vertical dimension D measured perpendicular to the terminal contact surfaces 2, 3 is even lower in the exemplary embodiment of FIG. 3 and corresponds to the sum the thicknesses of the chip 1, the lower part 5 of the lead frame and the upper part 6 of the
  • the further embodiment according to the figure 3 is thus particularly thin and meets a requirement compactest dimensions.
  • the lower part 5 of the lead frame has an outwardly-free contact surface 10 which allows connection to a heat sink.
  • the mechanical stability is determined in this embodiment mainly by the thickness of the lead frame 5, 6.
  • the thickness of the lead frame 5, 6 is therefore preferably to the
  • FIG. 4 shows a plan view of typical
  • Embodiments of the semiconductor chip package assembly Embodiments of the semiconductor chip package assembly.
  • Lead frame is recessed in the region of the opening 8 of the encapsulation 7 and surrounds a portion of the top 4 of the chip 1 frame-shaped. To illustrate the arrangement is in Figure 4, a narrow protruding edge of this
  • Example also frame-shaped upper
  • Terminal contact surface 3 located. Instead, the upper terminal contact surface 3 may be completely covered by the upper part 6 of the lead frame.
  • the recess in the upper part 6 of the lead frame and in the encapsulation 7 can in particular in a Semiconductor chip package with an optoelectronic chip 1 be provided to allow entry or exit of radiation.
  • the recess can be like
  • the luminous area of the chip 1 can be designed as desired by the geometric shape of the recess.
  • the described semiconductor chip package arrangement can be any type of semiconductor chip package arrangement.
  • Terminal contact surfaces 2, 3 of the chip 1 and the structure of the lead frame 5, 6 are connected to each other for this purpose
  • the electrical connections are formed directly by contacts 11, 12 without electrically conductive connections in the manner of interconnects or bonding wires, the spatial
  • the electrically conductive connection can be produced for example by soldering.
  • the solder material used for this purpose is electrically conductive and forms the contacts 11, 12 directly.
  • the chip packages can be separated in a cost-effective manner by punching.
  • the housing shape can

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L'invention concerne une puce (1) pourvue, sur ses côtés principaux opposés, de surfaces de contact de connexion (2, 3) électriques et montée sur une grille de connexion (5, 6). Dans un contact inférieur (11), une surface de contact de connexion inférieure (2) de la puce est connectée de façon électroconductrice à une partie inférieure (5) de la grille de connexion et, dans un contact supérieur (12), une surface de contact de connexion supérieure (3) de la puce est connectée de façon électroconductrice à une partie supérieure (6) de la grille de connexion séparée de la partie inférieure. Une encapsulation (7) peut ensuite être formée par injection de l'ensemble dans une matière de scellement.
PCT/EP2012/052057 2011-02-21 2012-02-07 Ensemble boîtier de puce semi-conductrice et procédé de fabrication Ceased WO2012113645A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011011861A DE102011011861A1 (de) 2011-02-21 2011-02-21 Halbleiterchipgehäuseanordnung und Herstellungsverfahren
DE102011011861.6 2011-02-21

Publications (1)

Publication Number Publication Date
WO2012113645A1 true WO2012113645A1 (fr) 2012-08-30

Family

ID=45592378

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2012/052057 Ceased WO2012113645A1 (fr) 2011-02-21 2012-02-07 Ensemble boîtier de puce semi-conductrice et procédé de fabrication

Country Status (2)

Country Link
DE (1) DE102011011861A1 (fr)
WO (1) WO2012113645A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230094566A1 (en) * 2021-09-30 2023-03-30 Infineon Technologies Ag Chip Package with Contact Clip

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002050729A (ja) * 2000-07-31 2002-02-15 Rohm Co Ltd リードフレーム、半導体装置の製造方法および半導体装置
US6396127B1 (en) * 1998-09-25 2002-05-28 International Rectifier Corporation Semiconductor package
US20040164395A1 (en) * 2001-01-12 2004-08-26 Rohm Co., Ltd. Surface-mounting semiconductor device and method of making the same
US20050161777A1 (en) * 2000-07-31 2005-07-28 Yoshitaka Horie Method of making wireless semiconductor device, and leadframe used therefor
US20060043618A1 (en) * 2004-08-30 2006-03-02 Renesas Technology Corp. Semiconductor device
US20060138532A1 (en) * 2004-12-24 2006-06-29 Masahide Okamoto Semiconductor device and manufacturing method of the same
DE102006035876A1 (de) 2006-08-01 2008-02-07 Infineon Technologies Ag Chip-Modul, Verfahren zur Herstellung eines Chip-Moduls und Mehrfachchip-Modul
EP2093793A2 (fr) * 2008-02-22 2009-08-26 Renesas Technology Corp. Procédé de fabrication d'un dispositif semi-conducteur

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3938177A (en) * 1973-06-25 1976-02-10 Amp Incorporated Narrow lead contact for automatic face down bonding of electronic chips
JP2007235103A (ja) * 2006-01-31 2007-09-13 Sanyo Electric Co Ltd 半導体発光装置
DE102007030129A1 (de) * 2007-06-29 2009-01-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Mehrzahl optoelektronischer Bauelemente und optoelektronisches Bauelement

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6396127B1 (en) * 1998-09-25 2002-05-28 International Rectifier Corporation Semiconductor package
JP2002050729A (ja) * 2000-07-31 2002-02-15 Rohm Co Ltd リードフレーム、半導体装置の製造方法および半導体装置
US20050161777A1 (en) * 2000-07-31 2005-07-28 Yoshitaka Horie Method of making wireless semiconductor device, and leadframe used therefor
US20040164395A1 (en) * 2001-01-12 2004-08-26 Rohm Co., Ltd. Surface-mounting semiconductor device and method of making the same
US20060043618A1 (en) * 2004-08-30 2006-03-02 Renesas Technology Corp. Semiconductor device
US20060138532A1 (en) * 2004-12-24 2006-06-29 Masahide Okamoto Semiconductor device and manufacturing method of the same
DE102006035876A1 (de) 2006-08-01 2008-02-07 Infineon Technologies Ag Chip-Modul, Verfahren zur Herstellung eines Chip-Moduls und Mehrfachchip-Modul
EP2093793A2 (fr) * 2008-02-22 2009-08-26 Renesas Technology Corp. Procédé de fabrication d'un dispositif semi-conducteur

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230094566A1 (en) * 2021-09-30 2023-03-30 Infineon Technologies Ag Chip Package with Contact Clip

Also Published As

Publication number Publication date
DE102011011861A1 (de) 2012-08-23

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