WO2012120694A1 - Procédé de fabrication de boîtier de niveau de tranche et boîtier de niveau de tranche - Google Patents

Procédé de fabrication de boîtier de niveau de tranche et boîtier de niveau de tranche Download PDF

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Publication number
WO2012120694A1
WO2012120694A1 PCT/JP2011/056251 JP2011056251W WO2012120694A1 WO 2012120694 A1 WO2012120694 A1 WO 2012120694A1 JP 2011056251 W JP2011056251 W JP 2011056251W WO 2012120694 A1 WO2012120694 A1 WO 2012120694A1
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WIPO (PCT)
Prior art keywords
wafer
groove
level package
manufacturing
wafer level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2011/056251
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English (en)
Japanese (ja)
Inventor
彰彦 佐野
孝明 宮地
知範 積
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Omron Corp
Original Assignee
Omron Corp
Omron Tateisi Electronics Co
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Publication date
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Publication of WO2012120694A1 publication Critical patent/WO2012120694A1/fr
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Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a wafer level package manufacturing method and a wafer level package, and more particularly to a wafer level package manufacturing method and a wafer level package capable of reducing dicing.
  • a mold package has been mainly used as a packaging method for semiconductor devices, but in recent years, a wafer level package capable of reducing the package cost and reducing the size of the package has expanded the market share.
  • a wafer level package is completed by dicing into individual devices by dicing.
  • dicing is performed after the first wafer and the second wafer are bonded. At that time, warpage occurs due to a difference in thermal expansion coefficient between the first wafer and the second wafer or a stress unique to the wafer, so that dicing in the presence of warpage deteriorates the wafer yield and product yield. A problem occurs.
  • FIGS. 8A to 8E after the semiconductor wafer 101 and the cap wafer 103 are bonded, A half cut 104 is performed along the scribe line from the semiconductor wafer 101 or cap wafer 103 side, and the chips in the horizontal direction are partially divided.
  • the half-cut 104 is inserted in the middle of the cap wafer 103 shown in FIG. 8A to the interface between the cap wafer 103 and the bonding layer 102 shown in FIG. 8B, as shown in FIG.
  • a plurality of surface acoustic wave device patterns 202 are formed on the surface of the piezoelectric substrate 201.
  • the step of removing the protective body 204 at the portion irradiated with the laser beam 205 to form the protective body removing portion 207 and the back surface side of the piezoelectric substrate 201 are ground by the grinder 208 to thin the piezoelectric substrate 201. It comprises a process and a process of separating each device in the modified region 206.
  • the surface acoustic wave device pattern 202 is surrounded and spaced from the outer periphery when separated into individual pieces.
  • the side wall 211 is provided, the excitation space 203 is covered, and a top plate 212 is provided that is spaced from the outer periphery to the entire periphery when separated into individual pieces, and is connected to the surface acoustic wave device pattern 202 and externally provided.
  • a connection electrode 213 for extracting an electric signal is provided on the first substrate, and the entire first surface side of the piezoelectric substrate 201 is covered with a protective body 204 made of an epoxy resin. Further, in the process of separating each device in the modified region 206, the pickup sheet 220 is attached to the piezoelectric substrate 201, and the pickup sheet 220 is stretched to be separated in the modified region 206. .
  • the laser beam 205 is condensed and the modified region 206 is provided in the piezoelectric substrate 201 to be separated into pieces.
  • the protective body removing portion 207 can be formed by condensing the laser beam 205 on the epoxy resin constituting the protective body 204 serving as a cap. Further, the device can be separated at the same time during the grinding process for thinning the piezoelectric substrate 201.
  • the device chip 301 is hermetically sealed with a sealing frame 302 made of resin.
  • the cap wafer 320 is bonded to the device wafer 310 on which the sealing frame 302 is formed, and then the sealing frame 302. 302 is divided into individual pieces by dicing.
  • the device chip 301 is isolated by the sealing frame 302, even when the sealing frames 302 and 302 are diced, the occurrence of cracks due to the dicing processing is prevented from affecting the device chip 301.
  • the wafer yield and the product yield are improved.
  • a scribe line that separates a plurality of semiconductor devices formed on a semiconductor substrate 401 individually.
  • a trench 402 for use and a through-hole trench 403 for forming a through-hole wiring in the semiconductor device are formed by etching using an etching mask 404.
  • the width of the scribe line groove 402 is made smaller than the width of the through hole groove 403.
  • the through hole groove 403 is penetrated by cutting the semiconductor substrate 401 to a thickness that reaches the bottom surface of the through hole groove 403 from the back surface to form a thinned semiconductor substrate 405.
  • the back metal wiring board 406 and the metal wiring 407 are formed.
  • a sheet 408 having adhesiveness and stretchability is attached to the back surface of the thinned semiconductor substrate 405, and along the scribe line groove 402 as shown in FIG. 11 (e). Then, the thinned semiconductor substrate 405 and the backside metal wiring board 406 are cleaved at the scribe line 411 using the break device 410, and the sheet 408 is stretched and separated for each semiconductor device as shown in FIG. To do.
  • This provides a method of manufacturing a semiconductor device that increases the number of devices that can be obtained.
  • Japanese Patent Publication Japanese Unexamined Patent Application Publication No. 2009-177034 (released on August 6, 2009)” Japanese Patent Publication “Japanese Patent Laid-Open No. 2010-213144 (published on September 24, 2010)” US Patent Application Publication No. 2009/0194861 (published Aug. 6, 2009) Japanese Patent Publication “Japanese Laid-Open Patent Publication No. 2002-198327 (released on July 12, 2002)”
  • Patent Document 2 the semiconductor device manufacturing method disclosed in Patent Document 2 is not a wafer level package. For this reason, when applied to a wafer level package in which two substrates are bonded together, both the upper and lower substrates must be modified, which increases the number of steps. Further, since the process is finally a cracking of the substrate, there is a problem that it causes a sealing failure due to a crack, a chip or the like.
  • the present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a wafer level package manufacturing method and a wafer level package capable of improving the wafer yield and the product yield.
  • a method for manufacturing a wafer level package of the present invention includes a first wafer on which a plurality of device chips are mounted or formed in a plane, and a second wafer that faces the first wafer.
  • a first groove for separating into at least one of the first wafer and the second wafer is formed.
  • the method includes a first groove forming step and a bonding step for bonding the first wafer and the second wafer in this order.
  • the wafer level package according to the present invention includes a first wafer on which a plurality of device chips are mounted or formed in a plane and a second wafer facing the first wafer, and then bonded to each device.
  • the singulated wafer level package at least one of the first wafer and the second wafer is provided with a first groove formed for singulation for each device. Yes.
  • the first groove for separating into at least one of the first wafer and the second wafer is formed in the first groove forming step. To do. Next, the first wafer and the second wafer are bonded by a bonding process.
  • the first groove for separating the individual wafer level packages is formed with the first wafer. It is formed in advance before bonding with the second wafer.
  • the first groove for separating into at least one of the first wafer and the second wafer is formed before bonding, warping is reduced by the buffering action of the first groove. It can be joined in the state.
  • the method for manufacturing a wafer level package according to the present invention includes a first groove forming step for forming a first groove for separating at least one of the first wafer and the second wafer, This is a method including a bonding step for bonding the first wafer and the second wafer in this order.
  • At least one of the first wafer and the second wafer is provided with a first groove formed for individual device separation.
  • FIGS. 4A to 4E are cross-sectional views showing an embodiment of a method for manufacturing a wafer level package according to the present invention and showing a manufacturing process of the wafer level package.
  • FIGS. It is a perspective view which shows the structure of the said wafer level package separated into pieces. It is sectional drawing which shows the structure of the said wafer level package.
  • (A)-(e) is sectional drawing which shows the manufacturing process of the modification of the manufacturing method of the said wafer level package.
  • (A)-(e) is sectional drawing which shows the manufacturing process of the other modification of the manufacturing method of the said wafer level package.
  • A)-(e) is sectional drawing which shows the manufacturing process of the other modification of the manufacturing method of the said wafer level package.
  • (A) It is a top view which shows the relationship between the device chip and scribe line by the manufacturing method of the wafer level package of this Embodiment, (b) is the device chip and die thin line by the manufacturing method of the conventional wafer level package It is a top view which shows a relationship.
  • (A)-(e) is sectional drawing which shows the manufacturing method of the conventional wafer level package.
  • (A)-(f) is sectional drawing which shows the manufacturing method of the conventional semiconductor device.
  • (A) is a top view which shows the manufacturing method of the other conventional wafer level package,
  • (b) is the sectional drawing.
  • (A)-(f) is sectional drawing which shows the manufacturing method of the other conventional semiconductor device. It is sectional drawing which shows the structure of the wafer level package which bonded together two other conventional semiconductor devices shown in the said FIG.
  • FIGS. 1 to 7 An embodiment of the present invention will be described with reference to FIGS. 1 to 7 as follows.
  • FIG. 2 is a perspective view showing a configuration of a wafer level package separated into pieces
  • FIG. 2 is a cross-sectional view showing a configuration of the wafer level package before being separated into pieces.
  • the wafer level package 10 of the present embodiment is formed by joining a base portion 2 on which a device chip 1 described later is mounted or formed and a cap portion 3 covering the base portion 2.
  • a through hole 5 is formed in the cap portion 3
  • the device chip 1 has a wiring formed in the through hole 5 and a wiring pattern 6 provided on the surface of the cap portion 3. It is electrically connected to an external device provided outside (not shown). Therefore, the wafer level package 10 according to the present embodiment performs signal transfer using a through silicon via (TSV).
  • TSV through silicon via
  • TSV through silicon via
  • the device chip 1 is composed of, for example, a switch contact portion.
  • the present invention is not necessarily limited to this, and any other device or chip such as an electronic circuit may be used.
  • the wafer level package 10 includes a device wafer 20 as a first wafer on which a plurality of device chips 1 are mounted or formed in a plane, and a second wafer facing the device wafer 20. After the cap wafer 30 is bonded to each other, each device is separated into individual pieces. That is, the wafer level package 10 according to the present embodiment performs all the processes up to rewiring, electrode formation, resin sealing, and singulation in the wafer process, and the size of the device chip 1 that finally cut the wafer remains as it is. It is the size of the package. Therefore, it can be said that the wafer level package is ideal from the viewpoint of miniaturization and weight reduction. As described above, the wafer level package 10 of the present embodiment is adopted in an electronic device such as a mobile phone. Any micro electro mechanical system (MEMS) structure may be used.
  • MEMS micro electro mechanical system
  • the device wafer 20 is formed by stacking silicon (Si) wafers, and an insulating film 21 is formed on each layer of wafers. A plurality of device chips 1 are mounted on the insulating film 21 formed on the surface of the upper wafer.
  • the cap wafer 30 is also made of silicon (Si), and an insulating film 31 is formed on the surface thereof.
  • the device chip 1 is electrically connected to an external device through the through hole 5, the wiring pattern 6 and the bump 7 formed in the cap wafer 30 as described above.
  • a switch movable portion 22 is provided on the lower wafer of the device wafer 20.
  • a frame-like bonding / sealing portion 4 is formed, whereby each device chip 1 is sealed by the bonding / sealing portion 4, the upper and lower device wafers 20, and the cap wafer 30.
  • the device wafer 20 and the cap wafer 30 can be bonded by a silicon (Si) -silicon (Si) bond or a silicon (Si) -silicon dioxide (SiO 2 ) bond.
  • the joining sealing part 4 as a joining material which consists of a metal, glass frit, or resin, or the other joining material which is not shown which consists of a metal, glass frit, or resin may be sufficient.
  • the device chip 1 is hermetically sealed between the device chip 1 and the bonding sealing portion 4, the device chip 1 is filled with a substance such as an inert gas or other resin even in a complete vacuum. It may be.
  • the device wafer 20 is provided with a first groove 23 formed to be separated for each device.
  • the other cap wafer 30 different from the device wafer 20 in which the first groove 23 is formed is provided with a band-shaped through-opening 32 that is formed by other than dicing after bonding. That is, the band-shaped through opening 32 is formed up to the lower surface of the cap wafer 30. For this reason, the band-shaped through opening 32 is a band-shaped through opening having no bottom in the cap wafer 30.
  • the present invention is not necessarily limited to this, and a second groove (not shown) that is a band-like opening having a bottom in the cap wafer 30 may be used.
  • the wafer level package 10 can be singulated by scribing or the like, as will be described later, even if the second groove is a bottomed belt-like opening, not necessarily the belt-like through-opening.
  • the first groove 23 is provided in the device wafer 20, and the band-shaped through opening 32 is provided in the cap wafer 30.
  • the present invention is not limited to this, and for example, the first groove 23 may be provided in the cap wafer 30 and the band-shaped through opening 32 may be provided in the device wafer 20.
  • FIGS. 1A to 1E are cross-sectional views showing manufacturing steps of the wafer level package 10.
  • the first groove 23 is formed on the surface of the device wafer 20 in the first groove forming step.
  • the first groove 23 is a bottomed band-shaped opening and is formed by, for example, dry etching or laser. In the case of dry etching, a dry etching mask is used.
  • the width of the first groove 23 is narrower than the disk width of a disk cutter in a dicing method that is generally used in the past to separate the first groove 23.
  • the device wafer 20 on which the first groove 23 is formed and the cap wafer 30 are bonded.
  • bonding is performed so that the first groove 23 of the device wafer 20 faces the cap wafer 30.
  • a bonding material made of metal, glass frit, or resin can be used, and bonding is performed by silicon (Si) -silicon (Si) bonding or silicon (Si) -silicon dioxide (SiO 2 ) bonding. Is also possible.
  • the back surface of the cap wafer 30 (the upper surface in FIG. 1B) is thinned by a grinder or etching not shown.
  • the through hole 5 is formed in the cap wafer 30 by, for example, dry etching.
  • the band-shaped through opening 32 is also formed by dry etching together as the second groove forming step.
  • the band-shaped through opening 32 is a band-shaped opening that penetrates the cap wafer 30 and is arranged so as to be collinear with the first groove 23 formed in the device wafer 20. Since the band-shaped through opening 32 is formed together with the through hole 5, it can be efficiently formed.
  • the formation of the band-shaped through opening 32 is performed by dry etching, for example.
  • the present invention is not limited to this, and a laser can also be used. That is, any method other than the dicing method may be used. The reason is that the cutting allowance can be made narrower than the dicing method.
  • metal through-wiring is formed in the through hole 5 of the cap wafer 30, and the wiring pattern 6 (not shown) is formed.
  • the first groove 23 is exposed, whereby the wafer level package 10 is singulated.
  • the wafer level package 10 is singulated. There are various methods for dividing the wafer level package 10 into individual pieces.
  • the device wafer 20 can be cut along the scribe line 24.
  • the wafer level package 10 can be cut along the first groove 23 by marking a line or the like with a sharp tool (not shown) as a mark and bending the mark. That is, the thickness of the wafer level package 10 is, for example, 150 ⁇ m for the cap wafer 30, 200 ⁇ m for the device wafer 20, and 60 ⁇ m between the cap wafer 30 and the device wafer 20.
  • a band-shaped through opening 32 is formed in the cap wafer 30, and the first groove 23 is formed halfway through the thickness of the device wafer 20. Therefore, in the thickness direction of the wafer level package 10, 60 ⁇ m between the cap wafer 30 and the device wafer 20 and a part of the device wafer 20 are connected. Therefore, with this thickness, the wafer level package 10 can be easily cut by a scribe method.
  • the wafer level package 10 can be separated into pieces by stretching the sheet.
  • the method of exposing the first groove 23 and dividing the wafer level package 10 into pieces is not necessarily limited to this.
  • the device wafer 20 bonded with the first groove 23 as a boundary in the device wafer 20 in which the first groove 23 is formed, and
  • the first groove 23 can be exposed at the cut surface 25 by extending the cap wafer 30 to both sides.
  • the back surface side of the first groove 23 in the device wafer 20 in which the first groove 23 is formed is ground, polished, or The first groove 23 can be exposed by forming a thinned device wafer 20a that has been thinned by etching.
  • the half groove 26 is used to expose the first groove 23.
  • the half die 26 refers to cutting from the back surface side of the first groove 23 to the first groove 23 in the device wafer 20 in which the groove is formed by a disk cutter used for dicing.
  • the device wafer 20 on which the plurality of device chips 1 are mounted or formed in the surface and the cap wafer 30 facing the device wafer 20 are bonded to each other. After that, it is separated into pieces for each device. Then, the first groove forming step for forming the first groove 23 to be separated into at least one of the device wafer 20 and the cap wafer 30 and the bonding step for bonding the device wafer 20 and the cap wafer 30 are performed. Includes in order.
  • the wafer level package 10 includes a device wafer 20 on which a plurality of device chips 1 are mounted or formed in a plane and a cap wafer 30 facing the device wafer 20, and then bonded to the device wafer 20. Each piece is separated. At least one of the device wafer 20 and the cap wafer 30 is provided with a first groove 23 that is formed to be separated into individual devices.
  • the first groove 23 for separating into at least one of the device wafer 20 and the cap wafer 30 is formed in the first groove forming step. .
  • the device wafer 20 and the cap wafer 30 are bonded by a bonding process.
  • the first groove 23 for separating the individual wafer level package 10 is formed with the device wafer 20. It is formed in advance before bonding the cap wafer 30 together.
  • the dimensional accuracy deteriorates due to the influence of warpage, and the wafer yield and the product yield deteriorate. To do.
  • the cause of this warpage is due to the difference in thermal expansion coefficient or the stress that the wafer has.
  • the stress possessed by the wafer is, for example, the stress possessed by the films formed by forming a bonding metal, an insulating film, a wiring metal, or the like on the wafer.
  • the wafer thickness and the wafer having an SOI structure (a structure having an insulating film in the middle of silicon (Si)) used for the device wafer 20 are also caused by warpage.
  • the first groove 23 for separating the device wafer 20 and the cap wafer 30 is formed in at least one of the device wafer 20 and the cap wafer 30 before bonding, the first groove 23 warps due to the buffering action. It is possible to join in a state where it is reduced.
  • the first groove 23 it is possible to form the first groove 23 to be separated into both the device wafer 20 and the cap wafer 30 before bonding.
  • the first groove 23 By forming the first groove 23 in at least the device wafer 20, even if the device wafer 20 and the cap wafer 30 are separated into individual pieces by extending to both sides after bonding, cracks and chips on the device surface are not generated. Can be prevented.
  • the depth of the first groove 23 shallow, it is possible to prevent breakage during bonding.
  • the first groove 23 is formed in one of the device wafer 20 and the cap wafer 30 and in the bonding step.
  • the band-shaped through-opening 32 or the second groove for separating the device wafer 20 into the other cap wafer 30 or the device wafer 20 different from either the device wafer 20 or the cap wafer 30 in which the first groove 23 is formed is formed.
  • a second groove forming step for forming other than dicing is included.
  • the first groove 23 is formed in one of the device wafer 20 and the cap wafer 30, and the device wafer 20 and the cap in which the first groove 23 is formed.
  • the other cap wafer 30 or device wafer 20 that is different from any one of the wafers 30 is provided with a band-shaped through-opening 32 or a second groove to be separated into pieces formed after bonding other than dicing. Is preferred.
  • the second groove is a bottomed belt-like opening, and the belt-like through opening 32 is a bottomless one.
  • the wafer level package 10 can be separated into pieces by scribing or the like even if the second groove is a bottomed belt-like opening, not necessarily the belt-like through opening 32.
  • a method of forming the band-like through opening 32 or the second groove other than dicing there is a method of drilling by etching or laser, for example.
  • the device wafer 20 and the device wafer 20 that are different from either the device wafer 20 or the cap wafer 30 in which the first groove 23 is formed are separated into pieces.
  • the band-shaped through opening 32 or the second groove is formed by other than dicing.
  • the first groove 23 and the band-shaped through opening 32 or the second groove exist on the same line, and thereby the bonded device wafer 20 and cap wafer.
  • the dimension of the connecting portion at 30 is small.
  • the bonded device wafer 20 and cap wafer 30 are stretched to both sides, for example, with the first groove 23 and the band-shaped through opening 32 or the second groove as a boundary, etc.
  • the wafer level package 10 can be easily separated into individual pieces. For this reason, a dicing process can be made unnecessary.
  • the number of device chips 1 can be increased. That is, as shown in FIG. 7B, conventionally, since the width of the dicing line by dicing is large, the number of device chips 1 per device wafer 20 is inevitably reduced. Specifically, in the case of the conventional dicing method shown in FIG. 7B, a dicing width of 50 to 100 ⁇ m is necessary, and a chip interval of 100 to 200 ⁇ m is necessary in consideration of dicing accuracy.
  • the device chip 1 can be cut into individual pieces by cutting with a scribe line 24 narrower than the width of the dicing line. it can.
  • the width of the groove is 5 to 30 ⁇ m, and even if the accuracy of the scribe line 24 is taken into consideration, it can be realized at an interval of 20 to 50 ⁇ m.
  • the wafer level package 10 is formed on either the device wafer 20 or the cap wafer 30 formed in the first groove forming step.
  • a first groove exposing step for exposing the first groove 23 from the back surface of the first groove 23 is included.
  • the first groove 23 is exposed and the wafer level package 10 can be singulated.
  • the first groove 23 is opposed to the back surface of the first groove 23 in either the device wafer 20 or the cap wafer 30. By scribing along the position, the first groove 23 can be exposed. As a result, the first groove 23 can be exposed by a scribing method without going through a dicing process, and the wafer level package 10 can be singulated.
  • the back surface of the first groove 23 in one of the device wafer 20 and the cap wafer 30 in which the first groove 23 is formed in the first groove exposing step, the back surface of the first groove 23 in one of the device wafer 20 and the cap wafer 30 in which the first groove 23 is formed.
  • the first groove 23 can be exposed by scraping the side by grinding, polishing, or etching to form a thin wafer.
  • the first groove 23 exists up to a thickness in the middle of either the device wafer 20 or the cap wafer 30.
  • channel 23 is exposed by scraping the back surface side of the 1st groove
  • the first groove 23 can be exposed and the wafer level package 10 can be separated into pieces by a method in which the wafer is thinned by grinding, polishing, or etching without going through a dicing process.
  • first groove exposing step from the back side of first groove 23 in either one of device wafer 20 and cap wafer 30 in which first groove 23 is formed. It is possible to expose the first groove 23 by performing the half die 26 up to the first groove 23.
  • each device chip 1 mounted on the surface of the device wafer 20 is already partitioned by the first groove 23 and the cut surface of the band-shaped through opening 32 or the second groove. For this reason, even if the half dice 26 is diced from the rear surface side of the first groove 23 with a large disc width, the dicing cost does not affect the singulation of the device chip 1. Therefore, the number of device chips 1 is not reduced.
  • the first groove 23 in either the device wafer 20 or the cap wafer 30 in which the first groove 23 is formed is bounded.
  • the first groove 23 can be exposed by extending the bonded device wafer 20 and cap wafer 30 to both sides.
  • the first groove 23 and the band-shaped through opening 32 or the second groove exist on the same line, and thereby the bonded device wafer 20 and cap wafer 30.
  • the dimension of the connecting portion in the case is small.
  • the bonded device wafer 20 and cap wafer 30 are stretched, that is, peeled off on both sides, with the first groove 23 and the band-shaped through-opening 32 or the second groove as a boundary.
  • the wafer level package 10 can be easily separated into individual pieces.
  • the first groove 23 is exposed by a method of extending the bonded device wafer 20 and cap wafer 30 to both sides with the first groove 23 as a boundary, and the wafer level package 10 is separated into individual pieces.
  • the method for manufacturing the wafer level package 10 of the present embodiment it is possible to use a bonding material made of metal, glass frit, or resin in the bonding process.
  • the device wafer 20 and the cap wafer 30 can be reliably bonded and sealed using the bonding material.
  • the device wafer 20 and the cap are bonded by silicon (Si) -silicon (Si) bonding or silicon (Si) -silicon dioxide (SiO 2 ) bonding in the bonding process.
  • the wafer 30 can be bonded.
  • the device wafer 20 and the cap wafer 30 are bonded and sealed without using a bonding material. Therefore, the cost can be reduced by not using the bonding material.
  • the first groove is formed on one of the first wafer and the second wafer.
  • a second groove forming step of forming the band-shaped through opening or the second groove other than dicing it is preferable to include a second groove forming step of forming the band-shaped through opening or the second groove other than dicing.
  • the first groove is formed in one of the first wafer and the second wafer, and the first wafer and the first wafer in which the first groove is formed
  • the other second wafer or the first wafer which is different from any one of the two wafers, is provided with a band-shaped through-opening or a second groove for separating into pieces formed after bonding other than dicing.
  • the second groove is a bottomed belt-like opening, and the belt-like through opening is a bottomless one.
  • the wafer level package can be separated into pieces by scribing or the like even if the second groove is a bottomed belt-like opening, not necessarily the belt-like through-opening.
  • a method for forming the band-shaped through-opening or the second groove other than dicing for example, there is a method of drilling by etching or laser.
  • the second wafer or the first wafer which is different from one of the first wafer and the second wafer in which the first groove is formed, is separated into pieces.
  • a belt-like through-opening or a second groove is formed by other than dicing.
  • the first groove and the band-shaped through-opening or the second groove exist on the same line, and thereby the bonded first wafer and the second wafer.
  • the dimension of the connecting portion of the wafer 2 is small.
  • the first wafer and the second wafer are stretched to both sides with the first groove and the belt-like through opening or the second groove as a boundary, for example.
  • the wafer level package can be easily separated. For this reason, a dicing process can be made unnecessary.
  • the first wafer formed in either the first wafer or the second wafer formed in the first groove forming step after the second groove forming step, the first wafer formed in either the first wafer or the second wafer formed in the first groove forming step.
  • a first groove exposing step for exposing the first groove from the back surface of the one groove is included.
  • the first groove can be exposed and the wafer level package can be separated.
  • the back surface of the first groove in either one of the first wafer and the second wafer extends along a position facing the first groove.
  • the scribing means cutting the wafer level package along the first groove by cutting a line or the like with a sharp tool as a mark and bending the mark.
  • the back surface side of the first groove in either one of the first wafer and the second wafer on which the first groove is formed is ground.
  • the first groove can be exposed by scraping, polishing, or etching to form a thin wafer.
  • the first groove exists up to a thickness in the middle of one of the first wafer and the second wafer.
  • channel is exposed by scraping off the back surface side of the 1st groove
  • the first groove can be exposed by a method of thinning the wafer by grinding, polishing, or etching, and the wafer level package can be singulated.
  • the first groove is formed from the back surface side of the first groove in either one of the first wafer and the second wafer.
  • the first groove can be exposed by half-dicing up to one groove.
  • the half die is a disc cutter used for dicing, which cuts from the back side of the first groove to the first groove in either one of the first wafer and the second wafer in which the groove is formed.
  • the first groove is exposed by a method of half-dicing up to the first groove, and the wafer level package can be separated.
  • each device chip mounted on the surface of the first wafer is already partitioned at the cut surface of the first groove and the band-like through opening or the second groove. For this reason, even if half dicing is performed from the back surface side of the first groove by dicing with a large disk width, the dicing cost does not affect the device chip separation. Therefore, the number of device chips is not reduced.
  • the bonding is performed using the first groove in either one of the first wafer and the second wafer on which the first groove is formed as a boundary.
  • the first groove can be exposed by stretching the first and second wafers formed on both sides.
  • the first groove and the band-shaped through-opening or the second groove exist on the same line, and thereby the bonded first wafer and second wafer.
  • the dimension of the connecting portion of the wafer is small.
  • the bonded first wafer and second wafer are stretched, that is, peeled off from both sides of the first wafer and the second wafer with the first groove and the band-shaped through-opening or the second groove as a boundary.
  • the wafer level package can be easily separated into individual pieces.
  • the first groove is exposed by extending the bonded first wafer and second wafer to both sides with the first groove as a boundary, and the wafer level package is separated into pieces. can do.
  • the present invention relates to a wafer level package, MEMS (Micro Electro Electrode) applied to a semiconductor package mounted on an electronic product represented by a mobile phone, a mobile computer, a personal digital assistant (PDA), a digital still camera (DSC) and the like. It can be applied to a manufacturing method of a wafer level package such as a mechanical system) device and a wafer level package.
  • MEMS Micro Electro Electrode
  • PDA personal digital assistant
  • DSC digital still camera

Landscapes

  • Dicing (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un boîtier de niveau de tranche comprenant les étapes consistant à joindre mutuellement une tranche de dispositif (20) comportant une pluralité de puces de dispositif montée ou formée au sein de la surface, et une tranche de coiffe (30) opposée à la tranche de dispositif (20) et singulariser par la suite la tranche jointe pour chaque dispositif. Le procédé comprend une première étape de formation de rainure consistant à former une rainure (23) pour singularisation au moins dans soit la tranche de dispositif (20), soit la tranche de coiffe (30) et une étape de jonction consistant à joindre la tranche de dispositif (20) et la tranche de coiffe (30) séquentiellement dans l'ordre. Ici, il est possible de proposer un procédé de fabrication d'un boîtier de niveau de tranche et un boîtier de niveau de tranche, qui soient capables d'augmenter le rendement de tranche et le rendement de produit.
PCT/JP2011/056251 2011-03-04 2011-03-16 Procédé de fabrication de boîtier de niveau de tranche et boîtier de niveau de tranche Ceased WO2012120694A1 (fr)

Applications Claiming Priority (2)

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JP2011048249A JP2012186309A (ja) 2011-03-04 2011-03-04 ウエハレベルパッケージの製造方法、及びウエハレベルパッケージ
JP2011-048249 2011-03-04

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WO2012120694A1 true WO2012120694A1 (fr) 2012-09-13

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US10163709B2 (en) * 2015-02-13 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
DE102019120844A1 (de) * 2019-08-01 2021-02-04 Horst Siedle Gmbh & Co. Kg Verfahren zur Herstellung von abgedichteten Funktionselementen
JP2023032049A (ja) 2021-08-26 2023-03-09 キオクシア株式会社 半導体装置
KR20230167794A (ko) 2022-06-02 2023-12-12 삼성전자주식회사 반도체 장치 및 제조 방법

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WO2014045701A1 (fr) * 2012-09-19 2014-03-27 三菱電機株式会社 Procédé de fabrication de dispositif à semi-conducteur
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CN112018027A (zh) * 2019-05-31 2020-12-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、晶圆切割方法
CN115939050A (zh) * 2022-09-29 2023-04-07 华天科技(南京)有限公司 一种硅基帽代替金属盖的传感器封装结构及封装方法

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