WO2012143347A1 - Ensemble commutateur - Google Patents

Ensemble commutateur Download PDF

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Publication number
WO2012143347A1
WO2012143347A1 PCT/EP2012/056986 EP2012056986W WO2012143347A1 WO 2012143347 A1 WO2012143347 A1 WO 2012143347A1 EP 2012056986 W EP2012056986 W EP 2012056986W WO 2012143347 A1 WO2012143347 A1 WO 2012143347A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
input
output
pmos
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2012/056986
Other languages
German (de)
English (en)
Inventor
Anatoli GRIGORIEV
Dmitri GUBANOV
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elmos Semiconductor SE
Original Assignee
Elmos Semiconductor SE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elmos Semiconductor SE filed Critical Elmos Semiconductor SE
Priority to DE112012001788.9T priority Critical patent/DE112012001788B4/de
Publication of WO2012143347A1 publication Critical patent/WO2012143347A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration

Definitions

  • the invention relates to a switch arrangement for switching through positive and negative voltages at an input to an output and for blocking the input from the output.
  • a switch arrangement for switching through positive and negative voltages at an input to an output and for blocking the input from the output.
  • the GmbHeranord- calculations in this case have controllable electronic switch in the form of Transis ⁇ tors. Depending on the technology in which the transistors are made, their blocking and forward voltages are limited. Theistsfes ⁇ activity of such transistors can be increased at the expense of larger chip areas, but sometimes economically not makes sense. In particular, there is a need for switching voltages for high precision industrial applications in the range of +/- 24 volts and higher.
  • the object of the invention is to provide a switch assembly for high-voltage applications, are used in the low-voltage transistors.
  • a switch arrangement is proposed with the invention, which is provided with
  • a second series circuit of two NMOS transistors each having a gate, a source and a drain and a substrate and parasitic diodes between the source and the drain on the one hand and the substrate on the other hand, wherein the parasitic diodes for preventing the unwanted switching of a voltage against each other are switched,
  • sources and the substrates of the input-side PMOS and NMOS transistors are connected to the input terminal, and the sources and the substrates of the output-side PMOS and NMOS transistors are connected to the output terminal, and
  • a drive unit for the PMOS and NMOS transistors for selectively blocking or passing a voltage at the input terminal with respect to the output terminal or vice versa
  • the drive unit when the input terminal is to be locked relative to the output terminal or vice versa, to the gate of the input side PMOS transistor and to the gate of the output ⁇ side PMOS transistor each applies a control voltage which is greater than the voltage at the input or Output terminal minus the threshold voltage of the respective PMOS transistor, and to the gate of the input side OS transistor and to the gate of the ⁇ gang townen NMOS transistor each applies a control voltage which is smaller than the voltage at the input or output terminal plus the Whole voltage of the respective NMOS transistor is, and wherein, when the input terminal is to be conductively connected to the output terminal, the drive unit applies to the gate of the input-side P MOS transistor and to the gate of the output-side PMOS transistor in each case a control voltage which is at least equal to the threshold voltage of the relevant one PMOS transistor is smaller than the voltage at the input or output terminal, and to the gate of the input-side MOS transistor and to the gate of the output side NMOS transistor respectively applies a control voltage which is at least the threshold voltage
  • the concept according to the invention is a "floating" high-voltage CMOS switch arrangement for blocking or passing a negative or positive voltage within a predetermined voltage range of, for example, +/- 24 volts.
  • the individual switches are embodied, for example, in SOI technology ,
  • the switch arrangement has an input terminal and an output terminal, between which two ⁇ to each other in parallel series circuits comprising PMOS and NMOS are connected sistoren transit.
  • Such transistors have substrate diodes.
  • the two PMOS transistors of the first SerienschaS- tung and the two OS transistors of the second series circuit are interconnected such that their parasitic substrate diodes are ⁇ respectively connected against each other, thereby (in any conceivable Radio Frequency at the input terminal with respect to more negative Voltage at the output connection or vice versa) in each series connection, one diode is connected in the reverse direction.
  • the gates of the PMOS and NMOS transistors are supplied via a control unit with control voltages which can be selectively switched on all or switched off all regardless of the size and the sign of the voltages at the input and output terminal.
  • the "gates" of the transistors "floated", namely, the gates of the two input-side PMOS and NMOS transistors of the current voltage at the input terminal tracked, while the gates of the two output-side PMOS and NMOS transistors track the current voltage at the output terminal.
  • the drive unit can be used to detect the respective magnitude (including sign) of the voltages at the input and output terminals.
  • the switches arrangement is to be inhibited, the gates of the input-side PMOS and IM MOS transistors are kept at the value of the voltage at the input terminal, while the gates of the output-side PMOS and NMOS transistors are at the value of the voltage currently being applied Output terminal are held.
  • the transistors are turned on by deducting the respective input voltages from these current voltages or adding them to these actual voltages, so that the gate-source voltages required for the turn-on state of the respective transistors are set. In the simplest case, this can be done by adding (or subtracting) these threshold voltages to the current gate voltages.
  • an input-side voltage tracking unit is connected between the input terminal and the gates of the input-side PMOS and NMOS transistors
  • an output-side voltage tracking unit is connected between the output terminal and the gates of the output-side PMOS and NMOS transistors
  • a voltage the voltage at the input terminal can be tracked at the gates of the two input-side PMOS and NMOS transistors
  • a voltage at the gates of the two output-side PMOS and NMOS transistors can be tracked at the voltage at the output terminal
  • the drive unit can be tracked when the input terminal is to be blocked relative to the output terminal, to which gates of the transistors, in addition to the voltage applied to the voltage at the input or output terminal, no further control voltage or a control voltage which continues to block these transistors is applied, and then, when the Ein The output terminal is to be conductively connected to the gates of the transistors, in addition to the voltage applied to the voltage at the input or output terminal voltage, the threshold voltage of the respective PMOS or NMOS transistor applies.
  • the switch assembly according to the above variant thus has floating gates.
  • the threshold or drive voltage for the respective transistor is added or subtracted to the voltage at the output or to the voltage at the input, which is done by voltage adder or -substrahierer.
  • the voltage at the output or at the input is in this case e.g. by a decoupling unit, e.g. an operational amplifier or other voltage follower circuit (e.g., so-called source follower transistor circuits) to the gate of the respective transistor.
  • the invention also embodies itself in a switch arrangement with only a series connection of two PMOS or two NMOS transistors, as described in claims 3 to 5.
  • the switch arrangement 10 has an input terminal 12 and an output terminal 14, between which two PMOS transistors 16, 18 and two NMOS transistors 20, 22 are connected.
  • the both PMOS transistors 16,18 connected in series
  • the two NMOS transistors 20,22 are also connected in series.
  • These two series circuits 24,26 are connected in parallel with each other and are located between the input and the output flange 12 and 14, respectively.
  • Each transistor 16, 18, 20, 22 has a gate 28, a source 30, a drain 32, and a dedicated substrate 34.
  • the source 30 of the input-side PMOS transistor 16 and the input-side NMOS transistor 20 are connected to the matterssanschius 12.
  • the substrates 34 of these two transistors are also connected to the input connection 12.
  • the sources 30 of the PMOS output side transistor 18 and the output side NMOS transistor 22 are connected to the output terminal 14.
  • Their substrates 34 are also connected to the output terminal 14.
  • the parasitic substrate diodes 36 of the respective PMOS or MOS transistors 16, 18 and 20, 22 of the two series circuits 24, 26 are in each case connected against one another, so that in each case an electrical connection between the input connection 12 and the output connection 14 is prevented via the substrates 34 of the interconnected transistors of the two series circuits 24,26.
  • the gates 28 of the four transistors 16, 18, 20, 22 are "floating" and follow the voltages at the input and output terminals 12, 14.
  • the gates 28 of the two input-side PMOS and NMOS transistors 16, 20 are coupled via an input-side voltage tracking unit 38 to the input terminal 12, by, for example, a per se known operational amplifier circuit, which prevents feedback of the voltage applied to the gate tommsanschius 12.
  • the off ⁇ input terminal 14 coupled via an output-sidedersnachriosnachriosnachriosnachriostician 40 to the gates 28 of the two output-side PMOS and NMOS transistors 18,22, again for example, by an operational amplifier, the feedback of the applied to the gate voltage to the output terminal 14 prevented.
  • the gates 28 of the four transistors are now supplied in addition to the floating potentials, the respective threshold voltages, which with the aid of a drive unit 42 and the at + and --- ange- indicated voltage adders or substrahierern whose circuitry technical realizations are known per se, takes place.
  • the output terminal 14 of the switch arrangement 10 there is an appiication-dependent circuit schematically illustrated at 44 as BSock for processing the switched-through or locked voltage signal at the input terminal 12 of the switch arrangement 10.
  • the switch assembly 10 of FIG. 1 operates as follows. To block a voltage at the input terminal 12 with respect to the output terminal 14 no further voltages are applied to the (floating) gates 28 of the four transistors via the updated actual voltages at the input terminal 12 and output terminal 14. Thus, the gate-source voltages of all transistors are nuii volts. Per series circuit 24,26 so that at least one transistor is blocked. The connection via the parasitic substrate diodes 36 is also blocked because at least one of these parasitic substrate diodes 36 blocks per series circuit 24, 26.
  • the four transistors are acted upon by the drive unit 42 with their respective threshold voltages V on , in such a way that the gates 28 of the two PMOS transistors 16,18 a voltage lower by the threshold voltage ⁇ as the actual voltage at the input terminal 12 and output terminal 14, respectively. Accordingly, the voltage at the gates 28 of the two NMOS transistors 20,22 compared to the current voltage at the input terminal 12 and output terminal 14 is increased by the A ⁇ output voltage. This is also indicated in the drawing.
  • the invention is DES same conductivity type (that is, a series circuit comprising two PMOS transistors and a series circuit of two NMOS transistors) is not limited to the realization of a switch assembly with two paral ⁇ lel-connected series circuits each consisting of two NMOS transistors.
  • the invention also encompasses switch arrangements in which only one series circuit (consisting of two PMOS transistors or of two NMOS transistors) is connected between the input and output terminals of the switch arrangement. is switched.
  • complementary transistors PMOS and NMOS transistors in series
  • the voltage range within which the switch assembly is to block or conduct can be extended to both the lower and upper allowable input / output voltage ranges.

Landscapes

  • Electronic Switches (AREA)

Abstract

L'invention concerne un ensemble commutateur pour commuter des tensions positives et négatives à une entrée vers une sortie, lequel est pourvu de deux montages en série (24, 26) couplés en parallèle de deux transistors PMOS ou encore de deux transistors NMOS (16, 18, 20, 22) qui sont montés entre l'entrée et la sortie. Les sources et les substrats des transistors PMOS et NMOS (16, 20) du côté entrée sont reliés à la borne d'entrée (12) et les sources ainsi que les substrats des transistors PMOS et NMOS (18, 22) du côté sortie sont reliés à la borne de sortie (14). Quand la borne d'entrée (12) doit être bloquée vis-à-vis de la borne de sortie (14) ou vice-versa, une unité de commande (42) applique alors à la grille du transistor PMOS (16) du côté entrée ainsi qu'à la grille du transistor PMOS (18) du côté sortie une tension de commande qui est supérieure à la tension à la borne d'entrée ou encore à la borne de sortie (12, 14) déduction faite de la tension de seuil du transistor PMOS (16, 18) concerné, et à la grille du transistor NMOS (20) du côté entrée ainsi qu'à la grille du transistor NMOS (22) du côté sortie une tension de commande qui est inférieure à la tension à la borne d'entrée ou encore à la borne de sortie (12, 14) addition faite de la tension de seuil du transistor NMOS (20, 22) concerné. De plus, quand la borne d'entrée (12) doit être reliée de manière conductrice à la borne de sortie (14), l'unité de commande (42) applique alors à la grille du transistor PMOS (16) du côté entrée ainsi qu'à la grille du transistor PMOS (18) du côté sortie une tension de commande qui est inférieure d'au moins la tension de seuil du transistor PMOS (16, 18) concerné à la tension à la borne d'entrée ou encore à la borne de sortie (12, 14) et à la grille du transistor NMOS (20) du côté entrée ainsi qu'à la grille du transistor NMOS (22) du côté sortie une tension de commande qui est supérieure d'au moins la tension de seuil du transistor NMOS (20, 22) concerné à la tension à la borne d'entrée ou encore à la borne de sortie.
PCT/EP2012/056986 2011-04-19 2012-04-17 Ensemble commutateur Ceased WO2012143347A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112012001788.9T DE112012001788B4 (de) 2011-04-19 2012-04-17 Schalteranordnung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP11163018 2011-04-19
EP11163018.2 2011-04-19

Publications (1)

Publication Number Publication Date
WO2012143347A1 true WO2012143347A1 (fr) 2012-10-26

Family

ID=44357964

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2012/056986 Ceased WO2012143347A1 (fr) 2011-04-19 2012-04-17 Ensemble commutateur

Country Status (2)

Country Link
DE (1) DE112012001788B4 (fr)
WO (1) WO2012143347A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112013001581B4 (de) 2012-03-20 2023-04-20 Analog Devices, Inc. Verfahren und Schaltungen eines parallelen DMOS-Schalters

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023688A (en) 1988-12-15 1991-06-11 Kabushiki Kaisha Toshiba Transfer gate with the improved cut-off characteristic
WO1995028035A1 (fr) 1994-04-08 1995-10-19 Vivid Semiconductor, Inc. Logique cmos haute tension utilisant un procede cmos basse tension
EP0698966A1 (fr) 1994-07-29 1996-02-28 STMicroelectronics S.r.l. Commutateur à transistor MOS sans effet de corps
US5789781A (en) 1995-02-27 1998-08-04 Alliedsignal Inc. Silicon-on-insulator (SOI) semiconductor device and method of making the same
EP1024596A1 (fr) 1999-01-29 2000-08-02 Fairchild Semiconductor Corporation Porte de transfert tolérant les surtensions et les sous-tensions

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7924085B2 (en) * 2009-06-19 2011-04-12 Stmicroelectronics Asia Pacific Pte. Ltd. Negative analog switch design

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023688A (en) 1988-12-15 1991-06-11 Kabushiki Kaisha Toshiba Transfer gate with the improved cut-off characteristic
WO1995028035A1 (fr) 1994-04-08 1995-10-19 Vivid Semiconductor, Inc. Logique cmos haute tension utilisant un procede cmos basse tension
EP0698966A1 (fr) 1994-07-29 1996-02-28 STMicroelectronics S.r.l. Commutateur à transistor MOS sans effet de corps
US5789781A (en) 1995-02-27 1998-08-04 Alliedsignal Inc. Silicon-on-insulator (SOI) semiconductor device and method of making the same
EP1024596A1 (fr) 1999-01-29 2000-08-02 Fairchild Semiconductor Corporation Porte de transfert tolérant les surtensions et les sous-tensions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112013001581B4 (de) 2012-03-20 2023-04-20 Analog Devices, Inc. Verfahren und Schaltungen eines parallelen DMOS-Schalters

Also Published As

Publication number Publication date
DE112012001788B4 (de) 2016-05-04
DE112012001788A5 (de) 2014-01-23

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