WO2012165329A1 - Dispositif à semi-conducteurs de puissance à grille en tranchée et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs de puissance à grille en tranchée et son procédé de fabrication Download PDF

Info

Publication number
WO2012165329A1
WO2012165329A1 PCT/JP2012/063480 JP2012063480W WO2012165329A1 WO 2012165329 A1 WO2012165329 A1 WO 2012165329A1 JP 2012063480 W JP2012063480 W JP 2012063480W WO 2012165329 A1 WO2012165329 A1 WO 2012165329A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench gate
semiconductor device
power semiconductor
gate power
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2012/063480
Other languages
English (en)
Japanese (ja)
Inventor
渡辺　祐司
雅人 岸
広輝 佐藤
竹森　俊之
道明 丸岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP2012540208A priority Critical patent/JP5554417B2/ja
Priority to CN201280001820.1A priority patent/CN103250254B/zh
Publication of WO2012165329A1 publication Critical patent/WO2012165329A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions

Definitions

  • the present invention relates to a trench gate power semiconductor device and a manufacturing method thereof.
  • FIG. 12 is a diagram for explaining a conventional trench gate power MOSFET 900.
  • the conventional trench gate power MOSFET 900 includes an n + -type drain layer 912, an n ⁇ -type drift layer 914 located on the drain layer 912, and a p-type located on the drift layer 914.
  • the body layer 920, the groove 924 formed by opening the body layer 920 and reaching the drift layer 914, and the body layer 920 are disposed in the body layer 920, and at least a part thereof is exposed to the inner peripheral surface of the groove 924.
  • n + -type source region 932 formed, a gate insulating film 926 formed on the inner peripheral surface of the groove 924, a gate electrode layer 928 formed on the inner peripheral surface of the gate insulating film 926, and a gate A source electrode layer (not shown) formed in contact with the source region 932 is provided while being insulated from the electrode layer 928.
  • p + type buried region 940 extending deeper than the groove protrudes downward from body layer 920 in the region sandwiched between adjacent trenches 924 in drift layer 914. Is formed.
  • reference numeral 934 indicates a p + type contact region.
  • the conventional trench gate power MOSFET 900 since the unit cell area can be reduced as compared with the case of the normal planar gate power MOSFET, the on-resistance can be reduced as compared with the case of the normal planar gate power MOSFET. It becomes possible. Further, according to the conventional trench gate power MOSFET 900, in the region sandwiched between adjacent trenches 924 in drift layer 914, p + type buried region 940 extending deeper than the trench protrudes downward from body layer 920. Therefore, the electric field in the vicinity of the bottom surface of the groove 924 is relaxed during reverse bias, and the reverse breakdown voltage can be increased.
  • the region where the on-current flows during forward bias becomes narrow due to the presence of the p + -type buried region 940, so that it is difficult to further reduce the on-resistance. There is.
  • Such a problem is also seen in the case of a trench gate power MOSFET in which p and n are reversed. Such a problem is not a problem that exists only in the case of the trench gate power MOSFET, but a problem that exists in the trench gate IGBT and other trench gate power semiconductor devices in general.
  • the present invention has been made to solve the above-described problems, and an object thereof is to provide a trench gate power semiconductor device that has a high reverse breakdown voltage and can further reduce the on-resistance.
  • a trench gate power semiconductor device includes a first conductivity type drift layer, a second conductivity type body layer located on the drift layer and opposite to the first conductivity type, and the body A groove formed by opening a layer and reaching the drift layer, and a first conductivity type formed by being disposed in the body layer and exposing at least a part of the inner peripheral surface of the groove
  • a first electrode layer formed in contact with the first semiconductor region, and a region of a second conductivity type extending deeper than the groove in a region sandwiched between the adjacent grooves in the drift layer.
  • An embedded region is formed in contact with the body layer; The depth position where the second conductivity type impurity in the buried region has the maximum concentration is deeper than the depth position located between the bottom surface of the body layer and the bottom surface of the buried region.
  • the periphery of the buried region in the drift layer contains a first conductivity type impurity having a concentration higher than that of the drift layer so as to cover the buried region. It is preferable that a high concentration first conductivity type semiconductor region is formed.
  • the depth position of the bottom surface of the groove is deeper than the depth position located between the bottom surface of the body layer and the bottom surface of the drift layer. It is preferable.
  • the trench gate power semiconductor device is a trench gate power MOSFET
  • the first semiconductor region is a source region
  • the first electrode layer is a source electrode.
  • the first conductivity type drift layer is disposed on the first conductivity type drain layer.
  • the trench gate power semiconductor device is a trench gate IGBT
  • the first semiconductor region is an emitter region
  • the first electrode layer is an emitter electrode layer.
  • the first conductivity type drift layer is preferably disposed on the second conductivity type collector layer.
  • a method for manufacturing a trench gate power semiconductor device according to the present invention is for manufacturing the trench gate power semiconductor device according to the present invention (the trench gate power semiconductor device according to any one of [1] to [5] above).
  • a method for manufacturing a trench gate power semiconductor device according to the present invention is a method for manufacturing a trench gate power semiconductor device for manufacturing the trench gate power semiconductor device according to the present invention (the trench gate power semiconductor device according to [2] above).
  • a first conductivity type impurity is ion-implanted into a predetermined region of the drift layer by an ion implantation method using a high-energy ion implantation apparatus, and a multi-stage ion implantation method using a high-energy ion implantation apparatus.
  • the high-concentration first conductive semiconductor region and the buried region are formed by ion-implanting a second conductive impurity into a predetermined region of the drift layer.
  • the depth position where the second conductivity type impurity in the buried region has the maximum concentration is more than the depth position located between the bottom surface of the body layer and the bottom surface of the buried region.
  • the electric field in the vicinity of the bottom surface of the groove is further relaxed during reverse bias, and the reverse breakdown voltage is further improved as compared with the case of the conventional trench gate power MOSFET 900. It becomes possible to make it higher.
  • the trench gate power semiconductor device of the present invention is a trench gate power semiconductor device that has a high reverse breakdown voltage and can further reduce the on-resistance.
  • the manufacturing method of the trench gate power semiconductor device of the present invention (the manufacturing method of the trench gate power semiconductor device of [6] above), the trench gate power semiconductor device of the present invention ([1] to [5] above). Any one of the trench gate power semiconductor devices) can be manufactured.
  • the trench gate power semiconductor device of the present invention According to the method of manufacturing a trench gate power semiconductor device of the present invention (the method of manufacturing the trench gate power semiconductor device of [7] above), the trench gate power semiconductor device of the present invention (trench gate according to [2] above). Power semiconductor device) can be manufactured.
  • FIG. 1 is a view for explaining a trench gate power semiconductor device 100 according to Embodiment 1.
  • FIG. It is a figure which shows typically the electric potential distribution at the time of reverse bias.
  • 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment.
  • FIG. 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment.
  • FIG. 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment.
  • FIG. 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment.
  • FIG. 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment.
  • FIG. 6 is a view for explaining a trench gate power semiconductor device 102 according to a second embodiment.
  • FIG. 6 is a view for explaining a method for manufacturing the trench gate power semiconductor device 102 according to the second embodiment.
  • 4 is a cross section of a trench gate power semiconductor device 104 according to a third embodiment. It is sectional drawing of the trench gate power semiconductor device 200 which concerns on a modification. It is a figure shown in order to demonstrate the conventional trench gate power MOSFET900.
  • FIG. 1 is a view for explaining a trench gate power semiconductor device 100 according to the first embodiment.
  • 1A is a cross-sectional view of the trench gate power semiconductor device 100
  • FIG. 1B is a diagram showing the concentration profiles of p and n impurities in the trench gate power semiconductor device 100.
  • FIG. 1A is a cross-sectional view of the trench gate power semiconductor device 100
  • FIG. 1B is a diagram showing the concentration profiles of p and n impurities in the trench gate power semiconductor device 100.
  • the trench gate power semiconductor device 100 includes an n ⁇ type drift layer 114, a p type body layer 120 positioned on the drift layer 114, and a body layer 120. And a groove 124 formed to reach the drift layer 114, and an n + type formed by being exposed in the inner peripheral surface of the groove 124 and being disposed in the body layer 120.
  • the trench gate power MOSFET is provided with a source electrode layer (first electrode layer) 136 that is insulated from 128 and formed in contact with the source region 132.
  • a p-type buried region 140 extending deeper than the groove 124 is formed in the body layer 120 in a region sandwiched between adjacent grooves 124 in the drift layer 114.
  • the depth position P at which the p-type impurity in the buried region 140 has the maximum concentration is in contact with the bottom surface P2 of the body layer 120 as shown in FIGS. 1 (a) and 1 (b). It lies deeper than the depth position located in the middle of the bottom surface P3 of the embedded region 140.
  • reference numeral 110 indicates a semiconductor substrate
  • reference numeral 130 indicates a protective insulating film
  • reference numeral 134 indicates a p + -type contact region
  • reference numeral 112 indicates an n + -type drain layer
  • Reference numeral 138 denotes a drain electrode layer.
  • the thickness of the drain layer 112 is, for example, 300 ⁇ m, and the impurity concentration of the drain layer 112 is, for example, 2 ⁇ 10 19 cm ⁇ 3 .
  • the thickness of the drift layer 114 is, for example, 20 ⁇ m, and the impurity concentration of the drift layer 114 is, for example, 1 ⁇ 10 15 cm ⁇ 3 .
  • the thickness of the body layer 120 is, for example, 1.5 ⁇ m, and the impurity concentration of the body layer 120 is, for example, 1 ⁇ 10 17 cm ⁇ 3 on the surface.
  • the depth of the groove is 2 ⁇ m, for example.
  • the depth of the source region 132 is, for example, 0.3 ⁇ m, and the impurity concentration of the source region 132 is, for example, 2 ⁇ 10 19 cm ⁇ 3 .
  • the depth of the contact region 134 is, for example, 1 ⁇ m, and the impurity concentration of the contact region 134 is, for example, 2 ⁇ 10 19 cm ⁇ 3 .
  • the thickness of the gate insulating film 126 is, for example, 0.1 ⁇ m.
  • the gate electrode layer 128 is made of, for example, polysilicon doped with phosphorus.
  • the source electrode layer 136 is made of, for example, aluminum and has a thickness of, for example, 5 ⁇ m.
  • the source electrode layer 136 is insulated from the gate electrode layer 128 by the protective insulating film 130.
  • the drain electrode layer 138 is made of, for example, nickel and has a thickness of, for example, 2 ⁇ m.
  • the depth position of the bottom surface P3 of the embedded region 140 is deeper than the bottom surface P2 of the body layer 120 by 5 ⁇ m.
  • the depth position P at which the p-type impurity has the maximum concentration in the buried region 140 is at a position 3 ⁇ m deeper than the bottom surface P2 of the body layer 120. Therefore, the depth position P at which the p-type impurity has the maximum concentration in the buried region 140 is deeper than the depth position located between the bottom surface P2 of the body layer 120 and the bottom surface P3 of the buried region 140.
  • FIG. 2 is a diagram schematically showing a potential distribution during reverse bias.
  • FIG. 2A is a diagram schematically showing a potential distribution at the time of reverse bias in the trench gate power semiconductor device 100 according to the first embodiment
  • FIG. 2B is a diagram in the trench gate power semiconductor device 100a according to the comparative example. It is a figure which shows typically the electric potential distribution at the time of reverse bias.
  • the trench gate power semiconductor device 100 according to the first embodiment is manufactured by a “method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment” described later.
  • the trench gate power semiconductor device 100a according to the comparative example is manufactured by a “method of manufacturing the trench gate power semiconductor device 100a according to the comparative example” described later.
  • equipotential lines are indicated by broken lines.
  • the depth position P where the p-type impurity in the buried region 140 has the maximum concentration is the bottom surface P2 of the body layer 120. Since it is deeper than the depth position located in the middle of the bottom surface of the buried region 140, the electric field in the vicinity of the bottom surface of the groove 124 is further relaxed during reverse bias as shown in FIG.
  • the reverse breakdown voltage can be further increased as compared with the conventional trench gate power MOSFET 900. Therefore, according to the trench gate power semiconductor device 100 according to the first embodiment, it is possible to increase the impurity concentration in the drift region while maintaining the reverse breakdown voltage, so that it is much more than in the case of the conventional trench gate power MOSFET.
  • the on-resistance can be lowered.
  • the trench gate power semiconductor device 100 is a trench gate power semiconductor device that has a high reverse breakdown voltage and can further reduce the on-resistance.
  • the trench gate power semiconductor device 100 according to Embodiment 1 can be manufactured by the following method.
  • FIGS. 7A to 7C are process diagrams.
  • a groove 124 having a predetermined depth is formed from the surface of the n ⁇ type epitaxial layer 113.
  • the depth of the groove is, for example, 2 ⁇ m.
  • a doped polysilicon film 128 ′ is formed so as to fill the groove 124 from the surface side of the n ⁇ type epitaxial layer 113.
  • the polysilicon film 128 ′ is etched back, and the polysilicon film 128 ′ is removed while leaving the polysilicon film 128 ′ only in the trench 124.
  • the gate electrode layer 128 is formed on the inner peripheral surface of the groove 124.
  • P-type body layer forming step Thereafter, as shown in FIG. 4C, p-type impurities (for example, boron ions) are ion-implanted from the surface side of the n ⁇ -type epitaxial layer 113 by ion implantation. Ion implantation is performed under conditions of a relatively low acceleration voltage (for example, 100 eV) and a relatively low dose (for example, 1 ⁇ 10 13 cm ⁇ 2 ). Next, heat treatment (for example, 1000 ° C., 1 hour) is performed on the semiconductor substrate 110 to diffuse and activate the p-type impurities, thereby forming the body layer 120 as shown in FIG.
  • a relatively low acceleration voltage for example, 100 eV
  • a relatively low dose for example, 1 ⁇ 10 13 cm ⁇ 2
  • heat treatment for example, 1000 ° C., 1 hour
  • boron ions are implanted under conditions of a first acceleration voltage (for example, 600 keV) and a first dose (for example, 1 ⁇ 10 13 cm ⁇ 2 ), and then a second acceleration voltage (for example, 550 keV). ) And a second dose (for example, 3 ⁇ 10 12 cm ⁇ 2 ), then boron ions are implanted, and then a third acceleration voltage (for example, 500 keV) and a second dose (for example, 1 ⁇ 10 12 cm). -2 ) by implanting boron ions.
  • a first acceleration voltage for example, 600 keV
  • a first dose for example, 1 ⁇ 10 13 cm ⁇ 2
  • a second acceleration voltage for example, 550 keV
  • boron ions are implanted
  • a third acceleration voltage for example, 500 keV
  • a second dose for example, 1 ⁇ 10 12 cm).
  • Ion Implantation Step for Forming Contact Region Thereafter, as shown in FIG. 6B, ion implantation of p-type impurities (for example, boron ions) is performed through the mask M1 while the mask M1 is attached. Do. This step is performed by implanting boron ions under conditions of a relatively low acceleration voltage (for example, 50 keV) and a relatively high dose (for example, 5 ⁇ 10 15 cm ⁇ 2 ).
  • a relatively low acceleration voltage for example, 50 keV
  • a relatively high dose for example, 5 ⁇ 10 15 cm ⁇ 2 .
  • Ion Implantation Step for Forming Source Region Thereafter, as shown in FIG. 6C, the mask M1 is removed from the surface of the body layer 120, and a mask M2 is formed in a predetermined region on the surface of the body layer 120. After that, ion implantation of n-type impurities (for example, arsenic ions) is performed through the mask M2. This step is performed by implanting arsenic ions under conditions of a relatively low acceleration voltage (for example, 50 keV) and a relatively high dose (for example, 1 ⁇ 10 15 cm ⁇ 2 ).
  • a relatively low acceleration voltage for example, 50 keV
  • a relatively high dose for example, 1 ⁇ 10 15 cm ⁇ 2 .
  • Step 10 Step of forming a protective insulating film Thereafter, after removing the thermal oxide film 126 ′ on the surface of the body layer 120, the semiconductor substrate 110 is subjected to a heat treatment to form silicon on the surface of the body layer 120 and the inner peripheral surface of the upper portion of the groove A thermal oxide film is formed, and then a PSG film is formed from the surface side of the body layer 120 by a vapor phase method to form a laminated film. Thereafter, the laminated film is etched by leaving the upper portion of the gate electrode layer 128. Remove. As a result, as shown in FIG. 7B, the protective insulating film 130 is formed on the gate electrode layer 128.
  • Source electrode layer forming step and drain electrode layer forming step Thereafter, as shown in FIG. 7C, a source electrode layer 136 is formed so as to cover the body layer 120 and the protective insulating film 130, and an n + -type drain is formed.
  • a drain electrode layer 138 is formed on the surface of the layer 112.
  • the trench gate power semiconductor device 100 according to the first embodiment can be manufactured.
  • the trench gate power semiconductor device 100a according to the comparative example is different from the trench gate according to the first embodiment in steps other than the “ion implantation step for forming a buried layer”.
  • the power semiconductor device 100 is manufactured by a method similar to the method for manufacturing the power semiconductor device 100.
  • the “ion implantation step for forming the buried layer” is performed as follows.
  • a mask M1 is formed in a predetermined region on the surface of the body layer 120, and then, from the surface side of the n ⁇ -type epitaxial layer 113 through the mask M1, P-type impurities (for example, boron ions) are ion-implanted by the step ion implantation method.
  • P-type impurities for example, boron ions
  • boron ions are implanted under conditions of a first acceleration voltage (eg, 600 keV) and a predetermined dose (eg, 3 ⁇ 10 12 cm ⁇ 2 ), and then a second acceleration voltage (eg, 550 keV).
  • boron ions are implanted under the condition of the above-mentioned predetermined dose (for example, 3 ⁇ 10 12 cm ⁇ 2 ), and then the third acceleration voltage (for example, 500 keV) and the above-mentioned predetermined dose (for example, 3 ⁇ 10 12). This is performed by implanting boron ions under the condition of cm ⁇ 2 ).
  • FIG. 8 is a view for explaining the trench gate power semiconductor device 102 according to the second embodiment.
  • FIG. 8A is a cross-sectional view of the trench gate power semiconductor device 102
  • FIG. 8B is a diagram showing the concentration profiles of p and n impurities in the trench gate power semiconductor device 102.
  • FIG. FIG. 9 is a view for explaining a method of manufacturing the trench gate power semiconductor device 102 according to the second embodiment.
  • FIG. 9A to FIG. 9C are diagrams showing main steps. 9A corresponds to FIG. 5A, and FIG. 9C corresponds to FIG. 5B.
  • the trench gate power semiconductor device 102 according to the second embodiment has basically the same configuration as that of the trench gate power semiconductor device 100 according to the first embodiment. However, as shown in FIG. A trench gate power semiconductor device according to the first embodiment in that an n + -type semiconductor region 142 containing an n-type impurity at a concentration higher than that of the drift layer 114 is formed around the embedded region 140 so as to cover the buried region 140. 100 is different.
  • the trench gate power semiconductor device 102 according to the second embodiment is different from the trench gate power semiconductor device 100 according to the first embodiment in that the n + -type semiconductor region 142 as described above is formed. Similar to the trench gate power semiconductor device 100 according to the first embodiment, the trench gate power semiconductor device having the above-described embedded region 140 and having a high reverse breakdown voltage and a further lower on-resistance. It becomes.
  • the trench gate power semiconductor device 102 since the n + type semiconductor region 142 is formed so as to cover the buried region 140, a p-type impurity is present in the region where the on-current flows in the drift layer 114. Is suppressed as much as possible, and the on-resistance can be further reduced.
  • the trench gate power semiconductor device 102 according to the second embodiment is different from the trench gate power semiconductor device according to the first embodiment except that the n + type semiconductor region 142 is formed so as to cover the buried region 140. 100, the trench gate power semiconductor device 100 according to the first embodiment has a corresponding effect.
  • the trench gate power semiconductor device 102 according to the second embodiment can be manufactured by substantially the same process as the method for manufacturing the trench gate power semiconductor device 100 according to the first embodiment. However, as shown in FIG. 9, a region (a region slightly larger than the buried region 140) that covers the buried region 140 between the p-type body layer forming step and the ion implantation step for forming the buried layer. ) Further includes an ion implantation step for forming an n + type semiconductor region. The ion implantation step can be performed using a high energy ion implantation apparatus. Thereby, the trench gate power semiconductor device 102 according to the second embodiment shown in FIG. 8 can be manufactured.
  • FIG. 10 is a cross-sectional view of the trench gate power semiconductor device 104 according to the third embodiment.
  • the trench gate power semiconductor device 104 according to the third embodiment basically has the same configuration as the trench gate power semiconductor device 100 according to the first embodiment, but the depth position of the bottom surface of the groove 124 is related to the first embodiment. Different from the trench gate power semiconductor device 100. That is, in the trench gate power semiconductor device 104 according to the third embodiment, as shown in FIG. 10, the depth position of the bottom surface of the groove 124 is located between the bottom surface of the body layer 120 and the bottom surface of the drift layer 114. Located deeper than the depth position.
  • the trench gate power semiconductor device 104 according to the third embodiment differs from the trench gate power semiconductor device 100 according to the first embodiment in the depth position of the bottom surface of the groove 124, but the trench according to the first embodiment. Similar to the case of the gate power semiconductor device 100, since the buried region 140 having the above-described structure is provided, a trench gate power semiconductor device having a high reverse breakdown voltage and a further reduced on-resistance can be obtained.
  • the depth position of the bottom surface of the groove 124 is deeper than the depth position located between the bottom surface of the body layer 120 and the bottom surface of the drift layer 114. Therefore, as in the case of the trench gate power semiconductor device 100 according to the first embodiment, the on-resistance can be further reduced as compared with the conventional case.
  • the buried region 140 is covered around the buried region 140 in the drift layer 114 as in the case of the trench gate power semiconductor device 102 according to the second embodiment.
  • an n + type semiconductor region 142 containing an n-type impurity at a concentration higher than that of the drift layer 114 may be formed.
  • the reverse breakdown voltage is reduced. There is nothing.
  • the trench gate power semiconductor device 104 according to the third embodiment has the same configuration as that of the trench gate power semiconductor device 100 according to the first embodiment except for the depth position of the bottom surface of the groove 124. 1 has a corresponding effect among the effects of the trench gate power semiconductor device 100 according to 1.
  • the trench gate power semiconductor device of the present invention has been described based on the above embodiment, but the present invention is not limited to this, and can be implemented without departing from the scope of the present invention. The following modifications are also possible.
  • the multistage ion implantation method is performed by three-stage ion implantation, but the present invention is not limited to this.
  • the multistage ion implantation method may be performed by two-stage ion implantation, or the multistage ion implantation method may be performed by four or more stages of ion implantation.
  • FIG. 11 is a cross-sectional view of a trench gate power semiconductor device 200 according to a modification. As shown in FIG. 11, the present invention can be applied to, for example, a trench gate IGBT.
  • the semiconductor device of the present invention has been described with the first conductivity type as n-type and the second conductivity type as p-type.
  • the present invention is not limited to this.
  • the first conductivity type may be p-type and the second conductivity type may be n-type.
  • trench gate power semiconductor device 110, 210, 910 ... semiconductor substrate, 112, 912 ... drain layer, 113 ... n - type epitaxial layer, 114, 214, 914 ... drift layer, 120, 220 , 920 ... body layer, 124, 224, 924 ... groove, 126, 226, 926 ... gate insulating film, 126 '... silicon oxide film, 128' ... polysilicon layer, 128, 228, 928 ... gate electrode layer, 130, 230, 930 ... protective insulating film, 132, 932 ... source region, 134, 234, 934 ... contact region, 136, 936 ... source electrode layer, 138, 938 ... drain electrode layer, 140, 240 ... buried region, 142 ... n + Type semiconductor region 212 ... collector layer 232 emitter region 236 emitter current Polar layer, 238 ... collector electrode layer, 900 ... trench gate power MOSFET

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteurs de puissance à grille en tranchée (100) qui comporte : une couche de dérive de type n- (114) ; une couche de corps de type p (120) ; une rainure (124) ; et une région de source de type n+ (132) ; un film d'isolation de grille (126) qui est formé sur la surface périphérique interne de la rainure (124) ; un film d'électrode de grille (128) qui est formé sur la surface périphérique interne du film d'isolation de grille (126) ; et une couche d'électrode de source (136) qui est formée pour être en contact avec la région de source (132) tout en étant isolée du film d'électrode de grille (128). Dans la couche de dérive (114), une région prise en sandwich entre deux rainures adjacentes (124) comporte une région enfouie de type p (140) qui est en contact avec la couche de corps (120) et s'étend plus profondément que les rainures (124). Dans la région enfouie (140), la position de profondeur à laquelle la concentration en impuretés de type p est maximale se situe plus profondément qu'à mi-chemin entre la surface inférieure (P2) de la couche de corps (120) et la surface inférieure (P3) de la région enfouie (140). Ce dispositif à semi-conducteurs de puissance à grille en tranchée (100) a une tension de claquage inverse élevée et une résistance à l'état passant encore plus faible.
PCT/JP2012/063480 2011-05-27 2012-05-25 Dispositif à semi-conducteurs de puissance à grille en tranchée et son procédé de fabrication Ceased WO2012165329A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012540208A JP5554417B2 (ja) 2011-05-27 2012-05-25 トレンチゲートパワー半導体装置及びその製造方法
CN201280001820.1A CN103250254B (zh) 2011-05-27 2012-05-25 沟槽栅极功率半导体装置及其制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011119798 2011-05-27
JP2011-119798 2011-05-27

Publications (1)

Publication Number Publication Date
WO2012165329A1 true WO2012165329A1 (fr) 2012-12-06

Family

ID=47259186

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/063480 Ceased WO2012165329A1 (fr) 2011-05-27 2012-05-25 Dispositif à semi-conducteurs de puissance à grille en tranchée et son procédé de fabrication

Country Status (3)

Country Link
JP (1) JP5554417B2 (fr)
CN (1) CN103250254B (fr)
WO (1) WO2012165329A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014192191A (ja) * 2013-03-26 2014-10-06 Shindengen Electric Mfg Co Ltd 半導体装置及び半導体装置の製造方法
JP2016066780A (ja) * 2014-09-16 2016-04-28 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JPWO2015104949A1 (ja) * 2014-01-10 2017-03-23 三菱電機株式会社 炭化珪素半導体装置
JP2018537858A (ja) * 2015-12-02 2018-12-20 アーベーベー・シュバイツ・アーゲー 半導体装置およびその製造方法
US10374047B2 (en) 2017-02-07 2019-08-06 Rohm Co., Ltd. Semiconductor device and manufacturing method thereof
CN111883584A (zh) * 2020-08-06 2020-11-03 苏州华太电子技术有限公司 沟槽栅功率器件及提高沟槽栅器件栅极击穿电压的方法
CN113990755A (zh) * 2021-10-25 2022-01-28 安建科技有限公司 一种屏蔽栅mosfet器件的制造方法
CN115588668A (zh) * 2021-07-06 2023-01-10 现代摩比斯株式会社 功率半导体器件及制造其的方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105655394B (zh) * 2014-12-03 2018-12-25 瀚薪科技股份有限公司 碳化硅场效晶体管
CN106328697B (zh) * 2015-07-02 2019-02-15 无锡华润上华科技有限公司 具有沟槽栅极结构的半导体器件及其制造方法
CN108352402B (zh) * 2015-10-16 2020-12-18 富士电机株式会社 半导体装置和半导体装置的制造方法
CN109935517B (zh) * 2017-12-15 2020-11-27 深圳尚阳通科技有限公司 Sgt器件及其制造方法
CN109166918A (zh) * 2018-08-30 2019-01-08 中国科学院微电子研究所 一种绝缘栅双极晶体管及其制作方法
CN109244127A (zh) * 2018-08-30 2019-01-18 中国科学院微电子研究所 一种绝缘栅双极晶体管及其制作方法
CN110571270A (zh) * 2019-09-16 2019-12-13 全球能源互联网研究院有限公司 一种沟槽栅型igbt器件及其制备方法、装置
KR102596320B1 (ko) * 2021-07-06 2023-11-01 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
US12249642B2 (en) 2021-07-28 2025-03-11 Pakal Technologies, Inc. Vertical insulated gate power switch with isolated base contact regions
CN116799036B (zh) * 2023-06-11 2026-03-31 湖北九峰山实验室 宽禁带半导体沟槽mosfet器件结构及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266133A (ja) * 2006-03-27 2007-10-11 Toyota Central Res & Dev Lab Inc 半導体装置
JP2008124346A (ja) * 2006-11-14 2008-05-29 Toshiba Corp 電力用半導体素子
JP2009141243A (ja) * 2007-12-10 2009-06-25 Toshiba Corp 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534829B2 (en) * 1998-06-25 2003-03-18 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
JP4091921B2 (ja) * 2004-02-16 2008-05-28 松下電器産業株式会社 半導体装置及びその製造方法
JP2006332607A (ja) * 2005-04-28 2006-12-07 Nec Electronics Corp 半導体装置
US7687851B2 (en) * 2005-11-23 2010-03-30 M-Mos Semiconductor Sdn. Bhd. High density trench MOSFET with reduced on-resistance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266133A (ja) * 2006-03-27 2007-10-11 Toyota Central Res & Dev Lab Inc 半導体装置
JP2008124346A (ja) * 2006-11-14 2008-05-29 Toshiba Corp 電力用半導体素子
JP2009141243A (ja) * 2007-12-10 2009-06-25 Toshiba Corp 半導体装置

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014192191A (ja) * 2013-03-26 2014-10-06 Shindengen Electric Mfg Co Ltd 半導体装置及び半導体装置の製造方法
JPWO2015104949A1 (ja) * 2014-01-10 2017-03-23 三菱電機株式会社 炭化珪素半導体装置
US9972676B2 (en) 2014-01-10 2018-05-15 Mitsubishi Electric Corporation Silicon carbide semiconductor device
JP2016066780A (ja) * 2014-09-16 2016-04-28 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP2018537858A (ja) * 2015-12-02 2018-12-20 アーベーベー・シュバイツ・アーゲー 半導体装置およびその製造方法
US10374047B2 (en) 2017-02-07 2019-08-06 Rohm Co., Ltd. Semiconductor device and manufacturing method thereof
CN111883584A (zh) * 2020-08-06 2020-11-03 苏州华太电子技术有限公司 沟槽栅功率器件及提高沟槽栅器件栅极击穿电压的方法
CN115588668A (zh) * 2021-07-06 2023-01-10 现代摩比斯株式会社 功率半导体器件及制造其的方法
US12484271B2 (en) 2021-07-06 2025-11-25 Hyundai Mobis Co., Ltd. Power semiconductor device and method for fabricating the same
CN113990755A (zh) * 2021-10-25 2022-01-28 安建科技有限公司 一种屏蔽栅mosfet器件的制造方法

Also Published As

Publication number Publication date
CN103250254B (zh) 2016-07-06
CN103250254A (zh) 2013-08-14
JP5554417B2 (ja) 2014-07-23
JPWO2012165329A1 (ja) 2015-02-23

Similar Documents

Publication Publication Date Title
JP5554417B2 (ja) トレンチゲートパワー半導体装置及びその製造方法
JP6418340B2 (ja) 逆導通型絶縁ゲートバイポーラトランジスタの製造方法および逆導通型絶縁ゲートバイポーラトランジスタ
JP6864288B2 (ja) 半導体装置および半導体装置の製造方法
CN101939843B (zh) 半导体装置
JP6140823B2 (ja) 炭化珪素半導体装置
CN108604552B (zh) 半导体装置以及用于制造这种半导体装置的方法
CN108701617B (zh) 用于制造半导体装置的方法
JP2013062344A (ja) 半導体装置およびその製造方法
JP2012114209A (ja) 半導体装置及びその製造方法
WO2014115253A1 (fr) Dispositif à semi-conducteur en carbure de silicium et son procédé de fabrication
JP7182850B2 (ja) 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
WO2014207793A1 (fr) Dispositif à semi-conducteurs et son procédé de fabrication
JP5809877B2 (ja) トレンチゲート型パワー半導体装置の製造方法
JP2013168549A (ja) 半導体装置およびその製造方法
JP2024153517A (ja) 超接合炭化珪素半導体装置および超接合炭化珪素半導体装置の製造方法
JP3642768B2 (ja) 横型高耐圧半導体装置
JP2011176157A (ja) 半導体装置の製造方法
JP2005191247A (ja) 半導体基板及びそれを用いた半導体装置
JP6092680B2 (ja) 半導体装置及び半導体装置の製造方法
JP7543950B2 (ja) 超接合炭化珪素半導体装置の製造方法
CN102714218B (zh) 穿通半导体装置及其生产方法
JP2012248760A (ja) トレンチゲートパワー半導体装置及びその製造方法
JP5851717B2 (ja) 半導体装置及びその製造方法
JP2009224495A (ja) 絶縁ゲート型半導体装置およびその製造方法
TWI433311B (zh) 具有自對準矽化物接觸的功率裝置及其製造方法

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2012540208

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12793300

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12793300

Country of ref document: EP

Kind code of ref document: A1