WO2012169162A1 - Élément de renfort, boîtier de semi-conducteur, dispositif à semi-conducteur et procédé de fabrication pour un boîtier de semi-conducteur - Google Patents

Élément de renfort, boîtier de semi-conducteur, dispositif à semi-conducteur et procédé de fabrication pour un boîtier de semi-conducteur Download PDF

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Publication number
WO2012169162A1
WO2012169162A1 PCT/JP2012/003627 JP2012003627W WO2012169162A1 WO 2012169162 A1 WO2012169162 A1 WO 2012169162A1 JP 2012003627 W JP2012003627 W JP 2012003627W WO 2012169162 A1 WO2012169162 A1 WO 2012169162A1
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WIPO (PCT)
Prior art keywords
adhesive layer
conductor pattern
main body
semiconductor package
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2012/003627
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English (en)
Japanese (ja)
Inventor
岡田　亮一
賢也 橘
小野塚　偉師
猛 八月朔日
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
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Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2013519378A priority Critical patent/JP5994776B2/ja
Publication of WO2012169162A1 publication Critical patent/WO2012169162A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a reinforcing member, a semiconductor package, a semiconductor device, and a method for manufacturing a semiconductor package.
  • An interposer used for a new package such as a BGA or a CSP is generally formed by forming a conductor pattern or a conductor post on a substrate formed by impregnating a fiber base material with a resin composition.
  • the interposer as described above has a large difference in thermal expansion coefficient from the chip and is easily thermally deformed. Further, since the interposer usually has a larger area than the chip, the area of the portion not in contact with the chip is large. Such a portion not in contact with the chip has a problem that rigidity is extremely low, the interposer is thermally deformed, warps toward the chip side, and reliability of electrical connection is lowered.
  • the substrate the first conductor pattern provided on the one surface side of the substrate, and the first conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern.
  • a reinforcing member joined to at least one of the one surface and the other surface of a wiring board having two conductor patterns, the plate-shaped main body and one surface side of the main body And an adhesive layer for joining the main body and the wiring board, wherein the adhesive layer is provided with a reinforcing member including a heat conductive material.
  • the adhesive layer of the reinforcing member includes a heat conductive material, heat from the wiring board can be transmitted to the main body, and thermal deformation of the wiring board can be suppressed.
  • the main body of a reinforcement member is plate shape, it is easy to form an adhesive layer. Since the reinforcing member has an adhesive layer, it can be easily joined to the wiring board.
  • a semiconductor package having the above-described reinforcing member can also be provided. That is, according to the present invention, the substrate, the first conductor pattern provided on one surface side of the substrate, and the other surface side of the substrate are electrically connected to the first conductor pattern.
  • a wiring board provided with the second conductor pattern, a semiconductor element electrically connected to the first conductor pattern, and at least one of the one surface and the other surface, the adhesive layer It is possible to provide a semiconductor package characterized by having the above-described reinforcing member to which is bonded.
  • the substrate, the first conductor pattern provided on one surface side of the substrate, and the other surface side of the substrate are electrically connected to the first conductor pattern.
  • a semiconductor package manufacturing method comprising a second step and a third step of obtaining a reinforcing member by processing the plate member bonded to the wiring board into a desired shape. Can be offered .
  • the plate member since the adhesive layer is formed on the plate member, the plate member can be easily joined to the wiring board. And since an adhesive layer contains a heat conductive material, the heat
  • the substrate the first conductor pattern provided on one surface side of the substrate, the first conductor pattern provided on the other surface side of the substrate, and electrically connected to the first conductor pattern.
  • a wiring board having two conductor patterns; a semiconductor element electrically connected to the first conductor pattern or the second conductor pattern of the wiring board; and a reinforcing member joined to the one surface of the wiring board.
  • the reinforcing member includes an adhesive layer that adheres to the wiring board and includes a thermally conductive material, and a main body provided on the adhesive layer, and the main body penetrates the main body.
  • the adhesive layer is formed with an opening that communicates with the opening of the main body and exposes the first conductor pattern, and is a plan view from the one surface side of the wiring board.
  • a semiconductor package in which a peripheral edge portion of the opening of the layer is located inside the opening of the main body, and solder bumps connected to the first conductor pattern are disposed in the opening of the adhesive layer can be provided. .
  • Such a semiconductor package can be manufactured by the semiconductor package manufacturing method described above.
  • the manufacturing method of the semiconductor package which uses the reinforcement member mentioned above can also be provided. That is, according to the present invention, the substrate, the first conductor pattern provided on one surface side of the substrate, and the other surface side of the substrate are electrically connected to the first conductor pattern. And a film-like solder resist provided on the one surface side of the substrate so as to cover the first conductor pattern and having an opening exposing a predetermined portion of the first conductor pattern.
  • a wiring board is prepared, and has a plate-shaped main body and an adhesive layer provided on one surface side of the main body and including a heat conductive material, and a through-hole penetrating the main body and the adhesive layer is formed.
  • a semiconductor package comprising: a first step of preparing a reinforced reinforcing member; and a second step of bonding the adhesive layer of the reinforcing member to the solder resist and communicating the through hole and the opening of the solder resist. Manufacturing method can also be provided.
  • a reinforcing member that can prevent the occurrence of problems due to heat and can be easily joined to a wiring board, a semiconductor package including the reinforcing member, a semiconductor device, and the reinforcing member.
  • a method for manufacturing the semiconductor package is provided. Furthermore, the manufacturing method which can manufacture the semiconductor package by which generation
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention. It is a top view which shows the semiconductor package shown in FIG. It is a bottom view which shows the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is sectional drawing which shows typically a semiconductor device provided with the semiconductor package shown in FIG. It is sectional drawing which shows typically the semiconductor package which concerns on 2nd Embodiment of this invention.
  • FIG. 7 is a cross-sectional view showing a manufacturing process of the semiconductor package shown in FIG. 1. It is sectional drawing which shows typically the semiconductor package which concerns on 5th Embodiment of this invention.
  • (A) (b) (c) is sectional drawing which shows the manufacturing process of the semiconductor package shown in FIG. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor package shown in FIG.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention
  • FIG. 2 is a top view showing the semiconductor package shown in FIG. 1
  • FIG. 3 shows the semiconductor package shown in FIG. 4 and 7 are views showing an example of a method for manufacturing the semiconductor package shown in FIG.
  • the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”. 1 to 7, each part of the semiconductor package is exaggerated for convenience of explanation.
  • a semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member (reinforcing member of the present invention) 4, and a second reinforcing member ( The reinforcing member 5 of the present invention.
  • both surfaces of the wiring board 2 are reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. Increases overall rigidity.
  • the thermal expansion coefficients of the first reinforcing member 4 and the second reinforcing member 5 are smaller than those of the wiring board 2, the wiring board 2 caused by the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3. Warping can be suppressed or prevented.
  • the adhesive layers 42 and 52 include a thermally conductive material. Therefore, the heat of the wiring board 2 can be radiated through the first reinforcing member 4 and the second reinforcing member 5. Furthermore, heat from the semiconductor element 3 can be released through the wiring board 2 and the second reinforcing member 5. Therefore, the semiconductor package 1 can exhibit excellent heat dissipation.
  • the wiring board 2 is a board that supports the semiconductor element 3, and is, for example, a relay board (interposer) that relays electrical connection between the mounted semiconductor element 3 and a mother board 200 as will be described later.
  • the wiring substrate 2 is usually a quadrangle such as a square or a rectangle in plan view.
  • the wiring board 2 includes a substrate 21, conductor patterns 221, 222, 223, 224, conductor posts 231, 232, 233, a heat transfer post 24, and solder resists 25, 26.
  • the conductor pattern 221 constitutes a first conductor pattern provided on one surface side of the substrate 21, and the conductor pattern 224 is provided on the other surface side of the substrate 21.
  • a second conductor pattern electrically connected to the conductor pattern is formed.
  • the saddle substrate 21 is composed of a plurality of (in this embodiment, three layers) insulating layers 211, 212, and 213. More specifically, the substrate 21 is configured by laminating an insulating layer 211, an insulating layer 212, and an insulating layer 213 in this order. In addition, the number of the insulating layers which comprise the board
  • substrate 21 is not limited to this, One or two layers may be sufficient, and four or more layers may be sufficient.
  • Each insulating layer 211, 212, 213 is made of an insulating material. Specifically, each insulating layer 211, 212, 213 is composed of a base material (fiber base material) and a resin composition impregnated in the base material.
  • the eaves base material is used as a core material for the insulating layers 211, 212, and 213. By having such a base material, the rigidity of the substrate 21 can be increased.
  • the base material examples include glass fiber base materials composed of glass fibers such as glass woven fabrics and glass nonwoven fabrics, polyamide resin fibers such as polyamide resin fibers, aromatic polyamide resin fibers, wholly aromatic polyamide resin fibers, and polyesters. Synthesis composed of woven or non-woven fabric mainly composed of at least one of resin fiber, aromatic polyester resin fiber, polyester resin fiber such as wholly aromatic polyester resin fiber, polyimide resin fiber, fluororesin fiber, etc. Examples thereof include a fiber base material, or a paper base material mainly composed of craft paper, cotton linter paper, mixed paper of linter and kraft pulp, or the like. Among these, as such a base material, a glass fiber base material is preferable. Thereby, the rigidity of the substrate 21 can be increased and the substrate 21 can be thinned. Furthermore, the thermal expansion coefficient of the substrate 21 can be reduced.
  • the glass constituting such a glass fiber substrate include one or more of E glass, C glass, A glass, S glass, D glass, NE glass, T glass, H glass, and the like.
  • T glass is preferable.
  • the content of the base material in the insulating layers 211, 212, and 213 is preferably 30 to 70 wt%, and preferably 40 to 60 wt%. Is more preferable. Thereby, the electric insulation and thermal expansion coefficient of each insulating layer can be made sufficiently low while reliably preventing damage such as cracks of these insulating layers.
  • at least 1 layer of the insulating layers 211, 212, and 213 may be comprised only with the resin composition, without including a base material.
  • the resin composition impregnated in such a base material contains a resin material.
  • a resin material a thermosetting resin is preferably used.
  • thermosetting resin examples include novolak type phenol resins such as phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, unmodified resole phenol resin, oil-modified resole modified with tung oil, linseed oil, walnut oil, and the like.
  • Phenol resin such as phenolic resin, bisphenol type epoxy resin such as bisphenol A epoxy resin, bisphenol F epoxy resin, novolac epoxy resin, novolac epoxy resin such as cresol novolac epoxy resin, biphenyl type epoxy resin, etc.
  • cyanate resin is particularly preferable.
  • substrate 21 can be made small enough.
  • the electrical characteristics (low dielectric constant, low dielectric loss tangent, etc.) of the substrate 21 can be made excellent.
  • each of the insulating layers 211, 212, and 213 preferably contains a filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, and 213 can be lowered.
  • Examples of the filler include various inorganic fillers or organic fillers.
  • Examples of the inorganic filler include oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide and metal ferrite, and hydroxide such as aluminum hydroxide and magnesium hydroxide.
  • examples of the organic filler include synthetic resin powder.
  • examples of the synthetic resin powder include alkyd resin, epoxy resin, silicone resin, phenol resin, polyester, acrylic resin, acetal resin, polyethylene, polyether, polycarbonate, polyamide, polysulfone, polystyrene, polyvinyl chloride, fluororesin, and polypropylene.
  • various thermosetting resins such as ethylene-vinyl acetate copolymers or powders of thermoplastic resins, or powders of copolymers of these resins may be mentioned.
  • Other examples of organic fillers include aromatic or aliphatic polyamide fibers, polypropylene fibers, polyester fibers, and aramid fibers.
  • the thermal expansion coefficient of the insulating layers 211, 212, and 213 can be effectively lowered.
  • the heat transfer properties of the insulating layers 211, 212, and 213 can be increased.
  • silica is preferable, and fused silica (particularly spherical fused silica) is preferable in that it has excellent low thermal expansion.
  • the average particle diameter of the inorganic filler is not particularly limited, but is preferably 0.05 to 2.0 ⁇ m, particularly preferably 0.1 to 1.0 ⁇ m. Accordingly, the inorganic filler can be more uniformly dispersed in the insulating layers 211, 212, and 213, and the physical strength and insulating properties of the insulating layers 211, 212, and 213 can be made particularly excellent. .
  • the average particle size of the inorganic filler can be measured by, for example, a particle size distribution meter (manufactured by HORIBA, LA-500). Moreover, in this specification, an average particle diameter refers to the average particle diameter on a volume basis.
  • the content of the inorganic filler in the insulating layers 211, 212, and 213 is not particularly limited, but is preferably 30 to 80 wt%, particularly 45 to 75 wt% when the resin composition excluding the substrate is 100 wt%. Is preferred. When the content is within the above range, the insulating layers 211, 212, and 213 have sufficiently low thermal expansion coefficients and particularly low hygroscopicity.
  • the resin composition may contain a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, and a polyethersulfone resin in addition to the thermosetting resin described above.
  • a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, and a polyethersulfone resin in addition to the thermosetting resin described above.
  • the resin composition may contain additives other than the above components such as pigments and antioxidants, as necessary.
  • the insulating layers 211, 212, and 213 may be made of the same material, or may be made of different materials.
  • the average thickness of the substrate 21 composed of a plurality of layers as described above is not particularly limited, but is preferably 30 ⁇ m or more and 800 ⁇ m or less, and more preferably 30 ⁇ m or more and 400 ⁇ m or less.
  • a conductor pattern 221 is formed on the upper surface of the insulating layer 211 of the substrate 21.
  • a conductor pattern 222 is interposed between the insulating layer 211 and the insulating layer 212.
  • a conductor pattern 223 is interposed between the insulating layer 212 and the insulating layer 213.
  • a conductor pattern 224 is formed on the lower surface of the insulating layer 213.
  • Each of the conductor patterns 221, 222, 223, and 224 functions as a circuit having a plurality of wirings.
  • the constituent material of the conductor patterns 221, 222, 223, and 224 is not particularly limited as long as it has conductivity, and examples thereof include various metals and various alloys such as copper, a copper-based alloy, aluminum, and an aluminum-based alloy. Can be mentioned. Among these, it is preferable to use copper and a copper-based alloy as the constituent material. Copper and copper-based alloys have relatively high electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be improved. Moreover, since copper and a copper-type alloy are excellent also in heat conductivity, the heat dissipation of the wiring board 2 can also be improved.
  • the average thickness of the conductor patterns 221, 222, 223, and 224 is not particularly limited, but is preferably 5 ⁇ m or more and 30 ⁇ m or less.
  • a via hole penetrating in the thickness direction is formed in the insulating layer 211, and a conductor post (via post) 231 is provided in the via hole.
  • the conductor post 231 penetrates the insulating layer 211 in the thickness direction, and the conductor pattern 221 and the conductor pattern 222 are electrically connected via the conductor post 231.
  • the insulating layer 212 is provided with a conductor post (via post) 232 that penetrates in the thickness direction.
  • the conductor post 232 penetrates the insulating layer 212 in the thickness direction, and the conductor pattern 222 and the conductor pattern 223 are electrically connected via the conductor post 232.
  • the insulating layer 213 is provided with a conductor post (via post) 233 that penetrates in the thickness direction.
  • the conductor post 233 penetrates the insulating layer 213 in the thickness direction, and the conductor pattern 223 and the conductor pattern 224 are electrically connected via the conductor post 233.
  • solder resist 25 having a through hole at a predetermined portion is formed on the upper surface of the insulating layer 211.
  • the solder resist 25 covers the conductor pattern 221 and the connection electrode portion of the conductor pattern 221 is exposed from the through hole.
  • a metal bump (solder bump) 31 is bonded to the exposed portion, and the semiconductor element 3 and the conductor pattern 221 are electrically connected through the metal bump 31.
  • the solder resist 25 has insulating properties, prevents solder from adhering to unnecessary portions of the conductor pattern 221, protects the conductor pattern 221 from dust, heat, moisture, etc. It is formed for the purpose of maintaining insulation.
  • the constituent material of the solder resist 25 is not particularly limited as long as it has an insulating property.
  • a thermosetting resist mainly composed of an epoxy resin can be used.
  • those commercially available under the trade names of PSR4000 / AUS308, AUS703 (manufactured by Taiyo Ink Manufacture) and SR-7200G (manufactured by Hitachi Chemical Co., Ltd.) can be used.
  • the method of forming the solder resist 25 is not particularly limited.
  • a through hole may be formed by laser processing, or a photosensitive liquid resist is screen-printed, A method of exposure curing may be used.
  • solder resist 26 having a through hole at a predetermined portion is formed on the lower surface of the insulating layer 213.
  • the solder resist 26 covers the conductor pattern 224, and the connection electrode portion of the conductor pattern 224 is exposed from the through hole.
  • Metal bumps (solder bumps) 71 are joined to the exposed portions.
  • the metal bump 71 is for electrically connecting the semiconductor package 1 to, for example, a mother board as will be described later.
  • the metal bump 71 has a substantially spherical shape.
  • the shape of the metal bump 71 is not limited to this.
  • the constituent material of the metal bump 71 is not particularly limited.
  • tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, tin-- Any one or more of various brazing materials (solder) such as copper and tin-silver-copper can be used.
  • a plurality of via holes penetrating in the thickness direction are formed in the substrate 21, and a heat transfer post 24 is provided in each via hole.
  • Each heat transfer post 24 penetrates the entire substrate 21 in the thickness direction, and its upper end is exposed from the upper surface of the insulating layer 211 and its lower end is exposed from the lower surface of the insulating layer 213.
  • the heat transfer post 24 has an upper end in contact with the first reinforcing member 4 and a lower end in contact with the second reinforcing member 5.
  • the heat transfer post 24 includes heat transfer post portions 241, 242, and 243.
  • the heat transfer post portion 241 is a solid columnar member that penetrates the insulating layer 211.
  • the heat transfer post portion 242 includes a hollow first portion that penetrates the insulating layer 212, and a second portion that is connected to the hollow portion 242 ⁇ / b> A and located on the front and back surfaces of the insulating layer 212.
  • the heat transfer post portion 241 is connected to the second portion.
  • a heat transfer post portion 243 is connected to the other second portion.
  • the heat transfer post portion 243 is a solid columnar member that penetrates the insulating layer 213.
  • the adhesive layer 42 of the first reinforcing member 4 enters the opening formed in the solder resist 25 and directly contacts one end portion (heat transfer post portion 241) of the heat transfer post 24 exposed from the opening. is doing.
  • the adhesive layer 52 of the second reinforcing member 5 enters the opening formed in the solder resist 26 and directly contacts the other end (heat transfer post 243) of the heat transfer post 24 exposed from the opening. is doing.
  • Each heat transfer post (heat conducting portion) 24 has higher heat transfer performance than the substrate 21 (insulating layer) described above. Thereby, for example, heat can be efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 via the heat transfer post 24. As a result, the heat dissipation of the semiconductor package 1 can be improved.
  • each of the heat transfer posts 24 penetrates the substrate 21 in the thickness direction, the heat transfer posts 24 can be formed easily and with high accuracy in the same manner as known conductor posts.
  • each heat transfer post 24 may be hollow or solid. Moreover, it does not specifically limit as a cross-sectional shape of each heat-transfer post
  • Each heat transfer post 24 does not contribute to the transmission of electrical signals. Thereby, heat can be more efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 through the heat transfer post 24.
  • the plurality of heat transfer posts 24 are juxtaposed along the outer peripheral portion of the wiring board 2 at intervals when the wiring board 2 is viewed in plan.
  • the plurality of heat transfer posts 24 are preferably arranged side by side at equal intervals in the circumferential direction along the outer peripheral portion of the wiring board 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring board 2 can be made more uniform.
  • the plurality of heat transfer posts 24 are provided so as not to overlap the conductor patterns 221, 222, 223, and 224 described above when the wiring board 2 is viewed in plan. Thereby, formation of the heat transfer post 24 is simplified, and a short circuit between the heat transfer post 24 and the conductor patterns 221, 222, 223, and 224 can be prevented.
  • each heat transfer post 24 is not particularly limited as long as it has a higher heat transfer property than the substrate 21 (insulating layer) described above, but a metal material is preferably used.
  • Such metal materials include various metals and various alloys such as copper, copper-based alloys, aluminum, and aluminum-based alloys. Among these, it is preferable to use at least one of copper, copper-based alloy, aluminum, and aluminum-based alloy as the metal material from the viewpoint of excellent heat conductivity. Thereby, the heat dissipation of the wiring board 2 can also be improved.
  • the constituent material of the heat transfer post 24 may be different from the constituent material of the conductor posts 231 to 233 described above, but is preferably the same as the constituent material of the conductor posts 231 to 233.
  • the semiconductor element 3 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light receiving / emitting element.
  • IC integrated circuit element
  • the semiconductor element 3 is bonded to the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above, and is electrically connected to the conductor pattern 221 that is the first conductor pattern.
  • the semiconductor element 3 is provided with a plurality of terminals (not shown) on the lower surface thereof, and each of the terminals is connected to the connection electrode portion (on the conductor pattern 221 of the wiring board 2 via the metal bump 31 ( Terminal). Thereby, the semiconductor element 3 and the conductor pattern 221 of the wiring board 2 are electrically connected.
  • the constituent material of the metal bump 31 is not particularly limited, but is similar to the metal bump 71 described above, for example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin
  • seed brazing materials such as silver-bismuth, tin-copper, tin-silver-copper can be used.
  • the adhesive layer 32 is made of a material having adhesiveness and insulation, and is made of, for example, a cured product of an underfill material.
  • the underfill material is not particularly limited, and a known underfill material can be used, but the same solder bonding resist as that for forming an insulating material 81 described later can also be used.
  • a thermally conductive member (for example, silver paste) is disposed between the side surface of the semiconductor element 3 and the inner surface of the through hole 4 b of the first reinforcing member 4, and the heat of the semiconductor element 3 is transferred to the first reinforcing member 4. Heat may be transferred.
  • the first reinforcing member (reinforcing member of the present invention; stiffener) 4 is joined to the above-described upper surface (one surface) of the substrate 21 of the wiring board 2 where the semiconductor element 3 is not joined.
  • the fact that the reinforcing member is bonded to the surface of the substrate 21 is not only in direct contact with the surface of the substrate 21, but also through a conductor pattern or a solder resist formed on the surface of the substrate 21. It includes the case where it is indirectly bonded to the surface of the substrate 21.
  • the first reinforcing member 4 includes a main body 41 and an adhesive layer 42 that is provided on the lower surface (one surface) of the main body 41 and joins the main body 41 and the wiring board 2.
  • the main body 41 has a smaller coefficient of thermal expansion than the substrate 21 and the wiring substrate 2. Thereby, by attaching the reinforcing member to the wiring board 2, the thermal expansion of the board 21 and further the wiring board 2 can be suppressed.
  • the thermal expansion coefficient of the wiring board 2 is preferably 5 ppm / ° C. to 25 ppm / ° C.
  • the thermal expansion coefficient means an average linear expansion coefficient in the plane direction at 50 ° C. to 150 ° C.
  • the main body 41 has a plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.
  • the front and back surfaces of the main body 41 are flat.
  • the front and back surfaces of the main body 41 are not formed with unevenness (for example, unevenness of 5 ⁇ m or more) formed by wiring, for example, and are flat.
  • the flat adhesive layer 42 having a uniform thickness can be easily formed. Therefore, the adhesive layer 42 and the surface of the wiring board 2 can be securely bonded.
  • the surface (that is, the upper surface) opposite to the substrate 21 of the main body 41 is located on the same surface as the surface (that is, the upper surface) opposite to the substrate 21 of the semiconductor element 3 or on the substrate 21 side (that is, the lower side). It is preferable. Thereby, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the installation of the semiconductor element 3 is facilitated.
  • the upper surface of the main body 41 and the upper surface of the semiconductor element 3 are located on the same plane. Thereby, the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned. Moreover, when providing another structure (for example, a board
  • the main body 41 and the semiconductor element 3 may be molded with a sealing resin.
  • the main body 41 is provided so as to surround the periphery of the semiconductor element 3.
  • the main body 41 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the effect which raises the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.
  • the distance between the main body 41 and the semiconductor element 3 (the distance between the inner surface of the opening 412 of the main body 41 and the outer peripheral surface of the semiconductor element 3) is constant over the entire circumference of the semiconductor element 3. Is formed. Thereby, the integrity of the main body 41 and the semiconductor element 3 is increased, and the reinforcing effect of the wiring board 2 by these is suitably exhibited.
  • the main body 41 preferably has a difference in thermal expansion coefficient with the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the main body 41 can integrally reinforce the wiring board 2 and suppress the thermal expansion of the entire semiconductor package 1.
  • the constituent material of the main body 41 is not particularly limited as long as it has a thermal expansion coefficient as described above.
  • any of a metal material, a ceramic material, and the like can be used. Then, a metal material is used.
  • the main body 41 is made of a metal material, the heat dissipation of the main body 41 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.
  • Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.
  • Examples of such an alloy containing Fe include one or more of an Fe—Ni alloy, an Fe—Co—Cr alloy, an Fe—Co alloy, an Fe—Pt alloy, an Fe—Pd alloy, and the like. In particular, it is preferable to use an Fe—Ni alloy.
  • Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the semiconductor element 3 and the main body 41 can integrally reinforce the wiring board 2.
  • the Fe—Ni alloy is not particularly limited as long as it contains Fe and Ni.
  • the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included.
  • Fe—Ni alloys include Fe—Ni alloys such as Fe-36Ni alloy (Invar), Fe-32Ni-5Co alloy (Super Invar), and Fe-29Ni-17Co alloy (Kovar). And Fe-Ni-Co alloys such as Fe-36Ni-12Co alloy (Erin bar), Ni-Mo-Fe alloys such as Fe-Ni-Cr-Ti alloy and Ni-28Mo-2Fe alloy.
  • Fe—Ni—Co alloys are commercially available under trade names such as KV series (manufactured by NEOMAX Materials) such as KV-2, KV-4, KV-6, KV-15, KV-25, and Nivarox. ing.
  • Fe—Ni alloys are commercially available under trade names such as NS-5 and D-1 (manufactured by NEOMAX Materials).
  • Fe—Ni—Cr—Ti alloys are commercially available under trade names such as, for example, Ni-Span C-902 (manufactured by Daido Special Metal), EL-3 (manufactured by NEOMAX Material).
  • the Fe—Co—Cr alloy is not particularly limited as long as it contains Fe, Co, and Cr.
  • an Fe—Co—Cr alloy such as Fe-54Co-9.5Cr (stainless invar) is used. Can be mentioned.
  • the Fe—Co—Cr-based alloy may contain one or more metals of metals such as Ni, Ti, Mo, Pd, and Pt in addition to Fe, Co, and Cr.
  • the Fe—Co alloy is not particularly limited as long as it contains Fe and Co.
  • one of metals such as Ni, Ti, Mo, Cr, Pd, and Pt is used. Or 2 or more types of metals may be included.
  • the Fe—Pt alloy is not particularly limited as long as it contains Fe and Pt.
  • one of metals such as Co, Ni, Ti, Mo, Cr, and Pd is used. Or 2 or more types of metals may be included.
  • the Fe—Pd alloy is not particularly limited as long as it contains Fe and Pd.
  • one of metals such as Co, Ni, Ti, Mo, Cr, and Pt is used. It may contain seeds or two or more metals.
  • the thermal expansion coefficient of the main body 41 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably.
  • the difference in thermal expansion coefficient between the semiconductor element 3 and the main body 41 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the absolute value of the difference in thermal expansion coefficient between the main body 41 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and further preferably 2 ppm / ° C. or less. .
  • the difference in thermal expansion coefficient between the semiconductor element 3 and the main body 41 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the Fe—Ni alloy when the metal material constituting the main body 41 is an Fe—Ni alloy, the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less. Thereby, the thermal expansion coefficient of the main body 41 can be brought close to the thermal expansion coefficient of the semiconductor element 3.
  • the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.
  • the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less.
  • the total content of is more preferably 90 wt% or more and 100 wt% or less. That is, in the Fe—Ni-based alloy, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. .
  • the thermal expansion coefficient of the main body 41 can be brought close to the thermal expansion coefficient of the semiconductor element 3.
  • the average thickness of the main body 41 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, etc. of the wiring board 2, and is not particularly limited. It is about 0.8 mm or less. Moreover, since the main body 41 is comprised with a metal material, the surface is electroconductivity and it has heat conductivity.
  • the heel adhesive layer 42 is provided on the lower surface of the main body 41 and has substantially the same shape as that of the main body 41 in plan view of the main body 41. That is, the adhesive layer 42 is provided over the entire lower surface of the main body 41.
  • the adhesive layer 42 has a function of joining the main body 41 to the wiring board 2.
  • Such an adhesive layer 42 has thermal conductivity, and is composed of a resin composition including a resin material and a heat conductive material. Thereby, it is possible to obtain the adhesive layer 42 that exhibits a sufficient function as the adhesive layer and is excellent in thermal conductivity. Therefore, the heat from the wiring board 2 can be efficiently transmitted to the main body 41, and the heat dissipation of the semiconductor package 1 can be improved.
  • the adhesive layer 42 has an insulating property. Thereby, the short circuit with the conductor pattern 221 and the main body 41 can be prevented, and the reliability of the semiconductor package 1 improves.
  • Examples of the resin material contained in the resin composition include various thermoplastic resins and various thermosetting resins.
  • thermoplastic resin examples include polyolefins such as polyethylene, polypropylene, and ethylene-vinyl acetate copolymer, modified polyolefins, polyamides (eg, nylon 6, nylon 46, nylon 66, nylon 610, nylon 612, nylon 11, nylon 12).
  • polyolefins such as polyethylene, polypropylene, and ethylene-vinyl acetate copolymer
  • modified polyolefins eg, nylon 6, nylon 46, nylon 66, nylon 610, nylon 612, nylon 11, nylon 12.
  • thermoplastic polyimide aromatic polyester and other liquid crystal polymers
  • polyphenylene oxide polyphenylene sulfide
  • polycarbonate polymethyl methacrylate
  • polyether polyether ether ketone
  • polyether imide polyacetal
  • Styrene polyolefin
  • polyvinyl chloride polyurethane
  • polyester polyamide
  • polybutadiene polybutadiene
  • trans polyisoprene fluoro rubber
  • thermoplastic elastomers such as chlorinated polyethylene and the like, or copolymers, blends, polymer alloys, etc. mainly composed of these, can be used, and one or more of these can be used in combination. .
  • thermosetting resin examples include epoxy resins, phenol resins, urea resins, melamine resins, polyester (unsaturated polyester) resins, polyimide resins, silicone resins, polyurethane resins, and the like. Or 2 or more types can be mixed and used.
  • thermosetting resin particularly, a liquid that forms a liquid before curing
  • a phenol resin or an epoxy resin more preferably a phenol resin.
  • phenolic resins include phenol novolac resins, cresol novolac resins, novolac type phenol resins such as bisphenol A novolac resins, unmodified resole phenol resins, oil-modified resole phenol resins modified with paulownia oil, linseed oil, walnut oil, etc.
  • examples thereof include phenolic resins such as resol type phenolic resins.
  • the heat conductive material contained in the resin composition is not particularly limited, but is preferably an inorganic filler (inorganic filler). Thereby, the thermal conductivity of the adhesive layer 42 can be further increased.
  • inorganic fillers examples include metals such as Au, Ag, and Pt, oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, and metal ferrite, boron nitride, and nitridation.
  • metals such as Au, Ag, and Pt
  • oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, and metal ferrite, boron nitride, and nitridation.
  • Nitride such as silicon, gallium nitride and titanium nitride, hydroxide such as aluminum hydroxide and magnesium hydroxide, carbonate such as calcium carbonate (light and heavy), magnesium carbonate, dolomite and dawsonite, calcium sulfate and barium sulfate , Sulfates or sulfites such as ammonium sulfate, calcium sulfite, talc, mica, clay, glass fiber, calcium silicate, montmorillonite, bentonite and other silicates, zinc borate, barium metaborate, aluminum borate, calcium borate , Borate such as sodium borate, carbon bra One or more of carbon such as carbon, graphite, and carbon fiber, iron powder, copper powder, aluminum powder, zinc white, molybdenum sulfide, boron fiber, potassium titanate, and lead zirconate titanate.
  • the insulation process is performed to the site
  • the insulation process is performed to the site
  • the insulation process is performed to
  • oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, and metal ferrite, boron nitride, and nitridation from the viewpoint of excellent insulation and thermal conductivity. Any one or more of nitrides such as silicon, gallium nitride, and titanium nitride are preferable.
  • the average particle size (d50) of the inorganic filler is preferably 0.05 to 100 ⁇ m, and more preferably 1 to 50 ⁇ m, from the viewpoints of enhancing thermal conductivity and dispersibility.
  • the content of the inorganic filler in the adhesive layer 42 is preferably 20 wt% or more from the viewpoint of thermal conductivity, more preferably 30 wt% or more, and 95 wt% from the viewpoint of moldability of the adhesive layer 42. Or less, more preferably 90 wt% or less.
  • the adhesive layer 42 includes a heat conductive material
  • the main body 41 is also formed of a heat conductive member, and the adhesive layer 42 directly contacts the surface of the main body 41.
  • the average thickness of the adhesive layer 42 is not particularly limited, but is, for example, about 0.01 mm or more and 0.2 mm or less.
  • the first reinforcing member 4 has a through hole 4b.
  • the through hole 4 b penetrates the main body 41 and the adhesive layer 42.
  • the through-hole 4 b includes an opening 412 that penetrates the main body 41 and an opening 423 that communicates with the opening 412 and penetrates the adhesive layer 42.
  • the diameter of the opening 412 that penetrates the main body 41 is equal to the diameter of the opening 423 that penetrates the adhesive layer 42.
  • the through hole 4 b is a hole for arranging the semiconductor element 3, and is formed in the central portion of the first reinforcing member 4 when viewed from the surface side of the first reinforcing member 4.
  • the first reinforcing member 4 is formed with a plurality of through holes 4a for exposing predetermined portions (connecting electrode portions) of the conductor pattern 221.
  • the through hole 4 a penetrates the main body 41 and the adhesive layer 42. That is, the through hole 4 a includes an opening 411 that penetrates the main body 41 and an opening 420 that communicates with the opening 411 and penetrates the adhesive layer 42.
  • the diameter of the opening 411 that penetrates the main body 41 is equal to the diameter of the opening 420 that penetrates the adhesive layer 42.
  • the plurality of through holes 4 a are arranged in parallel along the inner peripheral portion of the first reinforcing member 4 at intervals.
  • the plurality of through holes 4 a are arranged in parallel along the inner peripheral portion of the first reinforcing member 4 at equal intervals in the circumferential direction.
  • the mechanical strength of the 1st reinforcement member 4 can be equalize
  • the through hole 4a is disposed so as to surround the through hole 4b.
  • the metal bump 91 described later is disposed in the through hole 4a, the diameter of the through hole 4a is larger than that of the metal bump 91, and the insulating material 82 is filled between the metal bump 91 and the through hole 4a.
  • the insulating material 82 is filled between the inner surface of the opening 411 and the metal bump 91 and between the inner surface of the opening 420 and the metal bump 71.
  • metal bumps 91 connected to the conductor pattern 221 exposed from the through hole 4a, and contact between the metal bumps (solder bumps) 91 and the main body 41 (short circuit) formed around the metal bumps 91 are provided. And an insulating insulating material 82 for preventing the above.
  • the metal bump 91 is made of the same material as the metal bump 71 described above. It protrudes upward from the upper surface of the first reinforcing member 4. Thereby, the semiconductor package 1 can be electrically connected to another semiconductor package located above the metal package 91 via the metal bump 91.
  • the insulating material 82 has the same material configuration as the insulating material 81 described later.
  • the insulating material 82 surrounds the base side surface of the metal bump 91 on the conductor pattern 221 side and is in contact with the metal bump 91.
  • the insulating material 82 has a shape that spreads from the side surface side of the metal bump 91 toward the conductor pattern 221 side. That is, the insulating material 82 has a trapezoidal shape in a side view from a direction orthogonal to the wiring board thickness direction.
  • the metal bump 91 is reinforced by the insulating material 82, and the contact between the metal bump 91 and the main body 41 is prevented by the insulating material 82.
  • the insulating materials 82 and 81 may be semi-cured in the semiconductor package or may be completely cured.
  • the second reinforcing member (reinforcing member of the present invention; stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2.
  • the second reinforcing member 5 includes a main body 51 and a heat conductive adhesive layer 52 provided on the upper surface of the main body 51, similarly to the first reinforcing member 4 described above.
  • the bag body 51 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.
  • the bag body 51 has a smaller thermal expansion coefficient than the substrate 21 and the wiring substrate 2.
  • the main body 51 includes a portion (frame portion) 511 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21) and the metal bumps 71. And a portion 512 provided therebetween.
  • the main body 51 can effectively reinforce the wiring board 2 by joining the portion 511 of the main body 51 and the wiring board 2 (board 21).
  • the rigidity of the main body 51 is increased by joining the portion 512 of the main body 51 and the wiring board 2.
  • the main body 51 has a plurality of openings (through holes) 513 formed so as to surround the metal bumps 71 without contacting the metal bumps 71 described above.
  • the ratio of the area which the main body 51 occupies in the lower surface of the wiring board 2 can be enlarged.
  • the effect of increasing the rigidity of the wiring board 2 by the main body 51 can be made excellent.
  • each opening 513 has a circular shape in plan view.
  • the planar view shape of each opening part 513 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.
  • each opening 513 is provided corresponding to each metal bump 71 (one-to-one correspondence).
  • the rigidity of the main body 51 can be made uniform.
  • the heat dissipation of the main body 51 can also be improved.
  • the distance between the main body 51 and each metal bump 71 (that is, the distance between the wall surface of the opening 513 and the outer peripheral surface of the metal bump 71 in plan view) is constant over the entire circumference of the metal bump 71. It is formed to become. Thereby, the integrity of the main body 51 and each metal bump 71 increases, and the reinforcing effect of the wiring board 2 by these is suitably exhibited.
  • the main body 51 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the main body 51 can effectively reinforce the wiring board 2 and suppress the thermal expansion of the entire semiconductor package 1.
  • the constituent material of the main body 51 is not particularly limited as long as it has a thermal expansion coefficient as described above, and the same constituent material as that of the main body 41 described above can be used.
  • a ceramic material or the like can be used, but in this embodiment, a metal material is used. If the main body 51 is comprised with the metal material, the heat dissipation of the main body 51 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.
  • the main body 51 is comprised with a metal material, the surface is electroconductivity and it has heat conductivity.
  • the metal material is not particularly limited, but it is preferable to use an Fe—Ni-based alloy from the viewpoint of realizing heat dissipation and low thermal expansion.
  • an Fe—Ni-based alloy the same material as the main body 41 described above can be used.
  • the thermal expansion coefficient of the main body 51 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably.
  • the difference in thermal expansion coefficient between the semiconductor element 3 and the main body 51 can be reduced, and the main body 51 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the absolute value of the difference in thermal expansion coefficient between the main body 51 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and further preferably 2 ppm / ° C. or less. .
  • the absolute value of the difference in thermal expansion coefficient between the main body 51 and the main body 41 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and further preferably 0 ppm / ° C.
  • the thermal expansion coefficient difference between the main body 41 and the main body 51 can be reduced, and the warp of the wiring board 2 due to these thermal expansion differences can be prevented.
  • the constituent material of the main body 51 is preferably the same or the same as the constituent material of the main body 41.
  • the average thickness of the main body 51 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, etc. of the wiring board 2, and is not particularly limited. It is about 0.8 mm or less.
  • the adhesive layer 52 is provided on the upper surface of the main body 51, and has substantially the same shape as the main body 51 in a plan view of the main body 51.
  • Such an adhesive layer 52 has the same configuration as the adhesive layer 42 described above, and the same resin composition can be used. That is, the adhesive layer 52 includes the resin material described above and a heat conductive material. And the contact bonding layer 52 is directly contacting the heat conductive surface of the main body 51 comprised with a heat conductive member.
  • the adhesive layer 52 is provided over the entire upper surface of the main body 51.
  • the second reinforcing member is formed with a through hole 5a in which the conductive pattern 224 is exposed and the metal bump 71 connected to the conductive pattern 224 is disposed.
  • the through hole 5 a is configured by the opening 513 described above and the opening 521 formed in the adhesive layer 52.
  • the opening 521 formed in the adhesive layer 52 communicates with the opening 513.
  • the diameter of the opening 513 and the diameter of the opening 521 are equal.
  • the through hole 5a has a diameter larger than that of the metal bump 71, a gap is formed between the inner surface of the through hole 5a and the metal bump 71, and an insulating material 81 is filled between the metal bump 71 and the through hole 5a.
  • the insulating material 81 is filled between the inner surface of the opening 513 and the metal bump 71 and between the inner surface of the opening 521 and the metal bump 71.
  • An insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 (main body 51) and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be improved while improving the reliability of the semiconductor package 1.
  • the insulating material 81 is formed so as to surround the metal bump 71 and is bonded to each metal bump 71. Thereby, the insulating material 81 reinforces the metal bump 71.
  • the insulating material 81 surrounds the base side surface of the metal bump 71 on the conductor pattern 224 side and is in contact with the metal bump 71. Further, the insulating material 81 has a shape that spreads from the side surface side of the metal bump 71 toward the conductor pattern 224 side. Thereby, the metal bump 71 is reinforced by the insulating material 81, and the contact between the metal bump 71 and the main body 51 is prevented by the insulating material 82.
  • Such an insulating material 81 has an insulating property and includes a resin material.
  • Such an insulating material 81 is not particularly limited, but is preferably formed of, for example, a thermosetting resin composition for solder bonding.
  • Such a resin composition for solder joint acts as a flux at the time of solder joining, and then cures by heating to act as a reinforcing material for the solder joint.
  • the solder bonding resin composition removes harmful substances such as the solder bonding surface and the oxide of the solder material at the time of solder bonding, protects the solder bonding surface, and refines the solder material. Enables good bonding with high strength.
  • the resin composition for solder bonding does not need to be removed by washing or the like after the solder bonding, and is heated as it is to become a three-dimensionally crosslinked resin, which acts as a reinforcing material for the solder bonding portion.
  • Such a resin composition for solder bonding can be constituted by including, for example, a resin (A) having a phenolic hydroxyl group and a curing agent (B) of the resin.
  • the resin (A) having a phenolic hydroxyl group is not particularly limited, and examples thereof include a phenol novolac resin, an alkylphenol novolac resin, a polyhydric phenol novolac resin, a resole resin, and a polyvinylphenol resin.
  • the content of the resin (A) is preferably 20 to 80% by weight, and more preferably 25 to 60% by weight of the entire curable flux. If the content of the resin (A) is less than 20% by weight, the effect of removing dirt such as solder and oxides on the metal surface may be reduced, and solder jointability may be deteriorated. When content of resin (A) exceeds 80 weight%, the hardened
  • the phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group effectively removes dirt such as oxide on the solder and metal surface by its reducing action, and thus effectively acts as a solder joint flux.
  • examples of the curing agent (B) of the resin (A) having a phenolic hydroxyl group include an epoxy compound and an isocyanate compound.
  • examples of the epoxy compound and isocyanate compound include phenol-based epoxy compounds such as bisphenol, phenol novolac, alkylphenol novolac, biphenol, naphthol, and resorcinol, isocyanate compounds, saturated aliphatic, cycloaliphatic, Examples thereof include an epoxy compound and an isocyanate compound modified based on a skeleton such as a saturated aliphatic group.
  • the compounding amount of the curing agent (B) is such that the reactive functional group such as epoxy group or isocyanate group of the curing agent is 0.5 to 1.5 equivalent times the phenolic hydroxyl group of the resin (A). It is preferably 0.8 to 1.2 equivalent times. If the reactive functional group of the curing agent is less than 0.5 equivalents of the hydroxyl group, a cured product having sufficient physical properties cannot be obtained, and the reinforcing effect may be reduced, resulting in a decrease in bonding strength and reliability. There is. If the reactive functional group of the curing agent exceeds 1.5 equivalents of the hydroxyl group, the action of removing dirt such as oxide on the solder and metal surface may be reduced, and solder jointability may be deteriorated.
  • Such a solder bonding resin (curable flux) is formed because a cured product having good physical properties is formed by the reaction of the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin. It is not necessary to remove the flux by washing after soldering, the soldered part is protected by the cured product, and electrical insulation is maintained even in a high temperature and high humidity atmosphere, and soldering with high joining strength and reliability is possible. .
  • the solder bonding resin as described above is dispersed in a microcrystalline state as a curable antioxidant (C).
  • the curable flux may include, for example, a thermosetting resin, a flux active compound, and a curing accelerator such as imidazole.
  • Thermosetting resins include epoxy resin, phenoxy resin, silicone resin, oxetane resin, phenol resin, (meth) acrylate resin, polyester resin (unsaturated polyester resin), diallyl phthalate resin, maleimide resin, polyimide resin (polyimide precursor) Resin), bismaleimide-triazine resin, cyanate resin and the like.
  • an epoxy resin from the viewpoints of curability and storage stability and moisture resistance of the cured product.
  • the compound which has a phenolic hydroxyl group and / or a carboxyl group is preferable.
  • Examples of the compound having a phenolic hydroxyl group include phenol, o-cresol, 2,6-xylenol, p-cresol, m-cresol, o-ethylphenol, 2,4-xylenol, 2,5-xylenol, m- Ethylphenol, 2,3-xylenol, meditol, 3,5-xylenol, p-tert-butylphenol, catechol, p-tert-amylphenol, resorcinol, p-octylphenol, p-phenylphenol, bisphenol F, bisphenol AF, biphenol Monomers containing phenolic hydroxyl groups such as diallyl bisphenol F, diallyl bisphenol A, trisphenol, tetrakisphenol, phenol novolac resins, o-cresol novolac resins, bisphenols Nord F novolak resins, resins containing a phenolic hydroxyl group such as bis
  • Examples of the compound having a carboxyl group include an aliphatic acid anhydride, an alicyclic acid anhydride, an aromatic acid anhydride, an aliphatic carboxylic acid, and an aromatic carboxylic acid.
  • Examples of the aliphatic acid anhydride include succinic anhydride, polyadipic acid anhydride, polyazeline acid anhydride, and polysebacic acid anhydride.
  • Examples of the alicyclic acid anhydride include methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylhymic anhydride, hexahydrophthalic anhydride, tetrahydrophthalic anhydride, trialkyltetrahydrophthalic anhydride, methylcyclohexene dicarboxylic acid. An anhydride etc. are mentioned.
  • Examples of the aromatic acid anhydride include phthalic anhydride, trimellitic anhydride, pyromellitic anhydride, benzophenone tetracarboxylic anhydride, ethylene glycol bistrimellitate, and glycerol tris trimellitate.
  • compounds having a carboxyl group and a phenolic hydroxyl group include salicylic acid, 2,3-dihydroxybenzoic acid, 2,4-dihydroxybenzoic acid, gentisic acid (2,5-dihydroxybenzoic acid), 2,6- Benzoic acid derivatives such as dihydroxybenzoic acid, 3,4-dihydroxybenzoic acid, gallic acid (3,4,5-trihydroxybenzoic acid); 1,4-dihydroxy-2-naphthoic acid, 3,5-dihydroxy- Naphthoic acid derivatives such as 2-naphthoic acid; phenolphthaline; diphenolic acid and the like.
  • phenolphthaline, gentisic acid, 2,4-dihydroxybenzoic acid, and 2,6-dihydroxybenzoic acid are preferable, and phenolphthalin and gentisic acid are particularly preferable.
  • both surfaces of the wiring board 2 are reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. Therefore, the rigidity of the entire semiconductor package 1 is increased.
  • the thermal expansion coefficient of the first reinforcing member 4 and the second reinforcing member 5 is smaller than that of the wiring board 2, the semiconductor package 1 is provided in the same manner as the semiconductor element 3 is provided over the entire surface of the wiring board 2. Increases overall rigidity. Therefore, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3.
  • the reinforcement members 4 and 5 are provided, the occurrence of warping of the wiring board 2 can be suppressed, so that the thickness of the wiring board 2 can be reduced. Since the thickness of the wiring board 2 can be reduced, the thermal conductivity in the thickness direction of the wiring board 2 can be increased.
  • the adhesive layers 42 and 52 include a thermally conductive material. Therefore, the heat of the wiring board 2 can be radiated through the first reinforcing member 4 and the second reinforcing member 5. Furthermore, heat from the semiconductor element 3 can be released through the wiring board 2 and the second reinforcing member 5. Therefore, the semiconductor package 1 can exhibit excellent heat dissipation.
  • the first reinforcing member 4 since the first reinforcing member 4 has the insulating adhesive layer 42, the first reinforcing member 4 is wired while preventing the main body 41 and the conductor pattern 221 from being short-circuited. It can be easily bonded to the substrate 2. The same applies to the second reinforcing member 5. Therefore, as will be described later, the manufacture of the semiconductor package 1 is simplified. Furthermore, in this embodiment, the reinforcing members 4 and 5 have heat conductive adhesive layers 42 and 52, and the adhesive layers 42 and 52 are connected to the heat transfer post 24. The heat generated in the semiconductor element 3 can be transferred to the adhesive layer 52 and further to the main body 51 through the adhesive layer 42 and the heat transfer post 24 to be dissipated.
  • the heat of the wiring board 2 can be transferred to the reinforcing members 4 and 5 through the heat transfer posts to be radiated.
  • the insulating material 82 is disposed between the metal bump 91 and the inner surface of the through hole 4a of the first reinforcing member 4, and the metal bump 91 and the main body 41 of the first reinforcing member 4 are in contact with each other. It is suppressed. Although the surface of the main body 41 is conductive, the insulating material 82 can suppress the flow of electricity to the main body 41 of the first reinforcing member 4 through the metal bumps 91, thereby providing a highly reliable semiconductor package. Can do.
  • the insulating material 81 is arrange
  • the surface of the main body 51 is conductive, the insulating material 81 can suppress the flow of electricity to the main body 51 of the second reinforcing member via the metal bumps 71, so that a highly reliable semiconductor package can be obtained. it can.
  • the insulating material 82 (81) is provided so as to surround the metal bump 91 (71), the metal bump 91 (71) can be reinforced by the insulating material 82 (81).
  • the adhesive layer 42 (52) of the reinforcing member 4 (5) covers the solder resist 25 (26). Thereby, the solder resist can be protected by the adhesive layer.
  • the semiconductor package 1 as described above can be manufactured as follows, for example.
  • the manufacturing method of the semiconductor package 1 includes: [1] a step of manufacturing the wiring substrate 2, [2] a step of bonding the first and second reinforcing members 4 and 5 to the wiring substrate 2, and [3] the wiring substrate 2. A step of mounting the semiconductor element 3. Note that the order of the steps [2] and “3” may be reversed. That is, step [2] may be performed after step [3].
  • a laminate for example, a copper-clad laminate in which metal layers 222A and 223A are provided on both surfaces of an insulating layer 212A is prepared.
  • the insulating layer 212A is for forming the insulating layer 212 of the wiring board 2 described above.
  • the metal layer 222A is for forming the conductive pattern 222 of the wiring board 2 described above.
  • the metal layer 223A is for forming the conductor pattern 223 of the wiring board 2 described above.
  • through holes via holes, through holes
  • the insulating layer 212 is obtained.
  • the method for forming the through hole is not particularly limited, but for example, it can be formed by irradiating a laser.
  • conductor posts 232 are formed in predetermined through holes. Further, a heat transfer post portion 242 is formed in a predetermined through hole.
  • the method for forming the conductor post 232 and the heat transfer post portion 242 is not particularly limited. For example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, or the like can be used. . In particular, when the conductor post 232 and the heat transfer post portion 242 are each formed in a hollow shape, electrolytic plating is preferably used.
  • the metal layers 222A and 223A are selectively removed and patterned to form conductor patterns 222 and 223, respectively.
  • the patterning method is not particularly limited, but etching is preferably used.
  • the insulating layer 212, the conductor patterns 222 and 223, the conductor post 232, and the heat transfer post portion 242 are formed.
  • a stacked body including the insulating layer 211 ⁇ / b> A and the metal layer 221 ⁇ / b> A is pasted on the conductor pattern 222.
  • the laminated body is attached so that the insulating layer 211 ⁇ / b> A is in contact with the conductor pattern 222.
  • a laminated body including an insulating layer 213A and a metal layer 224A is attached onto the conductor pattern 223.
  • the stacked body is attached so that the insulating layer 213A is in contact with the conductor pattern 223.
  • the insulating layer 211A is, for example, a prepreg for forming the insulating layer 211 of the wiring substrate 2 described above, and an uncured product (semi-cured product) of the resin composition of the insulating layer 211 described above. ) Is impregnated into the base material.
  • the insulating layer 213A is, for example, a prepreg for forming the insulating layer 213 of the wiring board 2 described above, and an uncured product (semi-cured material) of the resin composition of the insulating layer 213 described above. ) Is impregnated into the base material.
  • a through hole (via hole) H is formed in the laminated body composed of the insulating layer 211A and the metal layer 224A. Thereby, the insulating layer 211 is obtained.
  • a through hole (via hole) H is formed in a stacked body including the insulating layer 213A and the metal layer 224A. Thereby, the insulating layer 213 is obtained.
  • the method for forming the through hole H is not particularly limited, but the same method as in the above-described step [1-B] can be used.
  • the conductor posts 231 and 233 are formed in the through hole H as shown in FIG.
  • heat transfer post portions 241 and 243 are formed in the through holes H.
  • the method for forming the conductor posts 231 and 233 and the heat transfer post portions 241 and 243 is not particularly limited. For example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, etc. Can be used.
  • the conductive layers 221 and 224 are formed by patterning the metal layers 221A and 224A, respectively.
  • the patterning method the same method as in the above-mentioned step [1-D] can be used.
  • solder resists 25 and 26 having openings are formed.
  • the solder resists 25 and 26 are not particularly limited, but can be formed by, for example, applying a resist material, exposing and developing, and selectively removing the resist material.
  • the conductor pattern 221 is exposed from the opening of the solder resist 25, and the conductor pattern 224 is exposed from the opening of the solder resist 26.
  • the wiring board 2 is obtained.
  • a first reinforcing member 4 and a second reinforcing member 5 are prepared.
  • the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be manufactured as follows, for example, and can be prepared beforehand.
  • the manufacturing method of the 1st, 2nd reinforcement member 4 and 5 is mutually the same, below, the manufacturing method of the 1st reinforcement member 4 is demonstrated as a representative, and the manufacturing method of the 2nd reinforcement member 5 is demonstrated below. The description is omitted.
  • a base material (plate member) 4A having a plate-like main body 41A and an adhesive layer 42A formed on one surface (upper surface in FIG. 7) of the main body 41A is prepared.
  • a substrate (plate member) 5A having a plate-like main body 51A and an adhesive layer 52A formed on one surface of the main body 51A may be prepared.
  • the other steps are the same as the manufacturing steps of the first reinforcing member 4).
  • the main body 41A is for forming the main body 41 of the first reinforcing member 4 described above, and is made of, for example, a metal material.
  • the adhesive layer 42A is for forming the adhesive layer 42 of the first reinforcing member 4, and is composed of the above-described resin composition containing a resin material and an inorganic filler, for example.
  • a protective sheet is provided on the upper surface (the lower surface when viewed in FIG. 7A) of the adhesive layer 42A to prevent a decrease in adhesive force due to drying of the adhesive layer 42A or adhesion of dust. May be provided.
  • As a method of providing the adhesive layer 42A on one surface of the main body 41A for example, there is a method of applying and drying a varnish to be the adhesive layer 42A on one surface of the main body 41A. A method of attaching the film-like adhesive layer 42A onto the main body 41A may be employed.
  • the base material 4A is processed into a desired shape. Specifically, the through holes 4a and 4b are formed in the base material 4A. Thereby, as shown in FIG.6 (b), the 1st reinforcement member 4 is obtained.
  • the method of processing the substrate 4A into a desired shape is not particularly limited, and examples thereof include various etching processes such as punching, dry etching, and wet etching, and laser irradiation. Processing or the like can be used.
  • the laser for example, a CO 2 laser, a UV-YAG laser, or the like can be used. Among these methods, etching or laser irradiation processing is preferable in that finer processing can be performed.
  • the first and second reinforcing members 4 and 5 manufactured in the step [2-A] are prepared.
  • the first reinforcing member 4 is attached to the adhesive layer. 42 is attached to the solder resist 25 on the upper surface of the wiring board 2 with the wiring board 2 side
  • the second reinforcing member 5 is attached to the solder resist 26 on the lower surface of the wiring board 2 with the adhesive layer 52 side. wear.
  • the first and second reinforcing members 4 and 5 can be attached by, for example, vacuum pressing, laminating, or the like.
  • the 1st reinforcement member 4 is affixed so that the some opening part formed in the soldering resist 25 and the through-holes 4a and 4b formed in the reinforcement member 4 may each communicate.
  • the 2nd reinforcement member 5 is affixed so that the some opening part formed in the soldering resist 26 and the through-hole 5a formed in the reinforcement member 5 may each communicate.
  • the semiconductor element 3 is made to be a metal bump. It joins by solder reflow via 31.
  • a resin having flux activity similar to that of the insulating material 81 described above is used as the underfill material.
  • a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured.
  • a metal ball (solder ball) 71A is soldered by solder reflow.
  • an insulating material 81A is applied on the conductor pattern 224 exposed from each through hole 5a.
  • the metal bump 71 is disposed on the insulating material 81A.
  • the insulating material 81A is crushed by the metal bump 71, spreads on the second conductor pattern, and surrounds the periphery of the metal bump 71.
  • the metal bump 71 is heated, for example, at 200 to 280 ° C. for 10 to 60 seconds to solder-bond the metal bump 71 and the second conductor pattern (see FIG. 7C).
  • the insulating material 81A is for forming the insulating material 81 described above, and is cured by heating, for example.
  • the insulating material 81A is applied to the lower surface of the wiring board 2, and after the solder bonding described above, the insulating material 81A is cured by heating to obtain the insulating material 81.
  • the insulating material 81 obtained in this way is formed so as to surround the metal bump 71 as described above.
  • the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by the interfacial tension with the metal bump 71A.
  • a metal ball (solder ball) 91A is soldered by solder reflow.
  • an insulating material 82A is applied on the conductor pattern 221 exposed from each through hole 4a.
  • the metal bump 91 is disposed on the insulating material 82A.
  • the insulating material 82 ⁇ / b> A is crushed by the metal bump 91 and spreads on the conductor pattern 221 and surrounds the periphery of the metal bump 91.
  • the metal bump 91 is heated, for example, at 200 to 280 ° C.
  • the insulating material 82A is for forming the insulating material 82 described above, and is cured by heating, for example.
  • the insulating material 82A is applied to the lower surface of the wiring board 2, and after the solder bonding described above, the insulating material 82A is cured by heating to obtain the insulating material 82.
  • the insulating material 82 thus obtained is formed so as to surround the periphery of the metal bump 91 as described above.
  • the insulating material 82A functions as a flux at the time of solder bonding, and is cured in a shape that reinforces the periphery of the solder bonding portion in a ring shape by interfacial tension with the metal bump 91A.
  • the semiconductor package 1 is obtained as described above.
  • the reinforcing member 4 (5) in which the through holes 4a, 4b (5a) are formed in advance is attached to the wiring board 2. After being attached to the wiring board 2, the process of forming the through hole in the reinforcing member is not performed, so that the wiring board can be prevented from being damaged when the reinforcing member 4 (5) is processed.
  • FIG. 8 is a cross-sectional view schematically showing a semiconductor device including the semiconductor package shown in FIG.
  • the semiconductor device 100 includes a mother board (substrate) 200, a bottom package 300 that is the semiconductor package 1 mounted on the motherboard 200, and a top that is another semiconductor package mounted on the bottom package 300.
  • Package 400 is another semiconductor package mounted on the bottom package 300.
  • the metal bumps 71 of the semiconductor package 1 are joined to the terminals (not shown) of the mother board 200, and the metal bumps 91 of the semiconductor package 1 are connected to the terminals (not shown) of the top package 400. ).
  • the semiconductor package 1, the top package 400, and the mother board 200 are electrically connected to each other, and electrical signals are transmitted among them.
  • the semiconductor package 1 having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.
  • the top package 400 may be omitted as necessary.
  • FIG. 9 is a cross-sectional view schematically showing a semiconductor package according to the second embodiment of the present invention.
  • the upper side in FIG. 9 is referred to as “upper” and the lower side is referred to as “lower”.
  • the semiconductor package of the second embodiment is the same as that of the first embodiment described above except that the adhesive layers of the first and second reinforcing members also serve as solder resists and do not have the solder resists 25 and 26.
  • the wiring board 2A of the semiconductor package 1A has a configuration in which the solder resists 25 and 26 are omitted from the wiring board 2 of the first embodiment.
  • the adhesive layer 42 of the first reinforcing member 4 is bonded to the upper surface of the insulating layer 211 included in the wiring board 2A, and the adhesive layer 42 and the conductor pattern 221 are in contact with each other.
  • the adhesive layer 52 of the second reinforcing member 5 is bonded to the lower surface of the insulating layer 213, and the adhesive layer 52 and the conductor pattern 224 are in contact with each other.
  • These adhesive layers 42 and 52 also function as a solder resist for protecting the wiring board 2.
  • the adhesive layer 42 is not formed on the upper surface of the wiring board 2 where it does not overlap the first reinforcing member 4, that is, inside the first reinforcing member 4 and in the region where the semiconductor element 3 is mounted. .
  • an adhesive layer 32 is formed in such a region, and this adhesive layer 32 also serves as a solder resist.
  • the adhesive layer 42 is not formed in the lower surface of the wiring board 2 where it does not overlap with the second reinforcing member 5, that is, inside the second reinforcing member and in the region where the metal bumps 71 are joined.
  • an insulating material 81 is applied to such a region, and this insulating material 81 also serves as a solder resist.
  • FIG. 10 is a cross-sectional view of the first and second reinforcing members according to the third embodiment of the present invention
  • FIG. 11 is a cross-sectional view of a semiconductor package manufactured using the first and second reinforcing members shown in FIG. It is.
  • the upper side in FIGS. 10 and 11 is referred to as “upper” and the lower side is referred to as “lower”.
  • the semiconductor package 1B of the third embodiment is the same as that of the first embodiment described above except that the configurations of the first and second reinforcing members are different.
  • the shape of the wiring board 2 is simplified.
  • the first reinforcing member 4 ⁇ / b> B of the present embodiment includes a plate-like main body 41, an adhesive layer 42 provided on the lower surface of the main body 41, and a protrusion 43 ⁇ / b> B.
  • the main body 41 and the adhesive layer 42 have the same structure and shape as those of the above embodiment, and the through holes 4a and 4b are formed. However, the illustration is simplified here.
  • the protrusion 43B protrudes from the main body 41 and penetrates the adhesive layer 42.
  • the protrusion 43B is formed at a position where it is connected (contacted) with the heat transfer post 24 when the first reinforcing member 4B is joined to the upper surface of the wiring board 2.
  • the second reinforcing member 5B has a plate-like main body 51, an adhesive layer 52 provided on the upper surface of the main body 51, and a protrusion 53B.
  • the main body 51 and the adhesive layer 52 have the same structure and shape as those of the above embodiment, and the through hole 5a is formed. However, the illustration is simplified here.
  • the protrusion 53 ⁇ / b> B protrudes from the main body 51 and penetrates the adhesive layer 52.
  • the protrusion 53B is formed at a position where the second reinforcing member 5B is connected to the heat transfer post 24 when the second reinforcing member 5B is joined to the lower surface of the wiring board 2.
  • the constituent material of the projections 43B and 53B is not particularly limited, but from the viewpoint of excellent thermal conductivity and the bonding property with the heat transfer post 24 as described later, the metal is the same as the main bodies 41 and 51. It is preferable that it is made of a material. Further, the protrusions 43B and 53B may be formed integrally with the main bodies 41 and 51, or may be formed as separate bodies. In the present embodiment, the protrusions 43B and 53B are formed separately from the main bodies 41 and 51 by plating.
  • FIG. 4 when the first reinforcing member 4B is attached to the upper surface of the wiring board 2 and the second reinforcing member 5B is attached to the lower surface of the wiring board 2, and these are pressed against the wiring board 2 by a vacuum press or the like, FIG. As shown in FIG. 4, the protrusions 43B and 53B are deformed and pressed against the heat transfer post 24 by the pressing force. As a result, the heat of the wiring board 2 can be more efficiently transmitted to the main bodies 41 and 51 via the protrusions 43B and 53B, so that the semiconductor package 1B is more excellent in heat dissipation.
  • the wiring board 2 and the first and second reinforcing members 4B and 5B can be joined by the pressure of the protrusions 43B53B in addition to the adhesive strength of the adhesive layers 42 and 52, the semiconductor package 1B having higher mechanical strength. It becomes.
  • the adhesive layers 42 and 52 indirectly contact the heat transfer post 24 via the protrusions 43B and 53B and the main bodies 41 and 51.
  • a solder paste may be printed on the surface of the heat transfer post 24 in advance, and the protrusions 43B and 45B may be positioned, pressurized and heated to alloy the solder and the protrusions 43B and 45B.
  • the first and second reinforcing members 4B and 5B may be joined to the wiring board 2 separately. That is, one of the first and second reinforcing members 4B and 5B may be bonded to the wiring board 2 first, and then the other may be bonded.
  • the adhesive layer 42 may be in direct contact with the heat transfer post together with the protrusion 43B.
  • the adhesive layer 52 may be in direct contact with the heat transfer post together with the protrusion 45B.
  • FIG. 12 is a cross-sectional view of a semiconductor package according to the fourth embodiment of the present invention.
  • the upper side in FIG. 12 is referred to as “upper” and the lower side is referred to as “lower”.
  • the semiconductor package of the fourth embodiment is the same as that of the first embodiment described above except that alignment marks are formed on the first and second reinforcing members. Since the first reinforcing member and the second reinforcing member have the same configuration, the first reinforcing member will be representatively described below, and the description of the second reinforcing member will be omitted.
  • an alignment mark 44C is formed at a predetermined position on the upper surface of the main body 41 of the first reinforcing member 4C.
  • the number of alignment marks 44C may be one, but it is preferable that two or more alignment marks 44C are formed at different positions such as at least two of the four corners. Thereby, positioning of the 1st reinforcement member 4C with respect to the wiring board 2 can be performed more accurately.
  • Such an alignment mark 44 ⁇ / b> C can be constituted by, for example, a convex portion formed by applying plating or the like on the upper surface of the main body 41. According to such 1st reinforcement member 4C, positioning with the wiring board 2 can be performed easily and joining to the wiring board 2 can be performed more simply and with high precision.
  • the joining of the first reinforcing member 4C to the wiring board 2 is performed as follows, for example. First, the wiring board 2 is fixed to a stage or the like, and the first reinforcing member 4C is fixed to a movable stage that can move with respect to the stage. Next, while detecting each alignment mark 44C of the first reinforcing member 4C by an imaging means such as a CCD camera, the moving stage is moved so that each alignment mark 44C is at a predetermined position. Then, after the movement of the first reinforcing member 4C is completed so that each alignment mark 44C is in a predetermined position, the moving stage is moved to the stage side, and the first reinforcing member 4C is bonded to the wiring board 2.
  • an alignment mark 54C is formed at a predetermined position on the lower surface of the main body 51 of the second reinforcing member 5C.
  • the alignment mark 54C may be one, but it is preferable that two or more alignment marks 54C are formed at different positions such as at least two of the four corners. Thereby, positioning of the 2nd reinforcement member 5C with respect to the wiring board 2 can be performed more accurately.
  • Such an alignment mark 54 ⁇ / b> C can be constituted by, for example, a convex portion formed by applying plating or the like on the lower surface of the main body 51.
  • the second reinforcing member 5C can be joined to the wiring board 2 in the same manner as the first reinforcing member 4C.
  • the reinforcing members 4C and 5C can be joined to the wiring board 2 with high accuracy, a highly reliable semiconductor package can be obtained.
  • the second reinforcing member 5C has a portion 512 formed so as to surround the periphery of the metal bump 71, if the second reinforcing member 5 can be accurately joined to the wiring board 2, the portion 512 can be obtained. And the metal bump 71 can be prevented more reliably. Thereby, the arrangement
  • the semiconductor package 1 can be downsized.
  • alignment marks may also be formed on the wiring board 2.
  • an alignment mark corresponding to the alignment mark 44C of the first reinforcing member 4 can be formed using the layer forming the conductor pattern 221, and the layer forming the conductor pattern 224 can be used.
  • An alignment mark corresponding to the alignment mark 54C of the second reinforcing member 5 can be formed. Then, the first reinforcing member 4C and the wiring board 2 are placed in a predetermined positional relationship while detecting the alignment mark of the first reinforcing member 4C and the alignment mark of the wiring board 2 using a CCD camera or the like. By relatively moving the first reinforcing member 4C relative to the wiring board 2, the first reinforcing member 4C can be positioned.
  • the present embodiment will be described with reference to FIGS.
  • the wiring board 2A of the semiconductor package 1D of this embodiment does not have the solder resists 25 and 26.
  • Other points are the same as in the first embodiment.
  • the shapes of the adhesive layers 42D and 52D of the reinforcing members 4D and 5D of the present embodiment are different from those of the first embodiment.
  • the semiconductor package manufacturing method of the present embodiment is different from the above-described embodiments. About another point, it is the same as that of 1st embodiment. This will be described in detail below. As shown in FIG.
  • the semiconductor package 1D of this embodiment does not have the solder resists 25 and 26, and the adhesive layers 42D and 52D of the reinforcing members 4D and 5D function as the solder resist.
  • the first reinforcing member 4 ⁇ / b> D includes a main body 41 similar to that of the first embodiment and an adhesive layer 42 ⁇ / b> D provided on one surface of the main body 41.
  • An opening 420 communicating with the opening 411 of the main body 41 is formed in the adhesive layer 42 ⁇ / b> D, and the through hole 4 a is formed together with the opening 411 of the main body 41.
  • the adhesive layer 42 ⁇ / b> D is formed with a plurality of openings 423 that communicate with the openings 412 of the main body 41.
  • the opening 423 penetrates the adhesive layer 42 ⁇ / b> D and is provided at a location corresponding to the metal bump 31. That is, a plurality of openings 423 are scattered inside the opening 412 of the main body 41, and the opening 423 of the adhesive layer 42 ⁇ / b> D is exposed from the opening 412 of the main body 41.
  • the diameter of the opening 412 is larger than that of the opening 423, and the periphery of the opening 423 is located inside the opening 412 in a plan view from one surface side of the wiring board.
  • the plurality of openings 412 and the openings 423 form a plurality of through holes 4b. By positioning the periphery of the opening 423 inside the opening 412, the main body 41 can be prevented from coming into contact with the solder bump.
  • the adhesive layer 42D is the same as the adhesive layer 42 of the first embodiment.
  • the second reinforcing member 5 ⁇ / b> D includes a main body 51 similar to that of the first embodiment, and an adhesive layer 52 ⁇ / b> D provided on one surface of the main body 51.
  • An opening 521 communicating with the opening 513 of the main body 51 is formed in the adhesive layer 52 ⁇ / b> D, and the through hole 5 a is formed together with the opening 513 of the main body 51.
  • the diameter of the opening 521 formed in the adhesive layer 52D is smaller than the diameter of the opening 513 of the main body 51, and the peripheral edge of the opening 521 of the adhesive layer 52 is exposed from the opening 513 of the main body 51. Become. Since the periphery of the opening 521 is located inside the opening 513, the main body 51 can be prevented from coming into contact with the solder bump.
  • the adhesive layer 52D is the same as the adhesive layer 52 of the first embodiment.
  • the wiring board 2A is manufactured.
  • the manufacturing process of the wiring board 2A is the same as the processes of FIGS. 4, 5A, and 5B of the first embodiment.
  • the process of FIG. 5C is not performed. Next, the following steps are performed.
  • the first plate member 4A shown in FIG. 15A is a member that becomes the first reinforcing member 4D.
  • a plate-like main body 41A made of a metal material is prepared by the same method as in the first embodiment, and then the upper surface (one surface) of the main body 41A is prepared. Then, the same adhesive layer 42A as in the above embodiment is formed.
  • the adhesive layer 42A is a thermally conductive adhesive layer including a thermally conductive inorganic filler and a resin material. Thereby, the first plate member 4A is obtained.
  • the method for forming the adhesive layer 42A is not particularly limited.
  • the adhesive layer 42A can be formed by laminating an adhesive sheet material on the upper surface of the main body 41A, and the adhesive can be formed by various printing methods such as screen printing. It can be formed by coating.
  • a protective sheet release sheet is preferably laminated on the surface of the adhesive layer 42A.
  • the second plate member 5A is a member that becomes the second reinforcing member 5D.
  • the adhesive layer 52A is a thermally conductive adhesive layer including a thermally conductive inorganic filler and a resin material.
  • the method for forming the adhesive layer 52A is not particularly limited.
  • the adhesive layer 52A can be formed by laminating an adhesive sheet material on the upper surface of the main body 51A, and the adhesive can be formed by various printing methods such as screen printing. It can be formed by coating. In order to suppress a decrease in adhesiveness of the adhesive layer 52A, it is preferable to laminate a protective sheet (release sheet) on the surface of the adhesive layer 52A.
  • first plate member 4A and the second plate member 5A can have the same configuration, and in this case, it is not necessary to distinguish between the first plate member 4A and the second plate member 5A. That is, two first plate members 4A may be manufactured and one of them may be used as the second plate member 5A. Conversely, two second plate members 5A may be manufactured and one of them may be the first. It may be used as the plate member 4A.
  • the first plate member 4A is attached (bonded) to the upper surface of the wiring board 2 with the adhesive layer 42A on the wiring board 2A side, and the second step.
  • the plate member 5A is attached (bonded) to the lower surface of the wiring board 2A with the adhesive layer 52A facing the wiring board 2 side.
  • the first and second plate members 4A and 5A can be attached to the wiring board 2 by, for example, vacuum pressing, laminating, or the like.
  • the first and second plate members 4A and 5A may be attached to the wiring board 2A at the same time, or after one of the first and second plate members 4A and 5A is attached to the wiring board 2A. Although the other may be affixed, it is preferable to carry out at the same time. Thereby, the manufacturing process of the semiconductor package 1 can be reduced.
  • the conductor pattern 221 directly contacts the adhesive layer 42A and bites into the adhesive layer 42A
  • the conductor pattern 224 directly contacts the adhesive layer 52A and bites into the adhesive layer 52A. Thereby, the conductor patterns 221 and 224 are protected by the adhesive layer as the solder resist.
  • the main body 41A of the first plate member 4A is processed into a desired shape (planar shape), and the main body 51A of the second plate member 5A is processed.
  • Process into desired shape Specifically, openings 411 and 412 that penetrate the main body 41A and an opening 513 that penetrates the main body 51A are formed.
  • the processing method is not particularly limited, and examples thereof include various etching methods such as wet etching and dry etching, and a method of irradiating a laser, but wet etching is preferably used. Thereby, highly accurate processing can be performed on the main bodies 41A and 51A.
  • the processing of the main bodies 41A and 51A may be performed simultaneously (within the same process), or the processing of the other may be performed after processing of one of the processing.
  • openings 420 and 423 for exposing the conductor pattern 221 are formed at predetermined positions of the adhesive layer 42A of the first plate member 4A, and the conductor pattern 224 is formed at predetermined positions of the adhesive layer 52A of the second plate member 5A.
  • An opening 521 for exposing is formed.
  • a method for forming the opening is not particularly limited, and examples thereof include a method of irradiating a laser through the removed portions of the main bodies 41A and 51A. As a result, it is possible to easily form a fine, narrow and narrow pitch opening with high accuracy.
  • the laser for example, a CO 2 laser, a UV-YAG laser, or the like can be used.
  • the openings in the main body 41A and the main body 51A it is preferable to perform wet etching when forming the openings in the main body 41A and the main body 51A, and use a laser when forming the openings in the adhesive layers 42A and 52A.
  • the opening portions 411 and 412 can be easily formed in the metal main bodies 41A and 51A without etching and removing the adhesive layers 42A and 52A. 513 can be formed.
  • an opening having a relatively small diameter can be formed in the adhesive layers 42A and 52A by using a laser.
  • the first reinforcing member 4D and the second reinforcing member 5D provided on both surfaces of the wiring board 2 are obtained.
  • the metal balls (solder balls) 71A are soldered by solder reflow.
  • the metal ball is disposed inside the opening 521 and the opening 513.
  • the second reinforcing member 5 functions as a ball mounting mask, so that it is not necessary to prepare a mask, and the manufacturing cost can be reduced.
  • the metal bump 71 and the insulating material 81 are formed by curing the insulating material 81A by heating.
  • solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2A and heating in that state, for example, 200 to 280 ° C. ⁇ 10 to 60 seconds. .
  • the insulating material 81 is formed so as to surround the periphery of the metal bump 71. At this time, the insulating material 81 functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by interfacial tension with the metal bump 71A.
  • the insulating material 81 is filled between the opening 513 and the metal bump 71, but may be filled between the opening 521 and the metal bump 71.
  • the shape of the insulating material 81 is the same as that of the above embodiment.
  • an insulating material 82A is applied to the upper surface of the wiring board 2A, that is, the through hole 4a of the first reinforcing member 4 in the same manner as in the first embodiment, and then a metal ball (solder ball) 91A is soldered. Solder bonding to the wiring board 2A is performed by reflow.
  • the metal ball is disposed inside the opening 411 and the opening 420. Thereby, as shown in FIG.7 (d), the metal bump 91 and the insulating material 82 are formed. Such solder bonding can be performed in the same manner as the metal bump 71 described above.
  • the insulating material 82 is filled between the opening portion 411 and the metal bump 71 and between the opening portion 420 and the metal bump 71.
  • the shape of the insulating material 82 is the same as that in the above embodiment.
  • the semiconductor package 1 is obtained as described above.
  • the adhesive layers 42A and 52A are formed on the first and second plate members 4A and 5A, the bonding to the wiring board 2A can be easily performed. . Therefore, the semiconductor package 1 in which warpage is suppressed can be easily manufactured. Further, since the adhesive layers 42D and 52D also serve as a solder resist, a step of separately forming the solder resist can be omitted. Therefore, the manufacturing process of the semiconductor package 1 can be reduced.
  • an opening is formed in the main body 41A (51A), and the opening is formed in the adhesive layer 42A (52A). Is forming.
  • each opening part can be formed in a desired position according to the conductor pattern of 2 A of wiring boards.
  • a reinforcing member is created in advance and attached to the wiring board 2A, it is necessary to accurately align the wiring board and the reinforcing member.
  • a plate member is attached to the wiring board 2A. After the attachment, the reinforcing member is processed to produce a reinforcing member, so that it is not necessary to align the conductor pattern of the wiring board 2 and the plate member.
  • the diameter of the opening 423 of the adhesive layer 42 ⁇ / b> D is smaller than the opening 412 of the main body 41.
  • the solder bump 31 is disposed in the opening 423.
  • the solder bump 31 Since the diameter of the opening 423 is smaller than that of the opening 412, the solder bump 31 is smaller than the case where the diameter of the opening 423 is the same as that of the opening 412. It becomes easy to position by the opening part 423, and the solder bump 31 can be arrange
  • FIG. 17 is a cross-sectional view schematically showing a semiconductor device including the semiconductor package shown in FIG.
  • the semiconductor device 100 includes a mother board (substrate) 200, a bottom package 300 that is a semiconductor package 1D mounted on the mother board 200, and a top that is another semiconductor package mounted on the bottom package 300.
  • Package 40 the semiconductor device 100 includes a mother board (substrate) 200, a bottom package 300 that is a semiconductor package 1D mounted on the mother board 200, and a top that is another semiconductor package mounted on the bottom package 300.
  • Package 40 is a mother board (substrate) 200, a bottom package 300 that is a semiconductor package 1D mounted on the mother board 200, and a top that is another semiconductor package mounted on the bottom package 300.
  • the metal bumps 71 of the semiconductor package 1D are joined to the terminals (not shown) of the mother board 200, and the metal bumps 91 of the semiconductor package 1D are connected to the terminals (not shown) of the top package 400. ).
  • the semiconductor package 1D, the top package 400, and the mother board 200 are electrically connected, and electrical signals are transmitted between them.
  • the semiconductor package 1D having excellent heat dissipation and reliability as described above since the semiconductor package 1D having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.
  • the top package 400 may be omitted as necessary.
  • a projection 43 (53) may be provided on the main body 41 (51), as in the third embodiment.
  • the protrusion 43 (53) is a thermally conductive member that penetrates the adhesive layers 42D and 52D.
  • an alignment mark may be formed on the main body 41 (51).
  • a semiconductor package 1E of this embodiment shown in FIG. 19 has a structure in which solder resists 25 and 26 are provided in the semiconductor package of the fifth embodiment.
  • the reinforcing member 4 ⁇ / b> D is the same as that of the fifth embodiment, the adhesive layer 42 ⁇ / b> D is formed so as to cover the solder resist 25. Thereby, the durability of the solder resist 25 is improved, and the conductor pattern 221 can be protected for a longer period. As a result, the reliability of the semiconductor package 1 is improved.
  • a plurality of openings 423 are formed in such an adhesive layer 42D.
  • the plurality of openings 423 are provided corresponding to the openings formed in the solder resist 25, and predetermined portions (connection electrode portions) of the conductor pattern 221 are exposed from the openings 423. Since the conductor pattern 221 is exposed from the opening of the solder resist 25, the conductor pattern 221 is also exposed from the opening 423 of the adhesive layer 42.
  • the opening 423 of the adhesive layer 42D is located inside the opening of the solder resist.
  • the adhesive layer 42 ⁇ / b> D integrally covers the surface of the solder resist 25 opposite to the conductor pattern 221 and the inner surface of the opening of the solder resist 25.
  • Solder bumps are disposed inside the opening 423 of the adhesive layer 42 ⁇ / b> D and inside the opening 412 of the main body 41, and the solder bump 31 is connected to the conductor pattern 221. Other points are the same as those of the reinforcing member 4D of the fifth embodiment.
  • the semiconductor package 1E has the same reinforcing member 5D as in the fifth embodiment.
  • the adhesive layer 52D is provided on the upper surface of the main body 51, and a plurality of openings 521 are formed at predetermined positions. Each opening 521 is provided corresponding to the opening 513 of the main body 51. Each opening 521 is provided concentrically with the opening 513 and has a substantially circular shape having a smaller diameter than the opening 513.
  • the adhesive layer 52 is formed so as to cover the solder resist 26.
  • the connection electrode portions of the conductor pattern 224 are exposed from the openings 521, and the metal bumps 71 are bonded to the portions. That is, solder bumps 71 are arranged inside the opening of the adhesive layer 52D and inside the opening of the main body, and the solder bump 71 is connected to the conductor pattern 224. Since the conductor pattern 224 is exposed from the opening of the solder resist 26, the conductor pattern 224 is also exposed from the opening 521 of the adhesive layer 52D.
  • the opening 521 of the adhesive layer 52 ⁇ / b> D is located inside the opening of the solder resist 26.
  • the adhesive layer 52 ⁇ / b> D integrally covers the surface of the solder resist 26 opposite to the conductor pattern 224 and the inner surface of the opening of the solder resist 26.
  • the semiconductor package of this embodiment is the same as the semiconductor package of the fifth embodiment.
  • the manufacturing method of the semiconductor package of this embodiment is demonstrated.
  • the wiring board 2 is manufactured as in the first embodiment.
  • the manufacturing process of the wiring board 2 is the same as the process of FIG. 4, FIG. 5 (a), (b) (c) of 1st embodiment.
  • the following steps are performed.
  • the first plate member 4A is a member that becomes the first reinforcing member 4D.
  • a plate-like main body 41A made of a metal material is prepared, and then an adhesive layer 42A similar to that of the above embodiment is formed on the upper surface (one surface) of the main body 41A.
  • the adhesive layer 42A is a thermally conductive adhesive layer including a thermally conductive inorganic filler and a resin material.
  • the method for forming the adhesive layer 42A is not particularly limited.
  • the adhesive layer 42A can be formed by laminating an adhesive sheet material on the upper surface of the main body 41A, and the adhesive can be formed by various printing methods such as screen printing. It can be formed by coating.
  • a protective sheet release sheet is preferably laminated on the surface of the adhesive layer 42A.
  • the second plate member 5A is a member that becomes the second reinforcing member 5D.
  • the adhesive layer 52A is a thermally conductive adhesive layer including a thermally conductive inorganic filler and a resin material.
  • the method for forming the adhesive layer 52A is not particularly limited.
  • the adhesive layer 52A can be formed by laminating an adhesive sheet material on the upper surface of the main body 51A, and the adhesive can be formed by various printing methods such as screen printing. It can be formed by coating. In order to suppress a decrease in adhesiveness of the adhesive layer 52A, it is preferable to laminate a protective sheet (release sheet) on the surface of the adhesive layer 52A.
  • first plate member 4A and the second plate member 5A can have the same configuration, and in this case, it is not necessary to distinguish between the first plate member 4A and the second plate member 5A. That is, two first plate members 4A may be manufactured and one of them may be used as the second plate member 5A. Conversely, two second plate members 5A may be manufactured and one of them may be the first. It may be used as the plate member 4A.
  • the first plate member 4A is attached (bonded) to the upper surface of the wiring board 2 with the adhesive layer 42A on the wiring board 2 side, and the second step.
  • the plate member 5A is attached (bonded) to the lower surface of the wiring board 2 with the adhesive layer 52A facing the wiring board 2 side.
  • the first and second plate members 4A and 5A can be attached to the wiring board 2 by, for example, vacuum pressing, laminating, or the like.
  • the solder resist 25 bites into the adhesive layer 42A, and the surface of the solder resist 25 is covered with the adhesive layer 42A.
  • the adhesive layer 42 ⁇ / b> A is filled in the opening of the solder resist 25.
  • the solder resist 26 bites into the adhesive layer 52A, and the surface of the solder resist 26 is covered with the adhesive layer 52A.
  • the adhesive layer 52 ⁇ / b> A is filled in the opening of the solder resist 26.
  • the first and second plate members 4A and 5A may be attached to the wiring board 2 at the same time, or after one of the first and second plate members 4A and 5A is attached to the wiring board 2. Although the other may be affixed, it is preferable to carry out at the same time. Thereby, the manufacturing process of the semiconductor package 1 can be reduced.
  • the main body 41A of the first plate member 4A is processed into a desired shape (planar shape), and the main body 51A of the second plate member 5A is processed. Processing into a desired shape (forms an opening that penetrates the main body 51A).
  • the processing method is not particularly limited, and examples thereof include various etching methods such as wet etching and dry etching, and a method of irradiating a laser, but wet etching is preferably used. Thereby, highly accurate processing can be performed on the main bodies 41A and 51A.
  • the processing of the main bodies 41A and 51A may be performed simultaneously (within the same process), or the processing of the other may be performed after processing of one of the processing.
  • an opening for exposing the conductive pattern 221 is formed at a predetermined position of the adhesive layer 42A of the first plate member 4A, and the conductive pattern 224 is exposed at a predetermined position of the adhesive layer 52A of the second plate member 5A.
  • the opening is formed.
  • a method for forming the opening is not particularly limited, and examples thereof include a method of irradiating a laser through the removed portions of the main bodies 41A and 51A. As a result, it is possible to easily form a fine, narrow and narrow pitch opening with high accuracy.
  • the laser for example, a CO 2 laser, a UV-YAG laser, or the like can be used.
  • the adhesive layer 42 ⁇ / b> A filled inside the opening of the solder resist 25 is selectively removed, and the opening 423 of the adhesive layer 42 is formed inside the opening of the solder resist 25.
  • the adhesive layer 42A is selectively removed so that the adhesive layer 42A filled inside the opening of the solder resist 25 remains in a film shape along the inner surface (side surface) of the opening of the solder resist 25.
  • the adhesive layer 52 ⁇ / b> A filled inside the opening of the solder resist 26 is selectively removed, and the opening 521 of the adhesive layer 52 is formed inside the opening of the solder resist 26.
  • the adhesive layer 52A is selectively removed so that the adhesive layer 52A filled inside the opening of the solder resist 26 remains in a film shape along the inner surface (side surface) of the opening of the solder resist 26.
  • the metal balls (solder balls) 71A are soldered by solder reflow.
  • the metal ball is disposed inside the opening 521 and the opening 513.
  • the second reinforcing member 5 functions as a ball mounting mask, so that it is not necessary to prepare a mask, and the manufacturing cost can be reduced.
  • the metal bump 71 and the insulating material 81 are formed by curing the insulating material 81A by heating.
  • solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2 and heating in that state, for example, 200 to 280 ° C. ⁇ 10 to 60 seconds. .
  • the obtained insulating material 81 is formed so as to surround the periphery of the metal bump 71.
  • the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by the interfacial tension with the metal bump 71A.
  • the insulating material 81 is filled between the opening 513 and the metal bump 71, but may be filled between the opening 521 and the metal bump 71.
  • the shape of the insulating material 81 is the same as that of the above embodiment.
  • an insulating material 82A is applied to the upper surface of the wiring board 2, that is, the through hole 4a of the first reinforcing member 4 in the same manner as in the first embodiment, and then a metal ball (solder ball) 91A is soldered. Solder bonding to the wiring board 2 is performed by reflow.
  • the metal ball is disposed inside the opening 411 and the opening 420. Thereby, as shown in FIG.21 (d), the metal bump 91 and the insulating material 82 are formed. Such solder bonding can be performed in the same manner as the metal bump 71 described above.
  • the insulating material 82 is filled between the opening portion 411 and the metal bump 71 and between the opening portion 420 and the metal bump 71.
  • the shape of the insulating material 82 is the same as that in the above embodiment.
  • the semiconductor package 1 is obtained as described above.
  • the adhesive layers 42A and 52A are formed on the first and second plate members 4A and 5A, the bonding to the wiring board 2 can be easily performed. . Therefore, the semiconductor package 1 in which warpage is suppressed can be easily manufactured.
  • FIG. 22 is a cross-sectional view schematically showing a semiconductor device including the semiconductor package shown in FIG.
  • the semiconductor device 100 includes a mother board (substrate) 200, a bottom package 300 that is a semiconductor package 1E mounted on the mother board 200, and a top that is another semiconductor package mounted on the bottom package 300.
  • Package 400 the semiconductor device 100 includes a mother board (substrate) 200, a bottom package 300 that is a semiconductor package 1E mounted on the mother board 200, and a top that is another semiconductor package mounted on the bottom package 300.
  • Package 400 is a mother board (substrate) 200, a bottom package 300 that is a semiconductor package 1E mounted on the mother board 200, and a top that is another semiconductor package mounted on the bottom package 300.
  • the metal bumps 71 of the semiconductor package 1E are joined to the terminals (not shown) of the mother board 200, and the metal bumps 91 of the semiconductor package 1E are connected to the terminals (not shown) of the top package 400. ).
  • the semiconductor package 1E, the top package 400, and the mother board 200 are electrically connected, and electrical signals are transmitted among them.
  • the semiconductor package 1E having excellent heat dissipation and reliability as described above since the semiconductor package 1E having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.
  • the top package 400 may be omitted as necessary.
  • a protrusion 43 (53) may be formed on the main body 41 (51) as in the third embodiment. Furthermore, as in the fourth embodiment, an alignment mark may be formed on the main body 41 (51).
  • the reinforcing member, the semiconductor package, and the semiconductor device according to the present invention have been described with respect to the illustrated embodiment.
  • the present invention is not limited to this, and each part constituting the bonded body exhibits the same function. It can be replaced with any configuration obtained. Moreover, arbitrary components may be added.
  • the semiconductor package includes the first reinforcing member and the second reinforcing member, but either one of the first reinforcing member and the second reinforcing member may be omitted.
  • the first reinforcing member has a through hole, and the metal bump is formed in the through hole.
  • the through hole and the metal bump may be omitted.
  • the heat transfer post is formed on the wiring board, but the heat transfer post may not be provided.
  • this invention includes the following aspects.
  • a substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern A reinforcing member joined to at least one of the one surface and the other surface of the wiring board, the plate-shaped main body having a smaller coefficient of thermal expansion than the substrate, and one of the main bodies A reinforcing member provided on a surface side and having an adhesive layer that joins the main body and the wiring board.
  • the adhesive layer includes a heat conductive material that transfers heat of the wiring board to the main body.
  • the said adhesion layer is a reinforcement member as described in (2) comprised by the resin composition containing the resin material and the inorganic filler as the said heat conductive material.
  • a semiconductor device comprising the semiconductor package according to (7).
  • At least one plate member having a plate-like main body having a smaller coefficient of thermal expansion than the substrate and an insulating adhesive layer provided on one surface side of the main body. And preparing at least one plate member and at least one of the one surface and the other surface of the wiring substrate with the adhesive layer of the plate member facing the wiring substrate.
  • a semiconductor package comprising: a second step of bonding to a surface; and a third step of obtaining a reinforcing member by processing the plate member bonded to the wiring board into a desired shape.
  • Manufacturing method (10) The method for manufacturing a semiconductor package according to (9), wherein the adhesive layer also functions as a solder resist that protects at least one of the first conductor pattern and the second conductor pattern.
  • the plate member As the plate member, a first plate member bonded to the one surface of the wiring board and a second plate member bonded to the other surface of the wiring substrate are prepared.
  • the first plate member is bonded to the one surface of the wiring board, and the second plate member is bonded to the other surface of the wiring substrate (9) or ( 10.
  • the body of the plate member is processed into a desired shape by wet etching, and an opening is formed at a desired position of the adhesive layer by irradiating the adhesive layer with a laser.
  • the adhesive layer is made of a resin composition including a resin material and an inorganic filler as the heat conductive material.
  • a semiconductor device comprising the semiconductor package according to (17).
  • a wiring board provided with a film-like second solder resist provided on the other surface so as to cover the second conductor pattern and having an opening exposing a predetermined portion of the second conductor pattern, and the board
  • a third step of obtaining a reinforcing member by processing the plate member into a desired shape (20)
  • a first plate member bonded to the one surface of the wiring board and a second plate member bonded to the other surface of the wiring substrate are prepared.
  • the first plate member is bonded to the one surface of the wiring board, and the second plate member is bonded to the other surface of the wiring substrate (19).
  • Semiconductor package manufacturing method (21)
  • the body of the plate member is processed into a desired shape by a wet etching process, and an opening is formed at a desired position of the adhesive layer by irradiating the adhesive layer with a laser. The method for manufacturing a semiconductor package according to (19) or (20).
  • a film-like first solder resist provided on the one surface side of the substrate so as to cover the first conductor pattern, and having an opening exposing a predetermined portion of the first conductor pattern
  • the substrate A wiring board provided with a film-like second solder resist provided on the other surface so as to cover the second conductor pattern and having an opening exposing a predetermined portion of the second conductor pattern, and the board
  • the manufacturing method of the semiconductor package characterized by the above-mentioned.
  • the adhesive layer includes a heat conductive material that transfers heat of the wiring board to the main body.

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Dans la présente invention, un substrat de câblage (2) comporte un substrat (21), un premier motif conducteur (221) disposé sur un côté du substrat (21), et un second motif conducteur (224) disposé sur l'autre côté du substrat (21) et connecté électriquement au premier motif conducteur (221), et un élément de renfort (4) est assemblé au substrat de câblage (2) sur au moins l'un des deux côtés du substrat (21). L'élément de renfort (4) présente un corps en forme de plaque (41) avec un coefficient de dilatation thermique inférieur à celui du substrat de câblage (2), et une couche d'adhésion (42) qui est disposée sur un côté du corps (41) et qui assemble le corps (41) au substrat de câblage (2).
PCT/JP2012/003627 2011-06-06 2012-06-01 Élément de renfort, boîtier de semi-conducteur, dispositif à semi-conducteur et procédé de fabrication pour un boîtier de semi-conducteur Ceased WO2012169162A1 (fr)

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WO2019058967A1 (fr) * 2017-09-25 2019-03-28 日東電工株式会社 Bobine d'induction et son procédé de fabrication
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US9412806B2 (en) 2014-06-13 2016-08-09 Invensas Corporation Making multilayer 3D capacitors using arrays of upstanding rods or ridges
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