WO2013091908A1 - Procédé et dispositif d'insertion d'instructions de synchronisation dans des secteurs d'un programme - Google Patents

Procédé et dispositif d'insertion d'instructions de synchronisation dans des secteurs d'un programme Download PDF

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Publication number
WO2013091908A1
WO2013091908A1 PCT/EP2012/062571 EP2012062571W WO2013091908A1 WO 2013091908 A1 WO2013091908 A1 WO 2013091908A1 EP 2012062571 W EP2012062571 W EP 2012062571W WO 2013091908 A1 WO2013091908 A1 WO 2013091908A1
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WO
WIPO (PCT)
Prior art keywords
program
command
ssi
resource
wait
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2012/062571
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German (de)
English (en)
Inventor
Stefan Kempf
Ronald VELDEMA
Michael Philippsen
Michael Wieczorek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Friedrich Alexander Universitaet Erlangen Nuernberg
Siemens Corp
Original Assignee
Siemens AG
Friedrich Alexander Universitaet Erlangen Nuernberg
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Friedrich Alexander Universitaet Erlangen Nuernberg, Siemens Corp filed Critical Siemens AG
Publication of WO2013091908A1 publication Critical patent/WO2013091908A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/458—Synchronisation, e.g. post-wait, barriers, locks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/456—Parallelism detection

Definitions

  • the invention relates to a method for inserting synchronization commands into program sections of a program.
  • PLC Programmable Logic Cont ⁇ roller
  • the synchronization commands may be, for example, release and wait commands.
  • the invention relates to a device for inserting synchronization commands into program sections of a program.
  • the invention has for its object to provide a method by which a freedom from error of the insertion of synchronization commands can be increased.
  • this object is achieved by providing a method for inserting synchronization commands into program sections of a program, which The following steps include:
  • the device is prepared to insert a release command after a write command of a first program section to a resource that is shared by the first program section and a second program section if the write command to the resource from the first program section , wherein an embodiment of the enable command, a condition variable set into a set status execute a Le ⁇ sebenning the second program portion of the resource.
  • DA in the device is prepared to insert a wait command for waiting for the Set condition of the conditional variable prior to the read instruction of the second program section on the res ⁇ source, wherein execution of the wait command causes the second program portion to tion with a continuation of the execution of the to wait for the second part of the program until the condition variable is set.
  • the parallel version of the sequential program is synchronized without errors. Furthermore, the method can be automated, so that it can help to reduce a work time for creating a sequential Pro ⁇ program. It is useful if the condition variable ei occasion ⁇ ner program initialization and is in an execution of the corresponding wait command reset. This can be recognized in test runs when a release command is unintentionally used by several wait commands.
  • a preferred embodiment provides that the method comprises a step for detecting a data dependency between parallel callable program sections. Is also preferred if the method comprises a step of determining which pairs of writing and ⁇ Lesebe missing in a predetermined order and which are run sequence must be followed in this case. By pre ⁇ called both measures, the synchronisationsver- will drive amenable to automation.
  • the method includes a step of recognizing a path that bridges a path with a write command to be synchronized to a resource, and a step of having a release command for that resource in the bridging path is inserted. This results in a flawless Since ⁇ tensynchronisation is possible even when a thread has a branch, which results in that a write command is carried out only under certain circumstances. It is also preferable to provide resource-specific or parti- tion-specific condition variables. An optimization option determines that a runtime requirement for different alternatives of partitions is determined and then the one or the alternatives with the lowest runtime requirements are used. The two aforementioned measures can help improve computational performance by reducing a sum of thread latencies.
  • the method includes a step of removing a second condition variable along with its associated release and wait instructions if each release command on a first condition variable postdoments each release command on the second condition variable and each wait command on the first condition variable each wait command on the second condition variable dominates.
  • 1 shows in the upper part schematically a sequence of a sequential program and in the lower part a sequence of a parallelized variant of the sequential program with error-free access order; 2 schematically shows a sequence of an embodiment of a
  • FIG. 3 schematically shows an example of a parallelized program in which a condition variable can be removed together with associated synchronization commands
  • Representation in the upper part schematically shows a first program loop that includes a write command to a memory location, and a subsequent program section that includes a read command to the Spei ⁇ cherstelle, and in the lower part schema ⁇ table a second program loop that fails a Lesebe ⁇ to a memory location and which connects to a program section that includes a write command to the memory location.
  • Programmable logic control programs access memory locations, actuators, and sensors to monitor and control engineering processes.
  • Future generations of programmable logic controllers will use multi-core processors.
  • programs for programmable logic controllers in parallel running strands (threads) up ⁇ shares must be.
  • race races data races
  • 'location' Memory locations whose contents are changed during program execution by means of write commands can also be referred to as variables.
  • FIG 1 shows a flow of SEQUENTIEL ⁇ len program 10.
  • SSi may be an external variable or a global one (but not mandatory).
  • memory locations SSi also subsume other memory-related system components than just memory locations SSi of a data memory in the strict sense. It should also be not necessarily assumed that a memory location SSi maintains its data ⁇ content between a write command 31 and a directly subsequent read command 32 unchanged.
  • a change in the data content may, for example, be design-specific if (not shown in the figures) there is a conflict of interest ing write accesses from a second bus system are vorgese ⁇ hen, or if a purpose of the program code is just to detect an unwanted change in the data content of a memory location SSi.
  • a (not shown in the figures) pair are viewed from an actuator and a sensor for the present purposes as a memory location SSi when the Ak ⁇ tor is suitable (for example, as an actuator of a control loop) to a ( physical) size and the sensor is intended to measure the (physical) size (for example, as a controlled variable).
  • a write command 31 of the first program section PA1 to a first memory location SSi may not after the write ⁇ command 31 of the second program section PA2 be performed in the SpeI ⁇ cherstelle SSi because the memory location SSi otherwise (from the perspective of the second program section PA2 and also from the viewpoint evtl further subse- quent program sections) could be incorrectly pre-assigned.
  • the read command 32 of the second program section PA2 to the storage location SSi must not be executed before the write command 31 of the first program section PA1 to the storage location SSi, because the storage location SSi otherwise from the perspective of the second program section PA2 (and off
  • FIG. 1 shows a sequence of a parallelized variant 12 of the sequential program with faulty free access order.
  • FIG. 2 shows a sequence of an embodiment of a method for producing a data synchronization.
  • the method 100 described in Fol ⁇ constricting is proposed:
  • a first step 110 for example, the dependency analysis described in Much Nick, Steven S .: “Advanced Compiler Design &Implementation" is examined, which data ⁇ dependencies between parallel callable program sections PA1, PA2 (e.g., program modules) are made.
  • the release commands 41 to set condition variables c and the waiting commands 42 for waiting for a Set ⁇ state of condition variables c are known synchronization primitives.
  • the condition variable c can be ⁇ play realized at by means of a flag or in the form of a Softwa- reinterrupt message.
  • Waiting commands 42 NEN with polling (by requesting an associated condition variable c) or in the interrupt process (by receiving a message that is generated by a release command 41) can be realized.
  • the release command 41 for setting a condition variable c may be inserted, for example, immediately after the write command 31 to be protected.
  • the wait command 42 for waiting for a set state of the conditional variable c may be inserted, for example, immediately before a read command 32 to be protected.
  • Each condition variable c is reset at program initialization to ⁇ .
  • the first program section PA1 a branching contained ⁇ th which causes the path with the write command 31 is executed under a specific constraint (which may comprise a plurality of boundary conditions) is run through, and otherwise a different path.
  • similarly acting condition variables c must also be inserted into all those program paths of the first program section PA1 which are passed through without a write command 31 being performed therein. This prevents the second pro- program section PA2 with the wait 42 for an infinitely long time on a release (set state of the conditional variable c) was ⁇ tet when the first program section PA1 is run on paths ⁇ in which the write command 31 is not performed.
  • release instructions 41, wait instructions 42 and condition variables c which are specific for each synchronization point 5j, even if different synchronization points 5j
  • Write and read commands 31, 32 are synchronized to a same memory location SSi. It is then not just a memory location-specific, but also a synchronization-specific synchronization.
  • a SSi spei ⁇ cher stellenspezifische condition variable c also a Parti ⁇ tion be associated with (in other words subset group or Freigabegrup ⁇ pe) of memory locations SSi.
  • the enable command 41 for setting the partition-specific conditional variable c may not be inserted until the write commands 31 for all the memory locations SSi of the partition have been completed in program sections to be executed beforehand.
  • the wait command 42 must be inserted before any read command 32 for one of the memory locations SSi of the partition is executed in subsequently executed program sections PA2.
  • the partition can include all memory locations SSi that are to be synchronized somewhere in the program sequence.
  • the condition variable c need not be memory location-specific.
  • the device which inserts the release commands 41 and the wait commands 42, the runtime requirements for different alternatives of partitions determined and then uses that alternative or one of the age ⁇ native with the lowest duration requirement.
  • a first command A dominates a second command B if the first command A is always guaranteed to be executed before the second command B.
  • a first command A postdominates a second command B if the first command A is always guaranteed to be executed after the second command B.
  • synchronization commands ie enable and wait commands
  • SSi shared memory location
  • each release command 41 on a first condition variable c each Release Certificates ⁇ bebetation 41 'on a second condition variable c', and do ⁇ miniert each wait command 42 on the first Bedingungsvariab ⁇ le c each wait command 42 'on the second condition variable c', then For example, the second condition variable c 'may be removed along with its associated enable commands 41' and wait instructions 42 '.
  • the read command 32 ' can only be executed after the release command 41 has been executed on the first condition variable c.
  • the second conditional variable c 'together with the associated synchronization commands 41 ', 42' are removed. Since also the synchronization commands 41 ', 42' cause runtime costs, this can contribute to the reduction of the computing time.
  • the first program loop 81 illustrated which includes a Schreibbe ⁇ lack 31 to a location SSi, and a subsequent program portion 84 which includes a read command 32 to the memory location SSi.
  • program loops 81, 82 represent a notation for a repetition of the loop contents 80, ie a notation for a chain of repeated executions of the loop contents 80.
  • a program section 84 following a first program loop 81 does not follow each loop pass of the first program loop 81, but only the last loop pass.
  • a program section 84, which is followed by a second program loop 82 does not precede every loop run of the program loop 82, but only the loop pass performed first.
  • a program section 84 which follows a first program loop 81 reads from a memory location SSi which is described within the program loop 81, then execution of the program section 84 following the first program loop 81 must be stopped so long as until the writing of the memory location SSi is completed in the last loop pass. To do so, the setting of the conditional variable c (the execution of the release command 41) may be made conditional on the fact that it is the last loop pass. Taking this proviso into account, it is not absolutely necessary to set the release instruction 41 to the end 86 of the program loop 81. To To remind the conditionality of the release command 41, the release command 41 is shown in dashed lines in FIG.
  • Evaluate program loop 81 It may also be that for reasons of clarity to monitor the termination condition for this purpose is undesirable (for example ei ⁇ ner while, for-each- or forever loop or when the demolition decision depends on a variable termination criterion, the decision parameters only present at the end 86 of the first program loop 81 and not at the time of the release command 41). There is also the alternative of inserting the release command 41 immediately behind or at the end 86 of the previously executed program loop 81 for setting the conditional variable c.
  • a loop content 80 within a (non-parallelized) second program loop 82 reads from a memory location SSi described by a previous program portion 84.
  • a second program loop 82 is shown, which comprises a read command 32 to a memory location SSi and connects to the preceding program section 84, which comprises a write command 31 to the memory location SSi.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne un dispositif et un procédé (100) servant à insérer des instructions de synchronisation (41, 42) dans des secteurs (PA1, PA2) d'un programme (10, 12) en vue de la synchronisation de données. Pour ce faire, une instruction de validation (41) est automatiquement insérée après une instruction d'écriture (31) d'un premier secteur (PA1) du programme sur une ressource (SSi), qui est utilisée conjointement par le premier secteur (PA1) du programme et par un deuxième secteur (PA2) du programme, dans le cas où l'instruction d'écriture (31) sur la ressource (SSi) doit être exécutée par le premier secteur (PA1) du programme avant une instruction de lecture (32) du deuxième secteur (PA2) du programme sur la ressource (SSi), une exécution de l'instruction de validation (41) mettant une variable conditionnelle (c) dans un état actif. Une instruction d'attente (42) servant à attendre l'état actif de la variable conditionnelle (c) est insérée automatiquement sur la ressource (SSi) avant l'instruction de lecture (32), une exécution de l'instruction d'attente (42) faisant en sorte que le deuxième secteur (PA2) du programme attende une poursuite du traitement du deuxième secteur (PA2) du programme jusqu'à ce que la variable conditionnelle (c) soit activée.
PCT/EP2012/062571 2011-12-20 2012-06-28 Procédé et dispositif d'insertion d'instructions de synchronisation dans des secteurs d'un programme Ceased WO2013091908A1 (fr)

Applications Claiming Priority (2)

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DE102011089180 2011-12-20
DE102011089180.3 2011-12-20

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050108695A1 (en) * 2003-11-14 2005-05-19 Long Li Apparatus and method for an automatic thread-partition compiler

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050108695A1 (en) * 2003-11-14 2005-05-19 Long Li Apparatus and method for an automatic thread-partition compiler

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MCCLOSKEY, B. ET AL.: "Autolocker: Synchronization Inference for Atomic Sections", CONF. RECORD OF THE 33RD ACM SIGPLAN-SIGACT SYMPOSIUM OF PRINCIPLES OF PROGRAMMING LANGUAGES, POPL '06, pages 346 - 358
NAIK, M. ET AL., EFFECTIVE STATIC RACE DETECTION FOR JAVA, PROCEEDINGS OF THE ACM SIGPLAN CONFERENCE ON PROGRAMMING LANGUAGE DESIGN AND IMPLEMENTATION, PLDI '06, pages 308 - 319

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