Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of DC power input into DC power output
  • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
  • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
  • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
  • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
  • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M3/338—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in a self-oscillating arrangement
  • H02M3/3382—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in a self-oscillating arrangement in a push-pull circuit arrangement
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K7/00—Modulating pulses with a continuously-variable modulating signal
  • H03K7/08—Duration or width modulation ; Duty cycle modulation

Definitions

• the present invention relates to the field of power supply control, and in particular, to a method and a circuit for generating an interleaved complementary PWM driving waveform. Background technique
• the resonant topology especially the LLC resonant topology, has become the industry's first choice for high-efficiency, high-power-density switching power supply solutions. It has a wide range, soft switching operation, and low main power components. As shown in Figure 1, the half-bridge resonant topology, the full-bridge resonant topology of Figure 2 is easy to implement in small and medium power supplies (below 2 kW), but the high power supply has a wide operating frequency due to the resonant topology, and the magnetic components are designed. The challenge is raised.
• the power converter is guaranteed to be in the entire controller output range by adjusting the combination of power converter frequency and duty ratio.
• the control device of the power converter of the resonant topology circuit includes a control module for adjusting the combination of the power converter frequency and the duty ratio to ensure that the power converter has good performance in the entire controller output range.
• the device is mainly to ensure the monotonicity of the power converter of the topology circuit over the entire PWM operating range.
• the technical problem to be solved by the present invention is to provide a method for providing two sets of a total of four driving signals for an interleaved parallel resonant topology.
• a technical solution adopted by the present invention is: Providing a method for generating an interleaved complementary PWM driving waveform, comprising the following steps:
• S200 Performing an exclusive OR operation on the two signals in the first group to obtain the first sub-signal based on the generated two sets of signals; and performing an exclusive OR operation on the two signals in the second group to obtain the second sub-signal;
• the first sub-group signal and the second sub-group signal are generated by using the rising edge and the falling edge of the first sub-signal and the second sub-signal based on the first sub-signal and the second sub-signal, and the two sub-group signals are out of phase difference 90 Degree, the two signals in each subgroup are complementary;
• step S100 the frequency modulation PWM driving signal is output by the resonance control chip.
• the FM PWM driving signal is a two-way PWM driving signal outputted by the resonant control chip MC33067.
• Step S300 is implemented by a D flip-flop, a NOT gate, and an AND gate.
• Step S400 is implemented by a NOT gate and an AND gate.
• the technical solution further provides an interleaved complementary PWM driving waveform generating circuit, including:
• the frequency dividing module is configured to divide the two frequency-modulated PWM driving signals by two, and obtain two sets of four signals in total, and the phase difference between the groups is 90 degrees, and the phase difference between the groups is one dead zone width, and the duty ratio is 50. %;
• a sub-signal generating module configured to perform an exclusive-OR operation on the first group of signals to obtain a first sub-signal; and perform an exclusive-OR operation on the second group of signals to obtain a second sub-signal;
• a sub-group signal generating module configured to receive the first sub-signal and the second sub-signal, and obtain a first sub-group signal and a second sub-group signal by a logic operation of a flip-flop, an AND gate or an OR gate, and the two sub-group signals have a phase difference 90 degrees, two signals in each subgroup are complementary, and a square wave with a duty cycle of 50%;
• a PWM driving generating module configured to invert the first sub-signal and respectively pair with the first sub-group signals to obtain a first path and a second path signal, and invert the second sub-signal and the second sub-group
• the two signals are phase-matched to obtain the third and fourth signals, and the first, second, third, and fourth signals are interlaced 90-degree phase angles, and four PWM-driven square waves with dead zones.
• the frequency dividing module comprises two sets of parallel frequency dividing circuits
• the sub signal generating module comprises two sets of juxtaposed sub-signal generating circuits
• the sub-group signal generating module comprises two sets of parallel sub-group signal generating circuits
• the PWM driving generating module comprises two a parallel PWM driving generation circuit
• the output end of the frequency dividing circuit is connected to the input end of the sub-signal generating circuit
• the output end of the sub-signal generating circuit is connected to the input end of the sub-group signal generating circuit
• the output end of the sub-group signal generating circuit is connected to the PWM Driving the input end of the generating circuit
• the frequency dividing circuit comprises an inverter, a first flip-flop and a second flip-flop
• the first flip-flop and the second flip-flop each comprise a clock input terminal, a Q terminal and a /Q terminal
• the signal generating circuit includes an exclusive OR gate, and the XOR gate includes a first input end, a second input end,
• the first to third triggers are all CD4013 triggers.
• a driving signal is generated digitally through a programmable logic device chip such as an FPGA or a DSP.
• the technical solution generates two sets of common four-way PWM signals by using an interleaved complementary PWM driving waveform generating method: first, second, third, and fourth paths, and the phase difference between the two groups is 90 degrees, each group
• the two internal PWM signals are complementary.
• These four complementary drive signals serve as four drive signals for the interleaved parallel resonance topology, thereby improving power supply efficiency and power density.
• FIG. 1 is a circuit diagram of a half-bridge resonant topology interleaved parallel connection using two driving signals OUTA and OUTB in the prior art
• FIG. 2 is a circuit diagram of applying a two-way driving signal OUTA and OUTB to realize full-bridge resonant topology interleaving and parallel connection in the prior art;
• FIG. 3 is a circuit diagram of an implementation method for implementing interleaved parallel control using four driving signals A, B, C, and D in the prior art;
• FIG. 5 is a waveform diagram of each step of the method for generating an interleaved complementary PWM driving waveform according to the technical solution of the present invention
• FIG. 6 is a circuit structural diagram of an embodiment of an interleaved complementary PWM driving waveform generating circuit of the present technical solution
• FIG. 7 is a flowchart of a method for generating an interleaved complementary PWM driving waveform according to the present technical solution
• FIG. 8 is a circuit structure of an embodiment of a PWM driving generating circuit of the present technical solution. Figure.
• 1 frequency division module 2 sub-signal generation module; 3 sub-group signal generation module;
• PWM drive generation module 5 frequency division circuit; 6 sub signal generation circuit; 7 subgroup signal generation circuit; 8 PWM drive generation circuit;
• an interleaved complementary PWM driving waveform generating method provided by the present invention specifically includes the following steps:
• S200 performing an exclusive OR operation on the first group of signals based on the generated two sets of signals to obtain a first sub-signal; and performing an exclusive-OR operation on the second group of signals to obtain a second sub-signal;
• the resonant control chip can be MC33067 of On Semiconductor, L6599 of ST, or UC3863 and UCC25600 of TI.
• the signal output by the resonant control chip is a typical two-way PWM drive signal of the MC33067.
• the rising and falling edges of the two PWM PWM drive signals are divided by two. 2 After frequency division, two sets of four signals are obtained, which are similar to signal AR, signal / BF, and signal /AF, signal / BR.
• the phase difference between the groups is 90 degrees, and the phase difference between the groups is one dead zone width. 50%.
• the signal AR obtained by dividing the frequency and the signal /BF, the signal /AF and the signal /BR are XORed to obtain two driving signals, which are the first sub-signal DB1 and the second sub-signal DB2, respectively.
• the first sub-signal DB1 and the second sub-signal DB2 have a phase difference of 90 degrees, and the widths of the two signals are dead zone widths.
• the first sub-group signal and the second sub-group signal are obtained by logic operations of the flip-flop, the AND gate or the OR gate, the first sub- The group signal includes the signal DB1R, the signal / DB1R, and the second subgroup signal includes the signal DB2R, the signal /DB2R, the two subgroup signals are 90 degrees out of phase, the two signals in each subgroup are complementary, and the square wave with a duty ratio of 50% .
• the signal DB1R and the signal /DB1R are inverted with the first sub-signal DB1 to obtain a first PWMA and a second PWMB.
• the signal DB2R, the signal /DB2R and the second sub-signal DB2 are inverted and then ANDed to obtain a third PWMC and a fourth PWMD.
• the first PWMA, the second PWMB, the third PWMC, and the fourth PWMD are four-way PWM-driven square waves with a 90-degree phase angle and dead zones.
• the interleaved circuit generates an interleaved signal AR, a signal / BF, a signal /AF, a signal /BR, and then directly through a logic gate operation to obtain a four-way PWM with a phase angle of 90 degrees and a dead zone.
• the first PWMA, the second PWMB, the third PWMC and the fourth square wave PWMD are driven. Instead of generating the intermediate first sub-signal DB 1, the second sub-signal DB2.
• step S300 is implemented by a D flip-flop, a NOT gate, and an AND gate
• step S400 is implemented by a NOT gate and an AND gate.
• the interleaved complementary PWM driving waveform generating circuit includes: a frequency dividing module 1 for two-way frequency modulation
• the PWM drive signal is divided by two to obtain two sets of four signals.
• the phase difference between the groups is 90 degrees.
• the phase difference between the groups is one dead zone width, and the duty ratio is 50%.
• a sub-signal generating module 2 configured to perform an exclusive-OR operation on the first group of signals to obtain a first sub-signal; and perform an exclusive-OR operation on the second group of signals to obtain a second sub-signal;
• the sub-group signal generating module 3 is configured to receive the first sub-signal and the second sub-signal, and obtain a first sub-group signal and a second sub-group signal by a logic operation of a flip-flop, an AND gate or an OR gate, and the two sub-group signal phases The difference is 90 degrees, the two signals in each subgroup are complementary, and the square wave with a duty ratio of 50%;
• the PWM driving generating module 4 is configured to invert the first sub-signal and then pair with the first sub-group signals to obtain the first path and the second path signal, and invert the second sub-signal and the second sub-signal.
• the two signals are combined to obtain the third and fourth signals.
• the first, second, third and fourth signals are interlaced with a 90-degree phase angle and four PWM drivers with dead zones. wave.
• the frequency dividing module includes two sets of parallel frequency dividing circuits 5, the sub signal generating module includes two sets of juxtaposed sub-signal generating circuits 6, and the subgroup signal generating module includes two sets of juxtaposed subgroup signals.
• the generating circuit 7, the PWM driving generating module comprises two sets of parallel PWM driving generating circuits 8, the output end of the frequency dividing circuit 5 is connected to the input end of the sub-signal generating circuit 6, and the output end of the sub-signal generating circuit 6 is connected to the sub-group signal generating circuit.
• the input end of the sub-group signal generating circuit 7 is connected to the input end of the PWM driving generating circuit 8, as shown in the structure diagram of the circuit shown in FIG.
• the frequency dividing circuit 5 includes an inverter, and the first trigger And the second flip-flop; the first flip-flop and the second flip-flop each include a clock input terminal, a Q terminal, and a /Q terminal; the sub-signal generating circuit includes an exclusive OR gate, and the XOR gate includes a first input end and a second input And the output end; the clock input end of the first flip-flop is externally connected with the first FM PWM drive signal, the Q end of the first flip-flop is connected to the first input end of the XOR gate, and the output end of the XOR gate is connected to the dead zone to generate The input end of the circuit; the /Q terminal of the first flip-flop is suspended; the input end of the inverter is externally connected with the second FM PWM drive signal, and the output end of the inverter is connected to the clock input end of the second flip-flop, the second flip-flop The Q terminal is suspended, the /Q terminal is connected to the second input terminal of the XOR gate; the sub-group
• the first to third triggers are all CD4013 triggers.
• the N/2 (N is an odd-numbered) frequency-dividing circuit has an important application. For a specific input frequency, the required output can be obtained by dividing by N/2, which requires the circuit to have N/. A non-integer multiple of the frequency division function of 2.
• the CD4013 is a dual-D flip-flop. It is convenient to form a N/2 frequency dividing circuit based on a number of two-way circuits composed mainly of CD4013 and feedback control such as XOR gate.
• the input terminals of the frequency dividing circuit 5 are externally connected to the FM PWM driving signals OUTA, OUTB, and finally the output of the PWM driving generating circuit outputs two paths.
• the interleaved complementary PWM drive waveform, the first PWMA, the second PWMB, the second half of the second circuit 10 (below the horizontal dashed line) has the same structure as the upper half, and the input terminal is externally connected to the PWM drive signals OUTA, OUTB.
• the output terminal outputs the third PWMC and the fourth PWMD.
• the second circuit 10 which is juxtaposed with the first circuit 9 described above, outputs a driving waveform third PWMC and a fourth PWMD.
• the first PWMA, the second PWMDB, the third PWMC, and the fourth PWMD are interlaced with a 90 degree phase angle, with dead zones, and complement each other.
• the generated first PWMA, the second PWMDB, the third PWMC, and the fourth PWMD driving signal are used in the parallel topology circuit shown in FIG. 3, thereby implementing the function of interleaving parallel control.
• the parallel resonant topology is two resonant topologies, which may be a LLC resonant topology.
• Each resonant topology includes at least two power transistors, one resonant inductor, and one resonant capacitor.
• the method is simple, and the cost is low, which solves the design problem of the magnetic component, and can greatly reduce the ripple current of the output filter capacitor C500 in FIG.
• the number and capacity of the output filter capacitors are reduced, and the power supply efficiency and the power density are further improved.
• the first to third flip-flops are all CD4013 triggers.
• the resonance topology in the present technical solution includes, but is not limited to, series resonance, parallel resonance, and LLC resonance.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Dc-Dc Converters (AREA)

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Citations (5)

• 2012
  • 2012-01-31 WO PCT/CN2012/070789 patent/WO2013113149A1/fr not_active Ceased

Patent Citations (5)

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