Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/662—Vertical DMOS [VDMOS] FETs having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
  • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/156—Drain regions of DMOS transistors
  • H10D62/157—Impurity concentrations or distributions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/411—Insulated-gate bipolar transistors [IGBT]
  • H10D12/441—Vertical IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
  • H10D62/126—Top-view geometrical layouts of the regions or the junctions
  • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
  • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

• the present invention relates to a vertical-conduction electronic device and to a process for manufacturing the same.
• the present invention relates to a MISFET (Metal Insulator Silicon Field Effect Transistor) device.
• MISFET Metal Insulator Silicon Field Effect Transistor
• VMOSs vertical MOSFET devices
• body regions having a conductivity type (e.g., of a P type), housed at a short distance from one another in a substrate or epitaxial layer having an opposite conductivity type (e.g., of an N type).
• a parasitic JFET which is activated when the VMOS device conducts.
• the resistance of the parasitic JFET basically depends not only upon the operating conditions and the doping level of the epitaxial layer, but also upon its channel width, i.e., upon the distance between body regions extending alongside one another. In practice, the greater the distance between the body regions, the lower the resistance of the JFET, and vice versa.
• the portion of epitaxial layer forming the channel of the JFET is overlaid by gate electrodes, normally made of polysilicon, which are insulated only through a gate-oxide layer and remain capacitively coupled. The effect of the capacitive coupling, however, increases as the distance between the body regions increases, unlike the resistance of the parasitic JFET, which decreases.
• a first measure envisages an enrichment implant for increasing doping in a surface layer of the wafer housing the VMOS device so as to increase the conductivity.
• the enrichment can be obtained by epitaxial growth of a layer having an appropriate doping level.
• the maximum doping of the body regions differs only a little from the doping of the epitaxial layer.
• the surface enrichment extending to the entire wafer could thus interfere significantly with the threshold voltage and the length of the VMOS channel (which extends in the proximity of the surface of the body regions) and even jeopardize operation of the device (premature "punch- through").
• the surface enrichment is normally made selectively, for example with masked implants, and confined to portions of the epitaxial layer comprised between the body regions and set at a slight distance from the latter.
• a further measure aimed at improving the dynamic performance regards the use of gate-oxide layers with differentiated thicknesses. More precisely, localized growths of oxide are performed above the areas forming the channel of the parasitic JFET. A solution of this type is described, for instance, in the patent document No. US 7,800,173. In this solution, however, the gate charge, the- dynamic performance, and the capacitance associated to the oxide in the region between the cells are not optimized.
• the aim of the present invention is to provide a vertical- conduction electronic device and a corresponding manufacturing process that will enable the drawbacks of the known art to be overcome, and in particular will enable a reduction of the parasitic resistance and of the dimensions, without jeopardizing the dynamic performance.
• FIG. 1-13 show manufacturing steps for forming a vertical-conduction electronic device (in particular, a VDMOS) according to one embodiment of the present invention
• FIG. 14 shows a vertical-conduction electronic device according to a further embodiment of the present invention.
• FIG. 15 shows a schematic cross section of a semiconductor device according to one embodiment of the present invention.
• FIG. 16 shows a system that uses the electronic device according to any one of the embodiments of the present invention.
• Figure 1 shows a wafer 1 of semiconductor material in an initial step of a process for manufacturing a vertical- conduction metal-insulator-silicon FET (or vertical MISFET) device, in particular a vertical-conduction MOS, or VMOS, transistor, even more in particular a double-diffused vertical-conduction MOS (VDMOS) transistor.
• a vertical- conduction metal-insulator-silicon FET or vertical MISFET
• MOS vertical-conduction MOS
• VMOS vertical-conduction MOS
• VDMOS double-diffused vertical-conduction MOS
• the wafer 1 comprises a substrate 2, of an N type (in particular having a heavy doping of an N+ type) , with a front side 2a and a rear side 2b, opposite to one another.
• the wafer 1 further comprises a semiconductor layer 3 that is less doped (in the example, with a doping of an N type) , for instance grown epitaxially on top of the front side 2a of the substrate 2 (in what follows, designated as "epitaxial layer 3") .
• the epitaxial layer hence has, in this step, a front side 3a of its own exposed and a rear side 3b coinciding with the front side 2a of the substrate 2.
• the wafer 1 is, for example, of a pre-processed type.
• the wafer 1 comprises, in a way not shown in the figures, board-termination structures formed by field-oxide regions designed to delimit one or more active areas 4 in the epitaxial layer 3.
• the active area 4 houses the VDMOS device.
• a protective layer 7 having the function of stopping layer for subsequent steps of etching and cleaning of the front 3a of the wafer 1.
• the protective layer 7 is, for example, made of silicon nitride or silicon oxide, or some other material.
• the protective layer 7 is, according to one embodiment, formed by chemical vapour deposition (CVD) , and has a thickness comprised between approximately 10 nra and approximately 300 nm, for instance approximately 100 nm.
• the protective layer 7 is omitted.
• the next step is formation of a trench 8 in the epitaxial layer 3.
• the trench 8 extends in the epitaxial layer 3 for a depth, measured starting from the front side 3a, comprised between approximately 0.1 ⁇ and approximately 1.5 ⁇ , for instance approximately 0.8 ⁇ .
• the depth of the trench 8 depends upon the class of voltage of the device and is the greater the higher the class of voltage considered.
• the trench 8 has the shape, in top plan view, of a strip, as shown in Figure 2b.
• a photoresist layer 10 is formed on top of the protective layer 7. Then, by means of a step of photolithography, an opening is defined in the photoresist layer 10 until a portion of the protective layer 7 is exposed. Said opening has a shape, in top plan view, corresponding to the desired shape for the trench 8.
• the next step is that of etching the protective layer 7, for example using a dry etch. Other types of etching, for instance wet etching, can be used according to further embodiments.
• This is followed by a step of etching of the epitaxial layer 3, for example an anisotropic dry etch, using, as etching chemistry, a mixture of SF 6 and C 4 F 8 .
• the trench 8 thus formed presents substantially vertical side walls 8' (i.e., extending substantially orthogonal to the front side 3a) , and a bottom 8" extending in a plane substantially parallel to the front side 3a.
• the enriched region 12 is formed by an enrichment implant, exploiting the mask formed by the protective layer 7 and the photoresist layer 10 (which protects the entire front side 3a except for the portion of the epitaxial layer 3 in which the trench 8 has been formed during the step of Figure 2a) . Then, following upon the implantation step, the photoresist layer 10 is removed. The photoresist layer 10 can also be removed prior to the step of enrichment implantation. In this case, the mask for the enrichment implant is formed by just the protective layer 7.
• the enriched region 12 is of an N type and is obtained using dopants such as phosphorus or arsenic, with a density comprised between 10 13 atoms/cm 3 and 10 17 atoms/cm 3 .
• the implantation energy is such that the dopant species extend in the epitaxial layer for a final depth, measured starting from the inner walls 8' and the bottom 8" of the trench 8, comprised between approximately 0.3 ⁇ and approximately 1.0 ⁇ , for instance approximately 0.7 ⁇
• the implantation dose is approximately constant along the entire side walls 8' and the bottom 8" of the trench 8.
• to provide a constant implantation profile on the side walls 8' and on the bottom 8" it is possible to configure the angle of implantation appropriately during the implantation step .
• dopants such as boron or aluminium substantially with the same concentrations indicated above can be implanted.
• the enriched region 12 can be formed according to a technique different from the implantation of dopant species represented in Figure 3, namely, by partial filling of the trench 8 through a process of epitaxial growth. Said variant is shown in Figure 4. Partial epitaxial filling of the trench 8 is preferably uniform and is obtained by growth of a layer of monocrystalline silicon with a doping of an N type (and with a doping value higher than that of the epitaxial layer 3) according to the known art.
• the process of epitaxial growth is carried out in a chamber for epitaxial growth in the presence of phosphorus or arsenic atoms in such a way that the region grown epitaxially will have a density of dopants comprised between 10 13 atoms/cm 3 and 10 17 atoms/cm 3 .
• the enriched region 12 is thus obtained.
• the enriched region 12 thus formed extends over the inner walls 8' and on the bottom 8" of the trench 8 and has an approximately uniform thickness comprised between 0.3 ⁇ and approximately 1.0 ⁇ , for example approximately 0.7 pm.
• an appropriate chemical etching agent is used within the epitaxial-growth reaction chamber, mixed with the source gas used for the epitaxial growth itself, said chemical agent being able to modulate appropriately the rate of epitaxial growth.
• a dynamic balancing is obtained between the epitaxial growth along the walls 8' and the bottom 8" of the trench 8 and the simultaneous removal of part of the layer grown so as to obtain an epitaxial layer that extends homogeneously over the walls 8' and on the bottom 8".
• hydrochloric acid (HC1) is used as chemical etching agent, appropriately supplied into the reaction environment together with the silicon-source gas, for instance constituted by dichlorosilane (DCS - SiH 2 Cl 2 ) ; the role of hydrochloric acid (HC1) is, as has been said previously, that of modulating the rate of epitaxial growth appropriately.
• a gas carrier which enables modulation of the partial pressure of the reagent species and also participates in the overall reaction of epitaxial growth; by way of example, molecular hydrogen (H 2 ) can be used as gas carrier.
• an appropriate doping agent such as to enable a desired dopant profile of the enriched region 12 to be obtained.
• an appropriate flow of phosphorus or arsenic is used to obtain a doping of an N type.
• diborane B 2 H 6
• the competitive behaviour of the etching agent (in the example, HC1) and of the growth agent (in the example, DCS) is appropriately exploited so as to modulate the shape of the material grown within the trench 8 and prevent formation of defects (in particular, residual voids ) .
• the filling step for epitaxial growth comprises one or more sub-steps, each of which is characterized by an appropriate competitive action between etching and epitaxial growth, determined by a corresponding ratio between the flow of HC1 and the flow of DCS supplied in the reaction environment (" ⁇ HCI ⁇ DCS ratio) .
• ⁇ HCI ⁇ DCS ratio a ratio between the flow of HC1 and the flow of DCS supplied in the reaction environment
• the process evolves in growth regime, i.e., with a predominance of . the epitaxial growth of material over etching of the material grown (and possibly pre-existing) .
• growth regime i.e., with a predominance of . the epitaxial growth of material over etching of the material grown (and possibly pre-existing) .
• the partial-filling layer made of monocrystalline epitaxial silicon thus obtained coats the bottom 8" and the side walls 8' of the trench 8 and forms the enriched region 12.
• the flows of dopant within the growth chamber are regulated in such a way that the ratio between the flow of dopant ⁇ 0 and the flow of HC1 ⁇ ⁇ ⁇ (i.e., the ratio between the flows of the dopant species and of the etching agent) will remain constant during the entire process of epitaxial growth, notwithstanding the variation of the HCI /* DCS ratio, for the reasons described previously of modulation of the epitaxial growth.
• the flow of dopant is accordingly varied and regulated as a function the flow of HC1.
• it is, however, possible to obtain different doping profiles according to the specific implementation requirements by appropriately varying the flow of the dopant species within the reaction environment during the process of filling of the deep trenches 4.
• the trench 8 is only partially filled with the enriched region 12. This is even more true with reference to the embodiment of Figure 3, where the trench 8 does not present a layer of partial filling and the enriched region 12 is formed by means of implantation. Irrespective of whether the embodiment of Figure 3 or that of Figure 4 is adopted, after formation of the enriched region 12, the trench 8 is completely filled by dielectric material (dielectric filling region 20 in Figure 5a) .
• the dielectric filling region 20 is formed by means of a step of deposition (for example by CVD - Chemical Vapour Deposition) of dielectric material such as silicon oxide or silicon nitride.
• the dielectric filling region 20 is formed by thermal growth of dielectric material (in particular, silicon oxide - S1O2) , or using some other appropriate technique.
• dielectric material in particular, silicon oxide - S1O2
• Figure 5b shows the wafer 1 of Figure 5a in top plan view.
• the wafer 1 has, in this embodiment, a structure made up of strips .
• the process of filling of the trench 8 terminates with a possible step of surface planarization (CMP - Chemical Mechanical Planarization) in order to remove portions of dielectric that have formed on top of the protective layer 7 (in particular, this occurs when the dielectric filling region 20 is formed by means of deposition) .
• the protective layer 7 has, during this planarization step, the function of planarization-stopping layer.
• machines commonly used for CMP are provided with sensors for monitoring the progression of the planarization step, and recognizing when a layer of a certain material (here, SiN) has been reached, automatically interrupting the CMP process.
• the planarization is carried out by dry plasma etching (for example, using a plasma with a base of Ar, CF 4 , CHF 3 and CO) .
• the protective layer 7 is used as etch-stopping layer.
• the protective layer 7 consequently remains on top of the front side 3a of the epitaxial layer 3 at the end of the planarization process.
• the protective layer 7 is then removed ( Figure 6) by means of an etch of a wet type, using an appropriate etching chemistry. There is then obtained a wafer 1, the top surface of which is the front side 3a of the epitaxial layer 3.
• a semiconductor device for instance a semiconductor device such as a vertical-channel MOSFET.
• a thin gate dielectric layer 22 is formed, having, for example, a thickness of between 10 nm and 150 nm.
• the gate dielectric layer 22 can be formed via thermal oxidation, or else via deposition of an oxynitride layer or of a multilayer constituted by the superposition of successive layers of oxide and nitride.
• a polysilicon layer 24 is deposited for a thickness comprised between 100 nm and 700 nm.
• the polysilicon layer 24 may be intrinsic and doped subsequently by ion implantation, or, possibly, already doped in the deposition step.
• a gate mask 26 is then provided ( Figure 8), which protects the wafer 1 around the enriched region 12 and in the proximity of the field-oxide regions (not shown) and has body windows 27 alongside the enriched region 12.
• the polysilicon layer 24 and the gate dielectric layer 22 are shaped using the gate mask 26 to form at least one first gate electrode 29 and second gate electrodes 31.
• the gate electrode 29, which comprises a portion 24' of the polysilicon layer 24, is set on the enriched region 12 and the dielectric filling region 20 and extends laterally for a stretch on both sides of the enriched region 12.
• the gate electrode 29 is electrically insulated from the underlying layers by means of the portion 22' of the gate dielectric layer 22 extending between the gate electrode 29 itself and the front side 3a of the epitaxial layer 3.
• Further gate electrodes 31 are located at the edges of the active area 4 and in part overlying the field-oxide regions .
• a body implantation followed by a first process of thermal diffusion, to obtain at least a first body region 32 and a second body region 34, both of a P type.
• the first body region 32 and the second body region 34 extend partially also underneath the first gate electrode 29 and the second gate electrodes 31.
• the first and second body regions 32, 34 extend in the proximity of the enriched region 12.
• the body regions 32, 34 extend in the epitaxial layer 3 for a depth equal to, or smaller than, the depth at which the enriched region 12 extends.
• the overall depth, in the epitaxial layer 3, of the trench structure 8 provided with the enriched region 12 is approximately smaller than or equal to the depth in the epitaxial layer 3 to which the first and second body regions 32, 34 extend.
• the body regions 32, 34 are electrically coupled together in a known way, by means of a connection here not shown.
• the gate mask 26 is removed, and a source mask 35 is provided, as shown in Figure 10a.
• the source mask 35 has a first window 36a, above the first body region 32 and aligned respectively to the region of the first gate electrode 29 and to the region of the second gate electrode 31 that coats part of the first body region 32.
• the source mask 35 has two second windows 36b, 36c that leave respective portions of the second body region 34 exposed, and is aligned, respectively, to the portion of the first gate electrode 29 and of the second gate electrode 31 that covers part of the second body region 34.
• FIG. 10b shows the wafer 1 of Figure 10a in top plan view, in which there may be noted the structure made up of strips of the regions formed according to the steps so far described (for greater clarity the mask 35 is here not shown) .
• the body regions 32, 34, and source regions 38, 39 extend substantially parallel to one another to form respective strips.
• the dielectric filling region 20 extends between the body regions 32, 34 right through them.
• the source mask 35 is removed, and an insulating layer 42 is deposited.
• the insulating layer 42 is made, for example, of silicon oxide, with a thickness such as to incorporate the first gate electrode 29 and the second gate electrodes 31.
• the insulating layer 42 and the gate dielectric layer 22 are etched to obtain source windows 44, which expose partially the first source, region 38 and the second source regions 39, as well as part of the second body region 34.
• first and second gate-insulation structures 46, 47 designed to protect and insulate electrically the first gate electrode 29 and, respectively, the second gate electrodes 31.
• a VDMOS transistor 100 is thus obtained, the structure of which is shown in Figure 13.
• the VDMOS transistor 100 includes a parasitic JFET, defined by the enriched region 12 and by the body regions 32, 34.
• a current I JFET flows from the source regions 38, 39 to the substrate 2, which forms a drain terminal (not shown in Figure 13 is a drain metallization that is, however, present) .
• the current I JFET traverses channel regions (defined by surface portions of the body regions 32, 34), the enriched region 12 and part of the epitaxial layer 3.
• the parasitic JFET hence conducts. Its resistance, however, is low because the enriched region 12, which is heavily doped, has a high conductivity and, moreover, is affected only to a negligible extent by the effect of modulation of the body regions 32, 34.
• the enriched region 12 is substantially decoupled from the first gate electrode 29, since the coupling regions are limited in extension.
• the presence of the dielectric filling region 20 enables an increase of the final thickness of the gate dielectric (which hence extends not only on top of the epitaxial layer 3, but also within the latter) and consequently enables reduction of the capacitance associated thereto.
• Said capacitance determines the rate of switching of the VDMOS transistor 100 in so far as to be able to turn on or turn off the VDMOS transistor 100 it is necessary to charge or discharge said capacitance.
• a capacitance of a reduced value enables higher switching speeds to be achieved.
• the structure of the VDMOS transistor 100 according to the present invention enables abatement of the resistance of the parasitic JFET without sacrificing either the dimensions or the dynamic performance.
• a VDMOS transistor 150 comprises a gate-dielectric structure 55 having a double thickness. Elements of the VDMOS transistor 150 that are similar to corresponding elements of the VDMOS transistor 100 of Figure 13 are designated by the same reference numbers and are not described any further herein.
• the gate-dielectric structure 55 comprises a thin portion formed by the portion 22' of the gate dielectric layer 22, which extends between the first source region 38 and the second source region 39 that is closer to the enriched region 12, and a thick dielectric gate region 57, which is set substantially on top of the dielectric filling region 20. In general, the thick dielectric gate region 57 is set between the two body wells 32 and 34 without overlying them.
• the gate- dielectric structure 55 hence has a differentiated thickness: a first part, which is thinner with a thickness of between 10 nm and 150 nm, has the thickness of just the gate dielectric layer 22, whereas a second part, set between the first body region 32 and the second body region 34, in particular on top of the dielectric filling region 20, comprises also the thick dielectric gate region 57 and has a greater thickness, between 20 nm and 2 ⁇ .
• the first gate electrode 29 has a differentiated thickness, in a way complementary to the gate-dielectric structure 55: the first gate electrode 29 has, in fact, a greater thickness where the gate-dielectric structure 55 is thinner and, vice versa, a smaller thickness where the gate-dielectric structure 55 is thicker.
• Figure 15 shows, by way of example, a power MOSFET device, designated by 180, provided according to the present invention .
• the power MOSFET device 180 of a planar type, has a structure made up of periodic strips (of the type shown in Figure 10b) given by the repetition of a plurality of elementary transistors (i.e., a plurality of VDMOS transistors 100 formed alongside one another on one and the same wafer 1), each of which is provided according to the teaching of the present invention.
• the power MOSFET device 180 is provided in the wafer 1, including the substrate 2 and the epitaxial layer 3.
• the power MOSFET device 180 hence comprises: a plurality of body regions (or wells) 182 (similar to the body wells 32, 34 described previously) , with a doping of a P type and set at the top surface 3a of the epitaxial layer 3; source regions 184 (similar to the source regions 38, 39 described previously) , with a doping of an N type, set within the body region 182; and an insulated-gate structure 186 (similar to the gate structure 29 described previously) , in turn formed by the superposition of a silicon-oxide region and of a conductive region, for instance made of polysilicon, set at least partially on top of a source region 184 and extending between two adjacent body regions 182 of the power MOSFET device 180.
• an enriched region 187 is present (similar to the enriched region 12 described previously) , of an N+ type, extending in the epitaxial layer 3, facing the top surface 3a.
• the enriched region 187 surrounds completely a dielectric filling region 189 (similar to the dielectric filling region 20), extending in the epitaxial layer 3, facing the top surface 3a.
• The. gate structure 186 extends over the enriched region 187 and over the dielectric filling region 189.
• a passivation layer 190 and a metallization layer 191 are set, in a way in itself known, on top of the top surface 3a of the epitaxial layer 3 and of the insulated-gate structures 186.
• FIG 16 is a schematic illustration a user system 300 that comprises a user apparatus 301 and a control device 302 coupled thereto for supplying control signals S c .
• the control device 302 comprises a circuit equipped with one or more examples of the VD OS transistor 100 of Figure 13 (or, alternatively, of the VDMOS transistor 150 of Figure 14) .
• the user system 300 and the user apparatus 301 can be,, for instance, a DC-DC converter system with a resistive or inductive load or a motor control system with an inductive load.
• the present invention enables significant abatement of the contribution of the parasitic JFET inherent in vertical-conduction MISFET structures without increasing the capacitance associated to the gate structure, and consequently improvement of the compromise between on- resistance (the so-called "RON") and gate charge of the electronic device.
• the structure with dielectric gate having a double thickness presents the advantage of enabling a further reduction in the output capacitance of the electronic device, to the advantage of the speed of response in use, thus improving the levels of dynamic performance of the device.
• the dielectric that forms the dielectric region 20 can be of any type; in particular, it can be a dielectric different from the one used to form the dielectric gate 22' .
• the process can be used to obtain MISFET devices different from VDMOS transistors.
• IGBTs multi-drain devices, or superjunction devices.
• the structure comprising the enriched region and the dielectric region internal to the enriched region is present between all the body wells of said devices.

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• 2012
  • 2012-02-28 WO PCT/IT2012/000060 patent/WO2013128480A1/fr not_active Ceased

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