WO2013129805A1 - Sous-substrat de fixation pour dispositif électroluminescent semi-conducteurs et procédé de fabrication dudit dispositif électroluminescent semi-conducteur utilisant ledit sous-substrat - Google Patents

Sous-substrat de fixation pour dispositif électroluminescent semi-conducteurs et procédé de fabrication dudit dispositif électroluminescent semi-conducteur utilisant ledit sous-substrat Download PDF

Info

Publication number
WO2013129805A1
WO2013129805A1 PCT/KR2013/001436 KR2013001436W WO2013129805A1 WO 2013129805 A1 WO2013129805 A1 WO 2013129805A1 KR 2013001436 W KR2013001436 W KR 2013001436W WO 2013129805 A1 WO2013129805 A1 WO 2013129805A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor
substrate
emitting device
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2013/001436
Other languages
English (en)
Korean (ko)
Inventor
오병두
신현우
구교선
이우식
정웅락
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hanbeam Co Ltd
Original Assignee
Hanbeam Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hanbeam Co Ltd filed Critical Hanbeam Co Ltd
Publication of WO2013129805A1 publication Critical patent/WO2013129805A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/019—Removal of at least a part of a substrate on which semiconductor layers have been formed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies

Definitions

  • the present invention relates to a submount substrate for a semiconductor light emitting device and a method of manufacturing a semiconductor light emitting device using the same, and more particularly, to a submount substrate for a semiconductor light emitting device providing a submount substrate having a multi-layer structure provided with a stress release layer and the same. It relates to a method for manufacturing a semiconductor device used.
  • LEDs light emitting diodes
  • LEDs which transmit and receive signals by converting electricity into infrared rays or light using characteristics of compound semiconductors, or are used as light sources
  • LEDs light emitting diodes
  • It can be used to emit light of a desired wavelength with little power and to suppress the emission of environmentally harmful substances such as mercury, and the development is being accelerated in consideration of energy saving and environmental protection aspects.
  • Such light emitting diodes may be classified into a horizontal type and a vertical type according to a difference in current flow direction and structure.
  • horizontal light emitting diodes are widely used for low power or medium power, and have recently been attempted for high power, but have not made progress in mass production due to serious thermal problems.
  • the vertical light emitting diode has the most suitable structure for high power and maximizes heat dissipation characteristics.
  • a vertical high-performance semiconductor light emitting device using a semiconductor multilayer light emitting structure on a sapphire substrate having a substantially different lattice constant and thermal expansion coefficient Is making In general, in view of current technology, economy, and performance, a vertical high-performance semiconductor light emitting device using a semiconductor multilayer light emitting structure on a sapphire substrate having a substantially different lattice constant and thermal expansion coefficient Is making.
  • the sapphire substrate has a disadvantage that it is difficult to apply a large current to the light emitting device because it is hard and has poor thermal conductivity, and it is difficult to cope with static electricity flowing from the outside because it is an electrically non-conductive material, which may cause defects due to static electricity. There is this big problem.
  • the semiconductor light emitting structure is safely lifted off from the sapphire substrate through a laser lift off process, and high performance using the same.
  • Many efforts have been made to manufacture vertical light emitting diodes.
  • the semiconductor light emitting structure thin film has a different lattice constant and thermal expansion. It can be seen that due to the coefficient, the semiconductor single crystal thin film exhibits many damages and breakages after being separated from the sapphire substrate because it cannot withstand the mechanical stress generated between the nitride semiconductor thin film and the thick sapphire substrate.
  • a wafer bonding or electroplating process is introduced before the sapphire substrate is separated from the light emitting structure to form a structurally stable and strongly adhered thermally conductive support substrate.
  • the support substrate used in the semiconductor light emitting device has a large difference in the coefficient of thermal expansion with the sapphire substrate, when the support substrate is bonded by the sapphire substrate and the wafer bonding, physical stresses such as stresses due to different lattice constants and coefficients of thermal expansion are different. Low wafer bending and fine micro-cracks are generated inside the semiconductor light emitting structure, and in severe cases, the sapphire substrate is broken, resulting in low performance due to degradation of the fabricated semiconductor light emitting device. Product yield is a problem.
  • the support substrate in the process of cooling to room temperature after the bonding at a high temperature because the thermal expansion coefficient of the support substrate is much smaller than the thermal expansion coefficient of the sapphire substrate While the shrinkage is small, the sapphire substrate is contracted a lot and a large tensile force is applied to the sapphire substrate. As a result, warpage of the intermediate product bonded to the support substrate and the sapphire substrate occurs. When this phenomenon occurs, the optical alignment that applies a uniform laser force during the removal of the sapphire substrate by the laser lift-off process is difficult. Subsequent processes such as the lift-off process and subsequent photo process and N-electrode formation process may be impossible.
  • an efficient support substrate and a high performance vertical light emitting device manufacturing process using the same must be considered in consideration of wafer warpage and cracking, micro crack generation, and low product yield. Should be developed.
  • the present invention provides a sub-mount substrate for a semiconductor light emitting device and a method of manufacturing a semiconductor light emitting device using the same, which can produce high performance and high reliability semiconductor light emitting devices by preventing problems caused by different lattice constants and thermal expansion coefficient differences.
  • the purpose is.
  • Another object of the present invention is to provide a submount substrate for a semiconductor light emitting device capable of manufacturing a light emitting device having high reliability without any thermal or mechanical damage, and a method of manufacturing the semiconductor light emitting device using the same.
  • the submount substrate for semiconductor light emitting device of the present invention comprises a temporary support substrate layer; A sacrificial layer formed on an upper surface of the temporary support substrate layer; A support substrate layer formed on the sacrificial layer; A bonding layer for a submount substrate formed on the support substrate layer; And a stress release layer formed on the lower surface of the temporary support substrate layer.
  • the temporary support substrate layer is at least among stainless steel, Cu, Al 2 O 3 , SiC, Si, Ge, SiGe, GaAs, GaP, ZnO, GaN, AlGaN, AlN, InP, graphite and metal-graphite composites. Including any one,
  • the sacrificial layer is made of at least one material of Al 2 O 3 , AlN, MgO, AlSiC, BN, BeO, TiO 2 , SiO 2 and PR (Photoresist),
  • the support substrate layer is formed of a single layer or a laminated structure, consisting of an electrolytic plating layer or an electroless plating layer containing any one of Ni, Cu, Ag, Au and Al,
  • the bonding layer for the submount substrate is Al-Si, Ag-Cd, Au-Sb, Al-Zn, Al-Mg, Al-Ge, Pd-Pb, Ag-Sb, Au-In, Al-Cu-Si, Ag-Cd-Cu, Cu-Sb, Cd-Cu, Au-Sn, Ag-Sn, Au-Sn-Ni, Ag-Sn-Ni, Al-Si-Cu, Ag-Cu, Ag-Zn, Ag- Cu-Zn, Ag-Cd-Cu-Zn, Au-Si, Au-Ge, Au-Ni, Au-Cu, Au-Ag-Cu, Cu-Cu 2 O, Cu-Zn, Cu-P, Ni- At least one of B, Ni-Mn-Pd, Ni-P, and Pd-Ni,
  • a stress release layer is formed on the lower surface of the temporary support substrate layer
  • the stress release layer is formed of a single layer or a laminated structure
  • the stress release layer is Ag, Al, Rh, Pt, Au, Cu, Ni, Pd, metallic silicide, Ag-based alloy, Al-based alloy, Rh-based alloy, carbon nanotube networks (CNTNs), transparent conductive oxide Transparent conductive nitride, including Ti, W, Cr, Ni, Pt, NiCr, TiW, CuW, Ta, TiN, CrN and TiWN,
  • the stress release layer has a thickness of 10 ⁇ m to 2000 ⁇ m
  • a stress release seed layer is formed between the temporary support substrate layer and the stress release layer.
  • the present invention comprises the steps of (a) providing a submount substrate in which a stress release layer, a temporary support substrate layer, a sacrificial layer, a support substrate layer and a bonding layer for a submount substrate are sequentially stacked;
  • An epitaxial structure including a semiconductor stack structure in which an N-semiconductor layer, an active layer, a P-semiconductor layer, and a P-electrode is laminated on the growth substrate layer and a growth layer bonding layer formed on the semiconductor stack structure are provided.
  • step (B) doing; (C) bonding the growth substrate bonding layer and the submount substrate bonding layer; (D) separating the growth substrate layer bonded to the submount substrate from the semiconductor stack structure; (E) forming an N-electrode on the N-semiconductor layer of the semiconductor stacked structure exposed while the growth substrate layer is separated; Performing a dicing process in a vertical direction from the N-electrode formation direction to cut the resultant of the step (e); And (g) separating the temporary support substrate layer while removing the sacrificial layer portion of the submount substrate as a result of the step (f).
  • the step (b) of preparing the epitaxial structure may include depositing an N-semiconductor layer material, an active layer material, a P-semiconductor layer material, and a material for a P-electrode on the growth substrate layer in sequence; N-semiconductor layer, active layer, P-semiconductor layer and P on the growth substrate layer by performing an ISO (Isolation) etching process on the P-electrode material, P-semiconductor layer material, active layer material and N-semiconductor layer material Forming a plurality of semiconductor laminate structures consisting of a stack of electrodes spaced apart from each other; Forming a protective film on a surface of the growth substrate layer including side surfaces of the plurality of semiconductor stacked structures; Forming a barrier film on an entire surface of the growth substrate layer so that the semiconductor stacked structure in which the protective film is formed is buried; And forming a growth layer bonding layer on the barrier film.
  • the step (b) of preparing the epitaxial structure includes sequentially depositing an N-semiconductor layer material, an active layer material, a P-semiconductor layer material, and a material for a P-electrode on the growth substrate layer; Patterning the material for the P-electrode to form a semiconductor laminate structure comprising a stack of N-semiconductor layer material, active layer material, P-semiconductor layer material and patterned P-electrode material on the growth substrate layer; Forming a barrier film on an entire surface of the growth substrate layer so as to embed the semiconductor stacked structure including the patterned P-electrode material; And forming a growth layer bonding layer on the barrier film.
  • the temporary support substrate layer is at least one of stainless steel, Cu, Al 2 O 3 , SiC, Si, Ge, SiGe, GaAs, GaP, ZnO, GaN, AlGaN, AlN, InP, graphite, and metal-graphite composites. Including,
  • the sacrificial layer is formed of at least one of Al 2 O 3 , AlN, MgO, AlSiC, BN, BeO, TiO 2 , SiO 2 and PR (Photoresist),
  • the support substrate layer is formed of a single layer or a laminated structure, and formed of an electrolytic plating layer or an electroless plating layer containing any one of Ni, Cu, Ag, Au, and Al,
  • step (a) Forming a seed layer between the sacrificial layer and the supporting substrate layer in step (a);
  • (A) providing a submount substrate having a laminated structure of the temporary support substrate layer, the sacrificial layer, the support substrate layer, and the bonding layer for the submount substrate may include forming a stress release layer on a lower surface of the temporary support substrate layer.
  • the stress release layer is formed of a single layer or a laminated structure
  • the stress release layer is Ag, Al, Rh, Pt, Au, Cu, Ni, Pd, metallic silicide, Ag-based alloy, Al-based alloy, Rh-based alloy, carbon nanotube networks (CNTNs), transparent conductive oxide Transparent conductive nitride, including Ti, W, Cr, Ni, Pt, NiCr, TiW, CuW, Ta, TiN, CrN and TiWN,
  • the stress release layer is formed to a thickness of 10 ⁇ m 2000 ⁇ m,
  • the step (f) may include cutting the semiconductor layered structure into a single chip structure by cutting at least until the surface of the sacrificial layer of the submount substrate is exposed.
  • the semiconductor laminate structure may be formed into a modular structure by cutting the first and second depths having different depths.
  • It includes a semiconductor light emitting device manufactured by any one of the above-described methods.
  • the present invention relates to a submount substrate for a semiconductor light emitting device and a method of manufacturing a semiconductor light emitting device using the same.
  • the present invention provides a multi-mount submount substrate having a stress release layer, which is generated due to different lattice constants and thermal expansion coefficients. It can cancel the stress of the compressive stress and the tensile stress can solve the mechanical stress. Therefore, it is possible to prevent the occurrence of micro cracks and cracks of the nitride semiconductor, thereby facilitating the prevention of product damage and the process, thereby providing a vertical semiconductor light emitting device of high quality and high performance.
  • the present invention can bring a stable process when manufacturing a light emitting device, it is possible to proceed freely to the subsequent process, as a result it is possible to obtain a high reliability light emitting device without any thermal and mechanical damage.
  • FIG. 1 is a cross-sectional view showing a submount substrate for a semiconductor light emitting device according to an embodiment of the present invention.
  • FIGS. 2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor light emitting device using the submount substrate for semiconductor light emitting device according to the embodiment of the present invention.
  • FIG 3 is a cross-sectional view illustrating another dicing process according to an embodiment of the present invention.
  • FIG. 4 is a cross-sectional view illustrating a submount substrate for a semiconductor light emitting device according to another exemplary embodiment of the present invention.
  • 5A and 5B illustrate an example in which a stress lily layer is applied to a submount substrate according to another embodiment of the present invention.
  • FIG. 6 is a view illustrating a manufacturing process of a semiconductor light emitting device using the submount substrate for semiconductor light emitting device provided with the stress release layer according to another embodiment of the present invention.
  • FIGS. 7A to 7G are cross-sectional views illustrating a method of manufacturing a semiconductor light emitting device using a submount substrate for semiconductor light emitting devices according to another embodiment of the present invention.
  • FIG. 8 is a sectional view for explaining another dicing process according to another embodiment of the present invention.
  • FIG. 1 is a cross-sectional view illustrating a submount substrate for a semiconductor light emitting device according to an exemplary embodiment of the present invention.
  • the submount substrate 100 for a semiconductor light emitting device may include a temporary support substrate layer 101, a sacrificial layer 102, a support substrate layer 104, and a bonding layer for a submount substrate. layer 105).
  • the semiconductor light emitting device submount substrate 100 includes a selected temporary support substrate layer 101, and a sacrificial layer 102 is formed on the temporary support substrate layer 101 by lamination.
  • the support substrate layer 104 is formed on the layer 103 by lamination, and the support substrate layer further includes a seed layer 103 interposed between the sacrificial layer 102 and the support substrate layer 104.
  • 104 is formed, and the support substrate layer 104 is formed of a multi-layer laminated structure in which a bonding layer 105 for a submount substrate is formed in a stack.
  • the temporary support substrate layer 101 serves to provide mechanical stability in a subsequent process, and is separated together with the sacrificial layer 102 in a subsequent process.
  • the temporary support substrate layer 102 is made of stainless steel, Cu, Al 2 O 3 , SiC, Si, Ge, SiGe, GaAs, GaP, ZnO, GaN, AlGaN, AlN, InP, graphite having excellent thermal and electrical conductivity. Graphite) and metal-graphite composites.
  • the sacrificial layer 102 is made of a material that is easily dissolved in a wet etching solution in a subsequent process, and preferably, Al 2 O 3 , AlN, MgO, AlSiC, BN, BeO, TiO 2 , SiO 2, and PR (Photoresist). ) At least one of the materials.
  • the support substrate layer 104 having the seed layer 103 is used as a final support substrate that effectively induces heat emission of a semiconductor light emitting device, and includes any one of Cu, Ag, Au, and Al having excellent electrical conductivity. It consists of an electrolytic plating layer or an electroless plating layer.
  • the bonding layer 105 for the submount substrate is a material layer for bonding the submount substrate to the semiconductor light emitting device, and includes Al-Si, Ag-Cd, Au-Sb, Al-Zn, Al-Mg, and Al-Ge.
  • the semiconductor light emitting device submount substrate is formed in a form having a temporary support substrate layer on a lower surface thereof, thereby securing a submount substrate having a thick thickness due to the temporary support substrate layer. It is possible to achieve mechanical stability than a submount substrate having a thickness, thereby preventing breakage during the process, thereby ensuring the stability and reliability of the manufacturing process.
  • a substructure formed of a laminated structure of a temporary support substrate layer, a sacrificial layer, a support substrate layer and a bonding layer for a submount substrate Step (a) of preparing a mount substrate, a semiconductor laminate structure formed by laminating an N-semiconductor layer, an active layer, a P-semiconductor layer and a P-electrode on the growth substrate layer, and a growth substrate formed by being stacked on the semiconductor laminate structure (B) preparing an epitaxial structure including a bonding layer, bonding (c) bonding the growth substrate bonding layer and the submount substrate bonding layer, and the epimount bonded to the submount substrate.
  • FIGS. 2A to 2G a method of manufacturing a semiconductor light emitting device using a submount substrate for semiconductor light emitting devices according to an embodiment of the present invention will be described.
  • the temporary support substrate layer 101 may be formed of a material having excellent heat conduction characteristics and ductility.
  • the sacrificial layer 102 and the support substrate layer 104 are sequentially formed on the temporary support substrate layer 101.
  • the seed layer 103 is further formed on the sacrificial layer 102 to improve the characteristics of the thin film.
  • a process of forming a bonding layer 105 for a submount substrate, which serves as an adhesive layer in a subsequent bonding process is performed on the support substrate layer 104, thereby sacrificing the temporary support substrate layer 101.
  • a submount substrate 100 having a stacked structure of a layer 102, a support substrate layer 104 provided with the seed layer 103, and a bonding layer 105 for a submount substrate is prepared.
  • the temporary support substrate layer 101 serves to provide mechanical stability in a subsequent process, and is separated together with the sacrificial layer 102 in a subsequent process.
  • the temporary support substrate layer 102 is made of stainless steel, Cu, Al 2 O 3 , SiC, Si, Ge, SiGe, GaAs, GaP, ZnO, GaN, AlGaN, AlN, InP, graphite having excellent thermal and electrical conductivity.
  • Graphite) and the metal-graphite composite are formed of a material layer including at least one.
  • the submount substrate 100 is formed in a multi-layered stack structure having a temporary support substrate layer 101 on a lower surface thereof, thereby securing a submount substrate having a thick thickness due to the temporary support substrate layer 101. Therefore, the subsequent steps can be sequentially carried out mechanically more stably than the submount substrate having a thin thickness, thereby preventing breakage during the process, and thus, the stability and reliability of the manufacturing process can be ensured.
  • the sacrificial layer 102 is made of a material that is easily dissolved in a wet etching solution in order to perform the process smoothly without thermal or mechanical impact on the neighboring chips itself in a subsequent process, and preferably, Al 2 O 3 , AlN, It is formed of at least one material layer of MgO, AlSiC, BN, BeO, TiO 2 , SiO 2, and PR (Photoresist).
  • the support substrate layer 104 is a final support substrate that effectively induces heat emission of the semiconductor light emitting device, and serves as a support layer and an electrode of the semiconductor light emitting device, and has any one of Cu, Ag, Au, and Al having excellent electrical conductivity. It is formed in a single layer or a laminated structure using an electrolytic plating layer or an electroless plating layer comprising a.
  • the bonding layer 105 for the submount substrate is an adhesive layer for attaching by a subsequent eutectic bonding method, Al-Si, Ag-Cd, Au-Sb, Al-Zn, Al-Mg, Al-Ge, Pd- Pb, Ag-Sb, Au-In, Al-Cu-Si, Ag-Cd-Cu, Cu-Sb, Cd-Cu, Au-Sn, Ag-Sn, Au-Sn-Ni, Ag-Sn-Ni, Al-Si-Cu, Ag-Cu, Ag-Zn, Ag-Cu-Zn, Ag-Cd-Cu-Zn, Au-Si, Au-Ge, Au-Ni, Au-Cu, Au-Ag-Cu, Cu-Cu 2 O, Cu-Zn, Cu-P, Ni-B, Ni-Mn-Pd, Ni-P and Pd-Ni formed of a material layer containing at least any one, and bonding with other layers In order to facilitate this, a seed layer (not shown)
  • a growth substrate layer 111 made of transparent sapphire is prepared, and the growth is performed.
  • An N-semiconductor layer material composed of an n-type gallium nitride system, an active layer material having a multi-well structure, and a P-semiconductor layer material composed of a p-type gallium nitride system are sequentially deposited on the substrate layer 111, and on the P-semiconductor layer material
  • the material for the P-electrode may be simultaneously deposited to serve as an electrode and a reflective film.
  • an ISO (Isolation) etching process is performed on the P-electrode material, the P-semiconductor layer material, the active layer material, and the N-semiconductor layer material to form an N-semiconductor layer 112a on the growth substrate layer 111.
  • a plurality of semiconductor stack structures 112 formed of a stack of an active layer 112b, a P-semiconductor layer 112c, and a P-electrode 112d are formed.
  • the semiconductor laminate structure 112 is formed in plural in a shape spaced apart from each other on the growth substrate layer 111 by the ISO etching process.
  • a passivation layer 113 is formed on a surface of the growth substrate layer 111 including the side surfaces of the plurality of semiconductor stacked structures 112 to absorb or block harmful ions.
  • a barrier layer 114 is formed on the entire surface of the growth substrate layer 111 so that the formed semiconductor stack structure 112 is buried.
  • a growth substrate bonding layer 115 is formed on the barrier layer 114 to attach the submount substrate 100 and the epitaxial structure 110 by eutectic bonding.
  • the growth substrate bonding layer 115 is Al-Si, Ag-Cd, Au-Sb, Al-Zn, Al-Mg, Al-Ge, Pd-Pb, Ag-Sb, Au-In, Al-Cu- Si, Ag-Cd-Cu, Cu-Sb, Cd-Cu, Au-Sn, Ag-Sn, Au-Sn-Ni, Ag-Sn-Ni, Al-Si-Cu, Ag-Cu, Ag-Zn, Ag-Cu-Zn, Ag-Cd-Cu-Zn, Au-Si, Au-Ge, Au-Ni, Au-Cu, Au-Ag-Cu, Cu-Cu 2 O, Cu-Zn, Cu-P, Ni-B, Ni-Mn-Pd, Ni-P and Pd-Ni formed of a material layer containing at least any one, where
  • the manufacturing process of preparing the epitaxial structure 110 which is the step (b) in the present embodiment, as described above, the N-semiconductor layer material, the active layer material, the P-semiconductor layer material and the P- A process of forming a plurality of semiconductor stacked structures 112 spaced apart from each other by sequentially stacking materials for electrodes and performing an ISO etching process on the stacked materials is described above.
  • the N-semiconductor layer material, the active layer material, the P-semiconductor layer material and the material for the P-electrode are sequentially deposited, and then the material for the P-electrode selectively. Only by performing the patterning process can proceed.
  • the step of preparing the epitaxial structure of the step (b) process first, an N-semiconductor layer material, multi-well consisting of n-type gallium nitride based on the growth substrate layer Sequentially depositing an active layer material having a structure, a P-semiconductor layer material composed of a p-type gallium nitride system, and a material for a P-electrode capable of simultaneously serving as an electrode and a reflective film, by patterning the material for the P-electrode Forming a semiconductor laminate structure consisting of a stack of N-semiconductor layer material, active layer material, P-semiconductor layer material and patterned P-electrode material on a growth substrate layer, comprising the patterned P-electrode material Forming a barrier film on the entire growth substrate layer so that the semiconductor laminate structure is embedded; and forming a bonding layer for the growth substrate on the barrier film.
  • bonding the growth substrate bonding layer 115 and the submount substrate bonding layer 105 in the step (c) may be performed by a thermo compressive method.
  • the epitaxial structure 110 and the submount substrate 100 are bonded by bonding the growth substrate bonding layer 115 and the submount substrate bonding layer 105 to each other.
  • bonding the growth substrate bonding layer 115 and the submount substrate bonding layer 105 is not limited to being performed by the heat-compression method, and electroplating using a plating crystal core layer. It can be done by the method.
  • the step of removing the growth substrate layer of the epitaxial structure 110 bonded to the submount substrate 100 in the step (d) from the semiconductor stack structure 112 may include laser lift-off.
  • a growth substrate layer is separated from the epitaxial structure 110 using a laser lift off technique.
  • a laser beam which is a strong energy source, is irradiated through the back side of the growth substrate layer, laser absorption is strongly generated at the interface between the semiconductor laminate structure and the growth substrate layer, thereby causing thermal chemical decomposition reaction of gallium nitride present at the interface.
  • the growth substrate layer made of transparent sapphire is lifted off.
  • the forming of the N-electrode 112e on the N-semiconductor layer 112a of the semiconductor stack structure exposed while the growth substrate layer is removed in the step (e) is performed by the growth.
  • the N-electrode material is etched to thermally stabilize the N-electrode on the N-semiconductor layer 112a.
  • a type semiconductor light emitting device electrode structure is formed.
  • the dicing process is performed in a vertical direction from the N-electrode 112e forming direction.
  • the semiconductor light emitting device electrode structure consisting of the electrode (112e) and the semiconductor layered structure 112 into a single chip structure formed between the semiconductor layered structure by mechanical cutting, grinding and chemical etching
  • laser removal method A dicing process is performed in which the substrate is cut only in the vertical direction with respect to the submount substrate including the epitaxial structure, and cuts up to the temporary support substrate layer 101.
  • a dicing process is performed to cut the submount substrate including the epitaxial structure until at least the sacrificial layer 102 surface, more preferably at least the top surface of the sacrificial layer is exposed.
  • the temporary support substrate layer formed on the lower surface of the sacrificial layer has an advantage of being recyclable.
  • the performing of the dicing process as the step (f) is described as described above with respect to a dicing process for manufacturing the resultant into a single chip structure.
  • the semiconductor light emitting device electrode structure including the N-electrode 112e and the semiconductor stacked structure 112 may be manufactured in a modular structure.
  • the first depth 191 has a depth shorter than the second depth 192, has a depth cut to at least an upper surface of the growth substrate bonding layer 115, and the second depth 192. At least said hee It is performed so as to have a cut depth to the upper surface of layer 102.
  • the sacrificial layer is dissolved using an acid, base, or salt solution determined according to the material used as the sacrificial layer in the substrate resulted by the dicing process, and the temporary support substrate layer is separated along the horizontal direction.
  • the temporary supporting substrate layer is separated and the supporting substrate 104 formed on the sacrificial layer preferably serves as a supporting layer and an electrode of the final semiconductor light emitting device, the electrical conductivity is reduced due to the supporting substrate layer 104. You get a support substrate that is good and has good heat transfer efficiency and easy productivity.
  • the temporary support substrate layer is separated from the submount substrate while being removed together with the sacrificial layer for heat dissipation of the light emitting device.
  • the temporary support substrate layer includes the temporary support substrate layer. Since it is possible to secure the thickness, this can bring about mechanical stability in a subsequent process than the submount substrate having a thin thickness to prevent breakage during the process, thereby securing the stability of the manufacturing process.
  • FIG. 4 is a cross-sectional view illustrating a submount substrate for a semiconductor light emitting device according to another embodiment of the present invention, wherein the difference in thermal expansion coefficient of the laminated thin films and the compressive stress and the tensile stress occurring during the subsequent process process are shown.
  • FIG. Represents a submount substrate in which a stress lily layer for canceling stress is further formed.
  • the submount substrate 700 includes a stress release layer 707, a temporary support substrate layer 701, and a sacrificial layer having a seed layer 706 for stress release thereon.
  • the layer 702, the support substrate layer 704 having the seed layer 703 thereon, and the bonding layer 705 for the submount substrate are formed in a multilayered laminated structure formed by lamination.
  • the stress release layer 707 is formed of a single layer or a laminated structure while arbitrarily adjusting the formation thickness to control the stress between the laminated structures, preferably, by adjusting the thickness arbitrarily in a thickness of 10 ⁇ m ⁇ 2000 ⁇ m It is formed in a single layer or laminated structure.
  • the stress release layer 707 may include Ag, Al, Rh, Pt, Au, Cu, Ni, Pd, metallic silicide, Ag-based alloy, Al-based alloy, Rh-based alloy, carbon nanotube networks (CNTNs), Transparent conductive oxide, transparent conductive nitride, Ti, W, Cr, Ni, Pt, NiCr, TiW, CuW, Ta, TiN, CrN and TiWN any one material.
  • the semiconductor light emitting device sub-mount substrate 700 is formed in a stacked structure including a stress relief layer 707 to cancel the stress, the semiconductor light emitting device electrode structure It is possible to prevent the phenomenon caused by the wafer warpage phenomenon and stress during the process of bonding or the process of separating the first growth substrate layer, it can provide a product damage prevention and ease of processing.
  • FIG. 5A and 5B illustrate an example in which a stress lilly layer is applied to the submount substrate.
  • the thin film may be interposed between the thin films.
  • the occurrence of stress causes the submount substrate 700 and the epitaxial structure 710 to bend, and as shown in FIG. 5B, when the submount substrate 700 is provided with a stress lily layer.
  • the stress release layer 707 it can be seen that the submount substrate 700 and the epitaxial structure 710 are stably formed without wafer warpage.
  • FIG. 6 is a view illustrating a process of fabricating a semiconductor light emitting device using the submount substrate for semiconductor light emitting device having the stress release layer.
  • the submount substrate for semiconductor light emitting device including the stress release layer is illustrated.
  • the process of manufacturing a semiconductor light emitting device using the step includes preparing a submount substrate having a stress release layer, preparing an epitaxial structure including a growth substrate layer, a semiconductor laminate structure, and a bonding layer for growth substrate, wherein The step of preparing the submount substrate and the step of preparing the epitaxial structure may be reversed.
  • the stress release layer is not formed during manufacturing of the submount substrate, and the submount substrate and the epitaxial structure are formed. After the bonding process step of wafer bonding, it may be formed in the next process.
  • a method of manufacturing a semiconductor light emitting device using the submount substrate for semiconductor light emitting device provided with the stress release layer will be described in detail with reference to FIGS. 7A to 7G.
  • a sacrificial layer 702 and a support substrate layer 704 are sequentially formed on a temporary support substrate layer 701 made of a material having excellent thermal conductivity and ductility.
  • the seed layer 703 is further formed on the sacrificial layer 702 to improve the characteristics of the thin film.
  • a bonding layer 705 for a submount substrate is formed on the supporting substrate layer 704 to serve as an adhesive layer in a subsequent bonding process, and then a seed layer for stress release is formed on the lower surface of the temporary supporting substrate layer 701.
  • the stress release layer 707 is formed to include the stress release layer 707, the temporary support substrate layer 701, the sacrificial layer 702, and the seed layer 703 provided with the stress release seed layer 706.
  • a submount substrate 700 having a laminated structure of one support substrate layer 704 and a submount substrate bonding layer 705 is prepared.
  • the stress release layer 707 is formed in a single layer or laminated structure while arbitrarily adjusting the formation thickness to control the stress between the laminated structures, preferably, the thickness is arbitrarily adjusted in the thickness range of 10 ⁇ m ⁇ 2000 ⁇ m To form a single layer or a laminated structure.
  • the stress release layer 707 may include Ag, Al, Rh, Pt, Au, Cu, Ni, Pd, metallic silicide, Ag-based alloy, Al-based alloy, Rh-based alloy, carbon nanotube networks (CNTNs), It is formed of at least one of transparent conductive oxide, transparent conductive nitride, Ti, W, Cr, Ni, Pt, NiCr, TiW, CuW, Ta, TiN, CrN and TiWN.
  • the temporary support substrate layer 701 serves to provide mechanical stability in a subsequent process, and is separated together with the sacrificial layer 702 in a subsequent process.
  • the temporary support substrate layer 701 is made of stainless steel, Cu, Al 2 O 3 , SiC, Si, Ge, SiGe, GaAs, GaP, ZnO, GaN, AlGaN, AlN, InP, graphite having excellent thermal and electrical conductivity.
  • Graphite) and a material layer including at least one of a complex of metal and graphite, and the sacrificial layer is easily immersed in a wet etching solution in order to perform the process smoothly without thermal or mechanical impact on neighboring chips itself in a subsequent process. It is composed of a material that dissolves, and preferably formed of at least one material layer of Al 2 O 3 , AlN, MgO, AlSiC, BN, BeO, TiO 2 and SiO 2 .
  • the support substrate layer 704 is a final support substrate that effectively induces heat emission of the semiconductor light emitting device, and serves as a support layer and an electrode of the semiconductor light emitting device, and has any one of Cu, Ag, Au, and Al having excellent electrical conductivity. It is formed in a single layer or a laminated structure using an electrolytic plating layer or an electroless plating layer comprising a.
  • the bonding layer 705 for the submount substrate is Al-Si, Ag-Cd, Au-Sb, Al-Zn, Al-Mg, Al-Ge, Pd- as an adhesive layer for attaching by a subsequent eutectic bonding method.
  • the stress release layer 707 reduces the stress that the stacked structures will receive during subsequent processing. As a result, it is possible to prevent the occurrence of micro cracks and cracks in the nitride-based semiconductor, thereby providing a high-quality and high-performance vertical semiconductor light emitting device.
  • the stress release layer 707 having the stress release seed layer 706 is not formed during the manufacturing process of providing the submount substrate, and the temporary support substrate 701 after the subsequent bonding process is performed. Can be formed on the lower surface. That is, in the manufacturing process of providing a submount substrate according to the method of manufacturing a semiconductor light emitting device, the supporting substrate layer 704 including the temporary supporting substrate layer 701, the sacrificial layer 702, and the seed layer 703 is provided. And providing a submount substrate having only a laminated structure of the bonding layer 705 for the submount substrate and not provided with the stress release layer, and then using a submount substrate without the stress release layer.
  • a subsequent bonding process of the submount substrate is performed, and a stress release layer 707 having a stress release seed layer 706 on the lower surface of the temporary support substrate layer of the submount substrate is performed in a subsequent process. Can be formed.
  • a growth substrate layer 711 formed of transparent sapphire is prepared, and an N-semiconductor layer material composed of n-type gallium nitride based on the growth substrate layer 711, an active layer having a multi-well structure.
  • a material and a P-semiconductor layer material composed of a p-type gallium nitride system are sequentially deposited, and a material for a P-electrode capable of simultaneously serving as an electrode and a reflective film is deposited on the P-semiconductor layer material.
  • an ISO (Isolation) etching process is performed on the P-electrode material, the P-semiconductor layer material, the active layer material, and the N-semiconductor layer material to form an N-semiconductor layer 712a on the growth substrate layer 711.
  • a plurality of semiconductor stacked structures 712 formed of a stack of an active layer 712b, a P-semiconductor layer 712c, and a P-electrode 712d are formed.
  • the semiconductor stack structure 712 is formed in plural in a shape spaced apart from each other on the growth substrate layer 711 by the ISO etching process.
  • the etching process for forming the semiconductor laminate structure 712 without performing an ISO etching process for etching all of the N-semiconductor layer material, active layer material, P-semiconductor layer material and P-electrode material, selective As a result, only the material for the P-electrode may be patterned to form a semiconductor stack structure.
  • a passivation layer 713 is formed on a surface of the growth substrate layer 711 including side surfaces of the plurality of semiconductor stacked structures 712 to absorb or block harmful ions.
  • a barrier layer 714 is formed on the entire surface of the growth substrate layer 711 so that the formed semiconductor stack structure is embedded.
  • a growth substrate bonding layer 715 is formed on the barrier layer 714 to attach the submount substrate 700 and the epitaxial structure 710 by eutectic bonding.
  • An epitaxial structure 710 including a substrate layer 711, a semiconductor stack structure 712, and a growth substrate bonding layer 715 is provided.
  • the growth substrate bonding layer 715 is Al-Si, Ag-Cd, Au-Sb, Al-Zn, Al-Mg, Al-Ge, Pd-Pb, Ag-Sb, Au-In, Al-Cu- Si, Ag-Cd-Cu, Cu-Sb, Cd-Cu, Au-Sn, Ag-Sn, Au-Sn-Ni, Ag-Sn-Ni, Al-Si-Cu, Ag-Cu, Ag-Zn, Ag-Cu-Zn, Ag-Cd-Cu-Zn, Au-Si, Au-Ge, Au-Ni, Au-Cu, Au-Ag-Cu, Cu-Cu 2 O, Cu-Zn, Cu-P, It is formed of a material layer including at least one of Ni-B, Ni-Mn-Pd, Ni-P, and Pd-Ni. Meanwhile, a seed layer (not shown) made of metal may be further provided to facilitate bonding with other layers.
  • the growth substrate bonding layer 715 and the submount substrate bonding are bonded by a thermo-compressive method to bond the prepared submount substrate 700 and the epitaxial structure 710. Bond layer 705.
  • the process of bonding the growth substrate bonding layer 715 and the submount substrate bonding layer 705 is not limited to that performed by the heat-compression method, and electroplating using a plating crystal nucleus layer. It can be done by the method.
  • the submount substrate 700 including the temporary support substrate layer 701 may have an epitaxial formation on which the growth substrate layer 711 is formed. Since the thermal expansion coefficient is different from that of the technical structure 710, when the submount substrate is bonded by wafer bonding, wafer warpage and fine micro cracks are generated inside the semiconductor stacked structure. However, in the present invention, by providing the submount substrate having the stress release layer, it is possible to prevent the wafer warpage phenomenon caused by the difference in thermal expansion coefficient during the bonding process. As a result, the subsequent process can be made stable and a high reliability light emitting device can be obtained without thermal and mechanical damage.
  • the growth substrate bonding layer 715 and the sub using a submount substrate having no stress lilly layer are used.
  • a stress release layer including a stress release seed layer may be formed on the lower surface of the temporary support substrate layer of the submount substrate.
  • the growth substrate is formed by performing a laser lift off process on a result of bonding the epitaxial structure 710 and the submount substrate 700 including the stress release layer 707.
  • a layer is separated from the semiconductor stacked structure 712.
  • a laser beam which is a strong energy source
  • laser absorption is strongly generated at the interface between the semiconductor laminate structure and the growth substrate layer, thereby causing thermal chemical decomposition reaction of gallium nitride present at the interface.
  • the growth substrate layer made of transparent sapphire is lifted off.
  • an N-electrode material is deposited on the semiconductor stacked structure 712 exposed as the growth substrate layer is separated due to the laser lift-off process, and then the N-electrode material is etched.
  • a thermally stable N-electrode 712e is formed on the N-semiconductor layer 712a to form the P-electrode 712d, the P-semiconductor layer 712c, the active layer 712b, and the N-semiconductor layer 712a.
  • a semiconductor light emitting device electrode structure including a semiconductor stacked structure 712 and an N-electrode 712e is formed.
  • a semiconductor light emitting device electrode structure including the N-electrode 712e and the semiconductor stacked structure 712 into a single chip structure mechanical cutting, grinding, and chemical treatment may be performed according to the N-electrode formation direction. Dicing to cut only in the vertical direction with respect to the submount substrate including the epitaxial structure formed between the semiconductor stacked structures 712 by etching and laser removal, but to the stress release layer 707. Perform the process. Preferably, a dicing process is performed to cut the submount substrate including the epitaxial structure until at least the sacrificial layer 702 surface, more preferably the top surface of the sacrificial layer 702 is exposed.
  • the temporary support substrate layer 701 formed on the lower surface of the sacrificial layer has an advantage of being recyclable.
  • Another dicing process according to an embodiment may include forming the semiconductor light emitting device electrode structure including the N-electrode and the semiconductor stacked structure as a modular structure, as shown in FIG. 8, between the semiconductor stacked structures.
  • the temporary support substrate layer is horizontally oriented by dissolving the sacrificial layer by using an acid, base, or salt solution that is determined according to the material used as the sacrificial layer with respect to the substrate product on which the dicing process is performed. According to the separation (separation) and removed to finally manufacture a unified semiconductor light emitting device.
  • the support substrate 704 formed on the sacrificial layer preferably serves as a support layer and an electrode of the final semiconductor light emitting device. A support substrate having good conductivity, good heat transfer efficiency, and easy productivity is obtained.
  • the temporary support substrate layer is separated from the submount substrate while being removed together with the sacrificial layer for heat dissipation of the light emitting device, but when the submount substrate is provided, the temporary support substrate layer is provided to secure the thickness of the submount substrate. This makes it possible to bring about mechanical stability in a subsequent process than a submount substrate having a thin thickness, thereby preventing breakage during the process, thereby ensuring the stability of the manufacturing process.

Landscapes

  • Led Device Packages (AREA)
  • Led Devices (AREA)
  • Semiconductor Lasers (AREA)

Abstract

La présente invention concerne un sous-substrat de fixation pour un dispositif électroluminescent semi-conducteurs et un procédé de fabrication dudit dispositif électroluminescent semi-conducteur utilisant ledit sous-substrat et, plus particulièrement, un procédé de fabrication d'un dispositif électroluminescent semi-conducteur vertical, dans lequel un sous-substrat de fixation d'une structure multicouche ayant une couche de libération des tensions, une couche de substrat de support temporaire, et une couche de substrat de support est prévu. Le sous-substrat de fixation prévu est utilisé en tant que substrat de support d'un dispositif électroluminescent semi-conducteur, ce qui permet d'obtenir un dispositif émetteur de lumière d'une grande qualité à haute performance.
PCT/KR2013/001436 2012-02-28 2013-02-22 Sous-substrat de fixation pour dispositif électroluminescent semi-conducteurs et procédé de fabrication dudit dispositif électroluminescent semi-conducteur utilisant ledit sous-substrat Ceased WO2013129805A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2012-0020250 2012-02-28
KR1020120020250A KR101210426B1 (ko) 2012-02-28 2012-02-28 반도체 발광소자용 서브마운트 기판 및 이를 이용한 반도체 발광소자의 제조방법

Publications (1)

Publication Number Publication Date
WO2013129805A1 true WO2013129805A1 (fr) 2013-09-06

Family

ID=47907291

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2013/001436 Ceased WO2013129805A1 (fr) 2012-02-28 2013-02-22 Sous-substrat de fixation pour dispositif électroluminescent semi-conducteurs et procédé de fabrication dudit dispositif électroluminescent semi-conducteur utilisant ledit sous-substrat

Country Status (2)

Country Link
KR (1) KR101210426B1 (fr)
WO (1) WO2013129805A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105261930A (zh) * 2015-10-21 2016-01-20 宜兴市大元电子科技有限公司 一种半导体激光器微通道冷却热沉
KR102784205B1 (ko) 2019-10-22 2025-03-21 엘지전자 주식회사 마이크로 led를 이용한 디스플레이 장치 및 이의 제조 방법
KR102274144B1 (ko) * 2020-01-17 2021-07-07 전남대학교산학협력단 전자 소자용 박막 및 그의 제조방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004281863A (ja) * 2003-03-18 2004-10-07 Nichia Chem Ind Ltd 窒化物半導体素子及びその製造方法
KR100916366B1 (ko) * 2006-12-08 2009-09-11 고려대학교 산학협력단 반도체 발광소자용 지지기판 및 이를 이용한 수직구조의 반도체 발광소자 제조 방법
KR20100008123A (ko) * 2008-07-15 2010-01-25 고려대학교 산학협력단 이중 히트 씽크층으로 구성된 지지대를 갖춘 고성능수직구조의 반도체 발광소자

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005026291A (ja) 2003-06-30 2005-01-27 Sharp Corp 窒化物系半導体発光装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004281863A (ja) * 2003-03-18 2004-10-07 Nichia Chem Ind Ltd 窒化物半導体素子及びその製造方法
KR100916366B1 (ko) * 2006-12-08 2009-09-11 고려대학교 산학협력단 반도체 발광소자용 지지기판 및 이를 이용한 수직구조의 반도체 발광소자 제조 방법
KR20100008123A (ko) * 2008-07-15 2010-01-25 고려대학교 산학협력단 이중 히트 씽크층으로 구성된 지지대를 갖춘 고성능수직구조의 반도체 발광소자

Also Published As

Publication number Publication date
KR101210426B1 (ko) 2012-12-11

Similar Documents

Publication Publication Date Title
WO2009145465A2 (fr) Dispositif émettant de la lumière et procédé de production de ce dernier
WO2009145483A2 (fr) Élément électroluminescent et son procédé de production
WO2010008209A2 (fr) Substrat de maintien pour produire un élément électroluminescent à semi-conducteur verticalement structuré, et élément électroluminescent à semi-conducteur verticalement structuré utilisant un tel substrat
WO2012077884A1 (fr) Procédé de fabrication d'un dispositif semi-conducteur utilisant la technique de connexion groupée par thermocompression, et dispositif semi-conducteur fabriqué par ledit procédé
WO2009148253A2 (fr) Substrat de support utilise dans la fabrication d’un dispositif electroluminescent semiconducteur et dispositif comprenant ledit substrat
WO2011065723A2 (fr) Élément électroluminescent à semi-conducteur à structure verticale et son procédé de production
WO2016056750A1 (fr) Dispositif à semi-conducteurs et son procédé de fabrication
WO2009116830A2 (fr) Dispositif à semi-conducteur et procédé de fabrication associé
WO2009120044A2 (fr) Élément électroluminescent et procédé de production correspondant
WO2009145502A2 (fr) Élément électroluminescent
WO2009125953A2 (fr) Élément lumineux
WO2009120011A2 (fr) Dispositif électroluminescent et son procédé de fabrication
WO2016153218A1 (fr) Diode luminescente, boîtier de diode luminescente la comprenant, et système d'éclairage la comprenant
WO2015190722A1 (fr) Élément électroluminescent et dispositif d'éclairage
WO2016064216A1 (fr) Substrat de support pour dispositif semi-conducteur, appareil semi-conducteur le comprenant, et son procédé de fabrication
WO2011129548A2 (fr) Ensemble substrat pour la croissance de cristaux et procédé de fabrication d'un dispositif émetteur de lumière utilisant ledit ensemble
WO2016137197A1 (fr) Dispositif électroluminescent et unité d'éclairage comprenant ce dernier
WO2010044642A2 (fr) Dispositif électroluminescent à semiconducteurs et son procédé de fabrication
KR100916366B1 (ko) 반도체 발광소자용 지지기판 및 이를 이용한 수직구조의 반도체 발광소자 제조 방법
WO2016153214A1 (fr) Élément électroluminescent et boîtier d'élément électroluminescent
KR100999548B1 (ko) 수직구조를 갖는 반도체 발광소자 제조용 지지기판, 이를 이용한 수직구조를 갖는 반도체 발광소자 제조방법 및 수직구조를 갖는 반도체 발광소자
WO2010011048A2 (fr) Dispositif électroluminescent à semi-conducteur et son procédé de production
WO2014084500A1 (fr) Procédé de séparation d'un substrat et procédé de fabrication d'une puce de diode électroluminescente l'utilisant
WO2017014580A1 (fr) Boîtier d'éléments luminescents
KR101210426B1 (ko) 반도체 발광소자용 서브마운트 기판 및 이를 이용한 반도체 발광소자의 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13755560

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13755560

Country of ref document: EP

Kind code of ref document: A1