WO2013176306A1 - Architecture de système basée sur une mémoire flash - Google Patents

Architecture de système basée sur une mémoire flash Download PDF

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Publication number
WO2013176306A1
WO2013176306A1 PCT/KR2012/004046 KR2012004046W WO2013176306A1 WO 2013176306 A1 WO2013176306 A1 WO 2013176306A1 KR 2012004046 W KR2012004046 W KR 2012004046W WO 2013176306 A1 WO2013176306 A1 WO 2013176306A1
Authority
WO
WIPO (PCT)
Prior art keywords
raid
flash memory
coupled
controller
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2012/004046
Other languages
English (en)
Inventor
Byungcheol Cho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taejin Infotech Co Ltd
Original Assignee
Taejin Infotech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taejin Infotech Co Ltd filed Critical Taejin Infotech Co Ltd
Priority to PCT/KR2012/004046 priority Critical patent/WO2013176306A1/fr
Publication of WO2013176306A1 publication Critical patent/WO2013176306A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD

Definitions

  • a fourth aspect of the present invention provides a method for providing an SSD system architecture based on flash memory, comprising: coupling a processor to a chip; coupling a main RAID controller to the chip; coupling a set of SSD RAID controllers to the main RAID controller; and coupling a set of flash memory control units to each of the set of SSD RAID controllers, each of the set of flash memory control units comprising an SSD controller and a set of flash memory units.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
PCT/KR2012/004046 2012-05-23 2012-05-23 Architecture de système basée sur une mémoire flash Ceased WO2013176306A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/KR2012/004046 WO2013176306A1 (fr) 2012-05-23 2012-05-23 Architecture de système basée sur une mémoire flash

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/KR2012/004046 WO2013176306A1 (fr) 2012-05-23 2012-05-23 Architecture de système basée sur une mémoire flash

Publications (1)

Publication Number Publication Date
WO2013176306A1 true WO2013176306A1 (fr) 2013-11-28

Family

ID=49623977

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2012/004046 Ceased WO2013176306A1 (fr) 2012-05-23 2012-05-23 Architecture de système basée sur une mémoire flash

Country Status (1)

Country Link
WO (1) WO2013176306A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030221061A1 (en) * 2002-05-23 2003-11-27 International Business Machines Corporation Serial interface for a data storage array
KR20090106139A (ko) * 2008-04-04 2009-10-08 주식회사 셀픽 레이드 기능을 지원하는 솔리드 스테이트 디스크
KR20110124711A (ko) * 2010-05-11 2011-11-17 주식회사 태진인포텍 멀티레벨 알에이아이디 아키텍처용 하이브리드 저장 시스템

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030221061A1 (en) * 2002-05-23 2003-11-27 International Business Machines Corporation Serial interface for a data storage array
KR20090106139A (ko) * 2008-04-04 2009-10-08 주식회사 셀픽 레이드 기능을 지원하는 솔리드 스테이트 디스크
KR20110124711A (ko) * 2010-05-11 2011-11-17 주식회사 태진인포텍 멀티레벨 알에이아이디 아키텍처용 하이브리드 저장 시스템

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