WO2014015628A1 - Substrat de réseau, son procédé de fabrication et dispositif d'affichage - Google Patents

Substrat de réseau, son procédé de fabrication et dispositif d'affichage Download PDF

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Publication number
WO2014015628A1
WO2014015628A1 PCT/CN2012/086776 CN2012086776W WO2014015628A1 WO 2014015628 A1 WO2014015628 A1 WO 2014015628A1 CN 2012086776 W CN2012086776 W CN 2012086776W WO 2014015628 A1 WO2014015628 A1 WO 2014015628A1
Authority
WO
WIPO (PCT)
Prior art keywords
photoresist
pattern
gate
drain
pixel electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/086776
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English (en)
Chinese (zh)
Inventor
曹占锋
童晓阳
姚琪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2014015628A1 publication Critical patent/WO2014015628A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • Embodiments of the present invention provide a method for fabricating an array substrate, including the following steps:
  • the step S1 specifically includes:
  • the exposed gate metal film is etched away and the remaining photoresist is stripped to form a pattern including the gate and gate lines.
  • the step S2 specifically includes:
  • a gate insulating film Forming a gate insulating film, an active layer sequentially on a substrate on which a pattern including a gate electrode and a gate line is formed a thin film and a source/drain metal film, and coating a photoresist on the source/drain metal film;
  • the remaining photoresist is stripped to form a gate insulating layer, an active layer pattern, a source/drain pattern, and a data line pattern.
  • the step S3 specifically includes:
  • the glue completely reserved area corresponds to an area outside the region where the photoresist is not completely retained
  • the first photoresist is retained above the layer, and the second photoresist over the first photoresist is less than the second photoresist corresponding to the portion of the drain region and the pixel electrode region thickness of;
  • the remaining first photoresist and the second photoresist are stripped to form a pixel electrode pattern.
  • the second photoresist is a photoresist having a viscosity in the range of 2 to 4 mPas.
  • the planarity of the photoresist is planarized by rotating the substrate.
  • Embodiments of the present invention also provide an array substrate including a gate line formed on an insulating substrate, a gate insulating layer, a data line, and a pixel unit formed between the gate line and the data line, the pixel unit including a thin film transistor and a pixel electrode, the gate insulating layer being over the gate of the gate line and the thin film transistor, the pixel electrode being over the gate insulating layer, and the thin film transistor The drain connection.
  • the array substrate further includes a passivation layer formed on the source/drain and the data line.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • FIG. 1 is a schematic cross-sectional view of a substrate after forming a gate and a gate line through a first mask and etching in an array substrate manufacturing method according to an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view showing a substrate in which a gate insulating film, an active layer film, and a source/drain metal film are sequentially deposited on the substrate of FIG. 1;
  • FIG. 3 is a schematic cross-sectional view showing a substrate after forming a gate insulating film, an active layer, a source/drain, and a data line through a second mask and etching on the substrate of FIG. 2;
  • FIG. 4 is a schematic cross-sectional view showing a substrate on which a passivation layer film is deposited on the basis of the substrate of FIG. 3, and a first photoresist is coated on the passivation layer film;
  • FIG. 5 is a schematic cross-sectional view of the substrate after the third mask is formed and etched to form a passivation layer pattern on the basis of the substrate of FIG. 4;
  • FIG. 6 is a schematic cross-sectional view showing a substrate on which a pixel electrode metal film is deposited on the basis of the substrate of FIG. 5, and a planarized second photoresist is coated on the pixel electrode metal film;
  • FIG. 7 is a schematic cross-sectional view of a substrate after a second photoresist other than a pixel electrode region and a pixel electrode pattern and a source/drain pattern contact region is ashed on the basis of the substrate of FIG. 6;
  • Figure 8 is a schematic cross-sectional view showing a substrate after etching the exposed metal film of the pixel electrode on the basis of the substrate of Figure 7;
  • FIG. 9 is a schematic cross-sectional view of the array substrate finally formed after the remaining first photoresist and the second photoresist are peeled off on the basis of the substrate of FIG. 8;
  • FIG. 10 is a schematic plan view of an array substrate according to an embodiment of the present invention.
  • Step 1 forming a gate metal film on the glass substrate 1 (which can be formed by sputtering, deposition or spin coating), coating a photoresist on the gate metal film, and performing photolithography through the mask Exposure development of the glue to retain the photoresist in the gate pattern area A, etching away the exposed gate metal film and stripping the remaining photoresist, as shown in FIG. 1, forming the gate 2 and the gate line (in the figure) Gate lines are not shown, and a common electrode is also typically formed).
  • Step 2 sequentially forming a gate insulating film, an active layer film, and a source/drain metal film on the substrate on which the gate electrode 2 and the gate line are formed (which may be formed by sputtering, deposition or spin coating), as shown in As shown in Fig. 2, a gate insulating film and an active layer film are deposited by plasma enhanced chemical vapor deposition (PECVD), and a source/drain metal film is deposited by sputtering.
  • PECVD plasma enhanced chemical vapor deposition
  • the photoresist is coated on the source/drain metal film. ⁇ Exposing and developing the photoresist with a two-tone mask (gray mask or halftone mask), leaving the photoresist corresponding to the source region B and the drain region C and the photoresist corresponding to the channel region D And the thickness of the photoresist corresponding to the channel region D is smaller than the photoresist corresponding to the source region B and the drain region C.
  • the exposed active layer film and the source/drain metal film are etched away, and the photoresist corresponding to the channel region D is removed by ashing treatment and etched to form a channel. The remaining photoresist is stripped and a gate insulating layer 3, an active layer 4, a source/drain 5, and a data line (not shown) are formed as shown in FIG.
  • Step 3 forming a passivation layer on the substrate on which the gate insulating layer 3, the active layer 4, the source/drain 5, and the data line are formed by only one mask (which may be formed by sputtering, deposition, or spin coating)
  • the pixel electrode, the specific steps are as follows:
  • Step 3.1 depositing a passivation layer film on the substrate on which the gate insulating layer 3, the active layer 4, the source/drain 5, and the data line are formed, and coating the passivation layer film
  • the first photoresist 100 is overcoated.
  • the first photoresist 100 is exposed and developed by using a mask to form a photoresist completely reserved region and a photoresist completely unretained region, as shown in FIG. 5, in which the photoresist is not retained at all.
  • the region corresponds to a portion of the drain region F (the region where the drain is in contact with the pixel electrode) and the pixel electrode region G, and the photoresist completely reserved region corresponds to a region outside the completely non-retained region of the photoresist, that is, the passivation layer pattern region E .
  • the passivation layer film exposed by the partial drain region F and the pixel electrode region G is etched away, as shown in FIG. 5, such that the drain of the partial drain region F and the gate insulating layer 3 of the pixel electrode region G are exposed.
  • the exposed first passivator 100 is also removed after etching away the exposed passivation film.
  • Step 3.2 after the substrate after step 3.1, that is, the substrate shown in FIG. 5, a metal film of a pixel electrode is deposited by sputtering deposition, and a second photoresist 200 is coated on the metal film of the pixel electrode.
  • the second photoresist 200 is a fluidity-sensitive photoresist having a viscosity in the range of 2 to 4 mPas, and the second photoresist 200 can be planarized by rotation.
  • the substrate after the planarization of the second photoresist 200 is as shown in FIG. 6. After the planarization of the substrate after step 3.1 (FIG. 5), after planarization, the second lithography over the remaining first photoresist 100 is performed.
  • the thickness of the glue 200 is smaller than the thickness of the second photoresist 200 on the corresponding partial drain region F and the pixel electrode region G.
  • the second photoresist 200 is ashed, because the thickness of the second photoresist 200 in the partial drain region F and the pixel electrode region G is greater than the second photoresist 200 above the first photoresist 100.
  • the thickness of the second photoresist 200 capable of retaining a portion of the drain region F and the pixel electrode region G after ashing, thereby graying out the second photoresist 200 over the first photoresist 100, so that the first The pixel electrode metal film over the photoresist 100 is exposed, as shown in FIG. 7, and the exposed metal film of the pixel electrode is etched, as shown in FIG.
  • Step 3.4 stripping the remaining first photoresist 100 and the second photoresist 200 to form the passivation layer 6 and the pixel electrode 7, and finally forming an array substrate, as shown in FIG.
  • the above manufacturing process uses only one mask in the step 3 to make the passivation layer and the pixel electrode, and reduces the mask once compared with the prior art, together with the mask in steps 1 and 2, a total of three masks, and only in step 2
  • a grayscale masking technique or a halftone masking technique which reduces the cost and improves the yield.
  • FIG. 9 is a cross-sectional view taken along line AA of FIG. 10
  • the array substrate comprising: a gate line formed on the glass substrate 1.
  • the pixel unit includes a thin film transistor and a pixel electrode 7.
  • the thin film transistor further includes a gate electrode 2 and a gate insulating layer 3. Active layer 4, source/drain 5.
  • the gate insulating layer 3 is located above the gate line 8 and the gate electrode 2.
  • the pixel electrode 7 directly overlies the gate insulating layer 3 and is connected to the source/drain 5 of the thin film transistor. Since the pixel electrode 7 directly covers the gate insulating layer 3, a two-layer structure of a gate insulating layer and a passivation layer is formed between the conventional pixel electrode and the glass substrate, which is advantageous for improving transmittance.
  • Embodiments of the present invention also provide a display device including the array substrate of Embodiment 2 above.
  • the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like, or any display product or component.
  • the method for fabricating an array substrate according to an embodiment of the present invention achieves the purpose of forming an array substrate by using only three times of masks by combining the passivation layer and the pixel electrode twice, and using only one gray in the entire manufacturing process. Degree mask technology reduces costs and improves yield.
  • the conventional pixel electrode and the glass substrate have two layers of a gate insulating layer and a passivation layer.
  • the pixel electrode of the array substrate fabricated by the method according to the embodiment of the present invention is directly on the gate insulating layer, so the array substrate structure is favorable for improving. Transmittance.
  • the production method includes the following steps:
  • step S1 comprises: forming a gate metal film on the transparent insulating substrate;
  • the exposed gate metal film is etched away and the remaining photoresist is stripped to form a pattern including the gate and gate lines.
  • step S2 includes Includes:
  • a gate insulating layer film, an active layer film, and a source/drain metal film on the substrate forming the pattern including the gate electrode and the gate line, and coating a photoresist on the source/drain metal film;
  • the remaining photoresist is stripped to form a gate insulating layer, an active layer pattern, a source/drain pattern, and a data line pattern.
  • step S3 comprises:
  • the glue completely reserved area corresponds to an area outside the region where the photoresist is not completely retained
  • the first photoresist of the passivation layer, the second photoresist thickness d above the first photoresist, and the second portion corresponding to the partial drain region and the pixel electrode region The thickness of the photoresist;
  • the remaining first photoresist and the second photoresist are stripped to form a pixel electrode pattern.
  • an array substrate comprising: a gate line formed on an insulating substrate, a gate insulating layer, a data line, and a pixel unit formed between the gate line and the data line, the pixel unit including a thin film transistor and a pixel electrode
  • the gate insulating layer is located above the gate line and the gate of the thin film transistor, wherein the pixel electrode is located above the gate insulating layer and is connected to a drain of the thin film transistor.
  • a display device comprising the array substrate according to (7) or (8).

Landscapes

  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un substrat de réseau, le substrat de réseau et un dispositif d'affichage. Le procédé de fabrication du substrat de réseau comprend les étapes suivantes : S1 : former un motif d'une électrode de grille (2) et d'une ligne de grille sur un substrat isolant ; S2 : former une couche d'isolation de grille (3), un motif de couche active (4), une source/drain (5) et un motif de ligne de données sur le substrat après l'étape S1 ; et S3 : former un motif de couche de passivation et un motif d'électrode de pixel sur le substrat après l'étape S2 par traitement à masque unique, le motif d'électrode de pixel étant en contact avec le motif de source/drain et recouvrant la couche d'isolation de grille (3). Le procédé de fabrication du substrat de réseau implique uniquement trois masques, et seulement un masque à niveau de gris est utilisé. Ainsi, le coût est réduit et le rendement est augmenté. L'électrode de pixel de substrat de réseau selon le procédé est directement agencée sur la couche d'isolation de grille, de telle sorte que la structure de substrat de réseau est bénéfique pour améliorer la transmittance.
PCT/CN2012/086776 2012-07-27 2012-12-17 Substrat de réseau, son procédé de fabrication et dispositif d'affichage Ceased WO2014015628A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210265597.3A CN102768990B (zh) 2012-07-27 2012-07-27 阵列基板及其制作方法、显示装置
CN201210265597.3 2012-07-27

Publications (1)

Publication Number Publication Date
WO2014015628A1 true WO2014015628A1 (fr) 2014-01-30

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WO (1) WO2014015628A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102768990B (zh) * 2012-07-27 2014-06-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN103034049A (zh) * 2012-12-13 2013-04-10 京东方科技集团股份有限公司 金属线及阵列基板的制作方法
CN103779232B (zh) 2014-01-28 2016-08-17 北京京东方光电科技有限公司 一种薄膜晶体管的制作方法
CN105206553A (zh) * 2015-08-28 2015-12-30 京东方科技集团股份有限公司 一种刻蚀装置及导电层的刻蚀方法、阵列基板的制备方法
CN105914183B (zh) * 2016-06-22 2019-04-30 深圳市华星光电技术有限公司 Tft基板的制造方法
CN106847930A (zh) * 2017-04-01 2017-06-13 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及制备方法
CN108089377A (zh) 2018-02-13 2018-05-29 京东方科技集团股份有限公司 一种水平电场型的显示面板、其制作方法及显示装置
CN109445193A (zh) * 2018-02-13 2019-03-08 京东方科技集团股份有限公司 一种水平电场型的显示面板、其制作方法及显示装置
CN116400545A (zh) * 2023-04-17 2023-07-07 北京京东方显示技术有限公司 电子纸基板及其制备方法、电子纸显示装置

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US7005332B2 (en) * 2004-07-06 2006-02-28 Chunghwa Picture Tubes, Ltd. Fabrication method of thin film transistor
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CN102768990A (zh) * 2012-07-27 2012-11-07 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

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KR100476366B1 (ko) * 2002-04-17 2005-03-16 엘지.필립스 엘시디 주식회사 박막 트랜지스터 어레이 기판 및 그 제조 방법
CN101807584B (zh) * 2009-02-18 2012-12-26 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN102034751B (zh) * 2009-09-24 2013-09-04 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN102456620B (zh) * 2010-10-22 2015-04-15 北京京东方光电科技有限公司 阵列基板及其制造方法

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Publication number Priority date Publication date Assignee Title
CN1605918A (zh) * 2003-10-11 2005-04-13 Lg.菲利浦Lcd株式会社 薄膜晶体管阵列基板及其制造方法
US7005332B2 (en) * 2004-07-06 2006-02-28 Chunghwa Picture Tubes, Ltd. Fabrication method of thin film transistor
CN1996603A (zh) * 2006-12-13 2007-07-11 京东方科技集团股份有限公司 一种薄膜晶体管液晶显示器像素结构及其制造方法
CN102768990A (zh) * 2012-07-27 2012-11-07 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

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CN102768990B (zh) 2014-06-25

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