WO2014094450A1 - 一种晶体管、晶体管的散热结构以及晶体管的生产方法 - Google Patents

一种晶体管、晶体管的散热结构以及晶体管的生产方法 Download PDF

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Publication number
WO2014094450A1
WO2014094450A1 PCT/CN2013/082154 CN2013082154W WO2014094450A1 WO 2014094450 A1 WO2014094450 A1 WO 2014094450A1 CN 2013082154 W CN2013082154 W CN 2013082154W WO 2014094450 A1 WO2014094450 A1 WO 2014094450A1
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Prior art keywords
layer
thermocouple
grown
type
heat
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English (en)
French (fr)
Inventor
王大朋
赵志勇
曾武
穆学禄
宗柏青
崔亦军
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ZTE Corp
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ZTE Corp
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Priority to JP2015548156A priority Critical patent/JP6064054B2/ja
Priority to EP13864368.9A priority patent/EP2937908B1/en
Priority to US14/653,693 priority patent/US9520338B2/en
Priority to KR1020157018392A priority patent/KR102010626B1/ko
Publication of WO2014094450A1 publication Critical patent/WO2014094450A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/28—Arrangements for cooling comprising Peltier coolers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/17—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/02—Manufacture or treatment of conductive package substrates serving as an interconnection, e.g. of metal plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/658—Shapes or dispositions of interconnections for devices provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Definitions

  • a power amplifier is an indispensable component of a wireless communication system, a medical system, a power supply device, a sound system, and a military radar system, and mainly functions to amplify the power of a transmitted signal. These devices generally have high power requirements. For example, wireless communication systems range from tens of watts to hundreds of watts. Medical devices can reach kilowatts, and radar devices can even reach several kilowatts.
  • the transistor As the core device of the power amplifier, withstands the amplification and output of all powers, but is limited to the working efficiency of the amplifier itself, and the amplified power. Not all of them are output as useful signals.
  • the power of a useful signal in a general communication system is only about 40%.
  • about 60% of the power is in the form of heat, and a small amount of heat is transferred to the surrounding air. Causing a large impact; most of the heat is concentrated in the power amplifier tube die and its surrounding devices, such as ceramic capacitors, aluminum electrolytic capacitors, etc.
  • Fig. 1 is a schematic diagram of a conventional transistor heat sink in a power amplifier, the transistor is soldered on the PCB, the PCB is fixed on the copper substrate, and the bottom of the transistor The source metal is soldered on the copper substrate, and then the copper substrate is fixed on the device casing. The contact between the copper substrate and the device casing is often coated with a thermal conductive adhesive or a thermal pad, and heat is transferred from the die through the source metal.
  • the copper substrate is transferred to the device casing and the heat dissipating teeth through the thermal adhesive, and then exchanges heat with the surrounding environment.
  • the thermal resistance between the power transistor and the device casing is affected by many aspects. For example, the welding effect of the tube, the thermal resistance of the copper substrate of the power amplifier, and the degree of hooking of the thermal conductive adhesive can cause the thermal resistance to become large, resulting in a very high heat transfer efficiency. Low, heat cannot be exported in time. After heat balance, the temperature of the transistor's die is very high, and the heat is quickly transferred to other devices on the PCB, which causes other devices to be heated and affects performance and life. In addition, there are many heat dissipating teeth on the device casing. Increases the size of the entire device and reduces the competitive advantage.
  • the Peltier effect is called the second effect of semiconductor thermoelectricity.
  • the thermocouple refrigeration device based on this effect has been applied in many fields of the industry. It has many advantages, such as: rapid cooling, heating; Degree control tolerance is within plus or minus 0.1 °C; compact and lightweight, no noise, reliable; multi-stage cascade can reach temperature difference above 100 °C.
  • the refrigeration equipment is used as an accessory component for external use, and requires additional purchase and installation, especially in the heat dissipation of high-power amplifiers.
  • Embodiments of the present invention provide a heat dissipation device for a transistor and a transistor, and a method for manufacturing the transistor, to solve the heat dissipation problem of the transistor in the prior art.
  • a transistor comprising: a semiconductor growth substrate and a semiconductor thermoelectric effect device, the semiconductor thermoelectric effect device comprising a semiconductor compound layer, a metal layer, a heat conduction layer, a thermocouple heat conduction device and a heat dissipation layer, and a semiconductor compound
  • the layer is grown on the semiconductor growth substrate, the metal layer is grown on the semiconductor compound layer, the heat conduction layer is grown on the metal layer, the thermocouple heat conduction device is grown on the heat conduction layer, and the heat dissipation layer is grown on the thermocouple heat conduction device opposite to the heat conduction layer.
  • thermocouple heat conducting device further comprises a power supply arm, and the power supply arm is grown on the heat conducting layer and electrically connected to the thermocouple heat conducting device.
  • the thermocouple heat conducting device comprises a group of N-type thermocouples and P-type thermocouples, wherein a plurality of sequentially arranged channels are arranged on the metal layer, and the openings of the channels are located at a bonding surface of the metal layer and the semiconductor compound layer.
  • the heat conducting layer is grown at the bottom of the channel, and a plurality of sets of N-type thermocouples and P-type thermocouples are grown along the channel on the heat conducting layer, and the N-type thermocouples and the P-type thermocouples in each group are electrically connected, in the adjacent group.
  • the N-type thermocouple is electrically connected to the P-type thermocouple to form an N-type thermocouple-P-type thermocouple-N-type thermocouple path, the power supply arm and the N-type thermocouple at each end of each channel and each channel The other end of the P-type thermocouple is electrically connected.
  • the thermocouple heat conducting device further comprises a first power supply electrode and a second power supply electrode, wherein the first power supply electrode is grown on the heat conduction layer in the channel and the position between the adjacent group of the N-type thermocouple and the P-type thermocouple Upper, electrically connecting the N-type thermocouple and the P-type thermocouple in the adjacent group; the second power supply electrode is grown at the bottom and the position between the N-type thermocouple and the P-type thermocouple of each group, electrically connected in each group N-type thermocouples and P-type thermocouples.
  • the thermocouple heat conducting device further comprises a temperature detecting point, and the temperature detecting point is grown on the heat conducting layer on the metal layer.
  • a heat dissipation structure of a transistor comprising: a printed circuit board, a heat dissipating substrate and a transistor, the printed circuit board is mounted on the heat dissipating substrate, the transistor is connected to the printed circuit board, and the transistor comprises a semiconductor growth substrate and a semiconductor thermoelectric effect device, and the semiconductor thermoelectric
  • the effect device comprises a semiconductor compound layer, a metal layer, a thermally conductive layer thermocouple heat conducting device and a heat dissipation layer, the semiconductor compound layer is grown on the semiconductor growth substrate, and the metal layer is grown on the semiconductor
  • the heat conducting layer is grown on the metal layer
  • the thermocouple heat conducting device is grown on the heat conducting layer
  • the heat dissipation layer is grown on the other side of the thermocouple heat conducting device opposite to the heat conducting layer, the metal layer of the transistor and the heat dissipating tooth substrate
  • the heat dissipating tooth is soldered, and the heat dissipating layer is in contact with the heat dissip
  • thermocouple heat conducting device further comprises a power supply arm, and the power supply arm is grown on the heat conducting layer and electrically connected with the thermocouple heat conducting device.
  • the thermocouple heat conducting device comprises a group of N-type thermocouples and P-type thermocouples, wherein a plurality of sequentially arranged channels are arranged on the metal layer, and the openings of the channels are located at a bonding surface of the metal layer and the semiconductor compound layer.
  • the heat conducting layer is grown at the bottom of the channel, and a plurality of sets of N-type thermocouples and P-type thermocouples are grown along the channel on the heat conducting layer, and the N-type thermocouples and the P-type thermocouples in each group are electrically connected, in the adjacent group.
  • the N-type thermocouple is electrically connected to the P-type thermocouple to form an N-type thermocouple-P-type thermocouple-N-type thermocouple path, the power supply arm and the N-type thermocouple at each end of each channel and each channel The other end of the P-type thermocouple is electrically connected.
  • thermocouple heat conducting device further comprises a first power supply electrode and a second power supply electrode, wherein the first power supply electrode is grown on the heat conduction layer in the channel and the position between the adjacent group of the N-type thermocouple and the P-type thermocouple Upper, electrically connecting the N-type thermocouple and the P-type thermocouple in the adjacent group; the second power supply electrode is grown at the bottom and the position between the N-type thermocouple and the P-type thermocouple of each group, electrically connected in each group N-type thermocouples and P-type thermocouples.
  • the heat dissipation structure further comprises a DC power supply device and a temperature detection and control chip
  • the thermocouple heat conduction device further comprises a temperature detection point
  • the temperature detection point is grown on the heat conduction layer on the metal layer
  • the temperature detection and control chip respectively and the temperature detection point Connected to a DC power supply.
  • a method for producing a transistor comprising the steps of: a. providing a growth substrate layer, growing a portion above the substrate, including a conductive channel, a doped region, a semiconductor oxide, a power supply electrode, etc., b.
  • a semiconductor growth substrate layer A layer of a semiconductor compound is grown thereon, c a metal thin film is epitaxially grown on the surface of the compound layer, a metal layer is formed on the interface of the metal and the semiconductor by a vapor deposition technique, and a plurality of regularly arranged channels are etched on the metal layer.
  • the opening of the channel is located on the opposite side of the bonding surface of the metal layer and the semiconductor compound layer, d. using a vapor deposition technique to grow a thermally conductive layer at the bottom of the channel, e. epitaxially growing the power supply arm on the surface of the thermally conductive layer by electroplating or vapor deposition
  • the first power supply electrode, the power supply arm and the first power supply electrode are independent parts, f.
  • thermocouple semiconductor layer N/P type thermocouple and the first power supply electrode is epitaxially grown by a vapor deposition technique or an electroplating method, and the second power supply electrode is covered on the surface of the second power supply electrode.
  • the power supply arm and the first power supply electrode are machined into separate portions of equal height.
  • the heat conducting layer and the heat dissipating layer use the same heat conducting material, and the outermost surface height of the heat dissipating layer is flush with the outermost surface of the channel.
  • a conductive metal thin film layer as a temperature detecting point is epitaxially grown on the heat conductive layer by electroplating or vapor deposition.
  • FIG. 1 is a schematic diagram of a conventional transistor heat sink
  • FIG. 2 is a schematic diagram of a novel transistor based on a Peltier effect according to an embodiment of the invention
  • FIG. 3 is a flow chart of a novel transistor semiconductor process according to an embodiment of the invention
  • FIG. 5 is a schematic diagram of a bottom view of a transistor BB according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a heat dissipation application of a transistor according to an embodiment of the present invention.
  • the present invention is based on the basic structure of a conventional LDMOSFET (laterally diffused metal oxide semiconductor) transistor, and combines the current semiconductor processing technology (such as epitaxial growth technology, vapor deposition technology, etc.) to apply the semiconductor Peltier effect to a conventional field effect transistor structure. Therefore, a novel fast thermal conduction transistor structure is proposed to solve the heat conduction problem of the conventional transistor.
  • the transistor of the present invention retains the mounting method of the existing tube on the one hand. It can be used on the other hand, and the heat of the die can be quickly exported to the heat dissipating teeth, and the temperature can be controlled within a certain range.
  • the present invention adopts a semiconductor epitaxial growth process to combine a semiconductor thermocouple and a heat sink device with a field effect transistor to form an integrated growth structure, thereby reducing unnecessary thermal resistance effects. It has a complete package structure from the appearance and has the same mounting method as the conventional transistor. The advantage is that the heat conduction effect is better, and the temperature can be detected and controlled.
  • a conventional transistor processing process is used to grow a conductive channel, a doped region, a semiconductor oxide, a metal electrode, and the like necessary for the operation of the transistor.
  • the lower half of Fig. 2 is a schematic view of the semiconductor thermoelectric effect device combined with the semiconductor substrate. As shown in FIG.
  • a schematic view of the AA section is shown, and one layer is a semiconductor growth substrate.
  • the 2 layers are semiconductor compounds grown on a semiconductor substrate.
  • a metal growth layer film is formed on two semiconductor compounds, such as a transition magnetic metal Mn, Cu, etc., and a thick metal layer 3 layers are formed on the metal film, and three layers are used as transistors.
  • the source is grounded to the metal and acts as a heat transfer metal layer for the transistor.
  • the heat conductive layer 4 layer and the heat dissipation layer 9 layer function as heat transfer and isolation, and are required to have good thermal conductivity and thermal stability, such as aluminum nitride, yttrium oxide, etc.; 4 layers serve as heat absorbing ends, absorbing the bottom of the transistor
  • the heat also acts to isolate the source metal layer and the thermocouple supply electrode; the 9-layer heat dissipation end transfers the heat conducted by the thermocouple to the external heat sink.
  • the 5th layer is the thermocouple positive and negative power supply arm, which is connected to the positive and negative poles of the power supply by welding.
  • the first power supply electrode 6 layer and the second power supply electrode 8 layer are power supply electrodes of the N/P type thermocouple, and the N/P type thermocouples are connected end to end to form a current flow.
  • 5, 6, and 8 layers are independent parts, 5 and 6 are equal in height, 5 layers are the two electric arms required for DC power supply; 6 layers and 8 layers are respectively at the two ends of the N/P thermocouple pole, Each layer consists of mutually independent metal electrodes connected to the two electrodes of adjacent N-type and P-type thermocouples, and the 6-layer and 8-layer layers are connected by N-type or P-type thermocouples; Layers 5, 6 and 8 form a current path.
  • the 7-layer is an N/P-type thermocouple layer, which is formed by a semiconductor doping process.
  • the current in the loop flows from N ⁇ P ⁇ N in sequence, transferring heat from the heat-absorbing end to the heat-dissipating end, and how much heat is absorbed and the current is The number of thermocouples is related.
  • a temperature detection point is connected to the temperature detecting chip for detecting the temperature at the bottom of the transistor and controlling the current at both ends of the N/P type thermocouple layer.
  • the bottom view of the BB of the transistor is schematic.
  • the source-level metal and the N/P thermocouple are arranged in phase, which can meet the grounding requirements of the source metal and meet the power supply and heat dissipation requirements of the thermocouple.
  • the temperature difference between the four-layer heat-absorbing end and the nine-layer heat-dissipating end can reach 71 °C, and the temperature difference can reach 131 °C when the multi-layer is used, and the maximum power dissipation can reach 300 W.
  • the heat dissipating device of the present invention is suitable for a transistor whose conductive channel is parallel to the ground plane, so that heat can be dissipated with maximum efficiency; the invention does not limit the type of semiconductor growth substrate, and can be adapted to Si substrate MOSFET, GaAs. Field effect transistors such as MESFETs and GaN FETs, and other semiconductor substrate transistors such as silicon germanium and indium phosphide. These transistors are characterized in that the source metal is parallel to the conductive channel, and the source metal is in close contact with the ground plane and heat dissipation. surface. An example of a heat dissipation application for a transistor is shown in FIG.
  • the PCB is mounted on the heat dissipating tooth substrate, the heat dissipating tooth substrate is a part of the whole device housing, the transistor gate and the drain are soldered on the PCB, and the bottom source metal and the lower heat dissipating teeth are well soldered, and the 9 layers of the heat dissipation in FIG. The end is in good contact with the heat dissipating teeth.
  • the positive and negative supply electrodes of the 5 layers are connected to the power supply on the PCB through the wires.
  • the wires can be soldered, and the wires pass through the heat dissipating teeth and the temperature detecting chip on the PCB.
  • the wire When it is turned on, the wire can also be taken out from the inside of the pipe body to form a terminal and connected to the wire.
  • Most of the heat generated by the transistor is conducted by the N/P thermocouple to the heat dissipating tooth, and then the heat from the heat dissipating tooth is blown into the surrounding air by an external fan (the fan can also be assembled on the outer casing of the whole device), also
  • the same heat dissipation effect can be achieved by water cooling or other means, so that most of the heat is dissipated through this way, and a small amount of heat is transmitted to the PCB through the heat dissipating teeth, but the influence on the device is already small.
  • the temperature detecting chip detects the temperature of the four-layer endothermic end in Fig.
  • the N/P thermocouple in real time, and achieves automatic control of the current level by the corresponding relationship between temperature and current (acquired by the test acquisition method before use), thereby controlling the N/P thermocouple.
  • the area of the bottom of the transistor can be increased to increase the number of N/P thermocouples and to derive heat more efficiently.
  • the height of the N/P thermocouple is recommended to be between 2.5mm and 4mm. If the height is too small, the amount of doping charge in the thermocouple material will be too small to affect the thermal conductivity; if the height is too large, the source metal heat dissipating teeth The length will increase accordingly, which will affect the source-level grounding effect, especially for transistors operating at high frequencies.
  • thermocouple layer stacking can be fabricated to enhance thermal conductivity, but it is not recommended for high-frequency transistors.
  • Layer mode (unless it does not affect the source level grounding effect); or processing into other shapes, such as folded form, curved form, etc., the upper case of the transistor can also be grown to increase the heat conduction channel and area, the specific way It should be extended and constrained according to system equipment and heat dissipation conditions.
  • FIG. 3 it is a flow chart of the fabrication process of the novel transistor semiconductor of the present invention. The fabricated embodiment will be described in detail below with reference to the flow chart 3 and the cut-away views 4 and 5.
  • Step 1 For processing the transistor amplifying functional region, refer to block 1 in FIG. 3, and referring to the structural schematic diagram in FIG. 4, firstly provide a layer of a growth substrate, such as a common substrate material such as single crystal silicon, silicon carbide, or gallium arsenide. , press According to the conventional semiconductor process technology, a portion above the substrate is grown, including a conductive channel, a doped region, a semiconductor oxide, a power supply electrode, and the like.
  • a growth substrate such as a common substrate material such as single crystal silicon, silicon carbide, or gallium arsenide.
  • Step 2 Starting from the step of processing the heat conduction function region of the transistor, referring to the frame 2 and the structure diagram 4 in FIG. 3, a semiconductor compound layer 2 is preferentially grown on the semiconductor growth substrate, and the compound layer requires high heat conduction efficiency and heat. It has good stability and is beneficial to the growth of the underlying metal thin film epitaxial layer, such as IV-VI compound.
  • Step 3 Referring to the frame 3 and the structure diagram 4 in FIG. 3, a metal film is epitaxially grown on the surface of the two-layer compound to form a metal/IV-VI semiconductor interface, and the metal material may be the same as the gate and the drain, or Different, but must be a good conductive and thermally conductive material.
  • Step 4 Referring to the frame 4 and the structure diagram 4 in FIG. 3, on the basis of the third step, the vapor deposition technique can also be used to grow a layer of a thermally conductive layer having a good heat conduction effect on the surface of the source metal channel, such as yttrium oxide. Aluminum nitride, etc., vapor deposition technology can effectively control the density and purity of the compound.
  • Step 5 Referring to Box 5 and Structure Figures 4 and 5 in Figure 3, the surface of the thermally conductive compound in the metal channel described in Step 4 is epitaxially grown as a 5, 6 and 10 layer by electroplating or vapor deposition. During the growth process, the metal-free layer is partially blocked by the mold, and the metal layer is formed only in the place where it is needed, and the 10 layers are temperature detection points.
  • Step 6 Referring to frame 6 and structure diagram 4 in FIG. 3, 7 layers of thermocouple semiconductor material are epitaxially grown on the basis of 6 layers, generally used as a germanium telluride compound semiconductor material, and then subjected to high temperature diffusion and ion implantation. The semiconductor material is doped to form N-type and P-type thermocouples arranged in phase.
  • Step 7 Referring to the frame 7 and the structure diagram 4 in FIG. 3, a metal film is epitaxially grown as a second power supply electrode layer 8 by vapor deposition or electroplating on the top of the 7-layer N/P type thermocouple, and the metal electrode is N-type.
  • the P-type semiconductor is connected in series with the first end, and the heat is transferred from the heat absorption end to the heat dissipation end in parallel.
  • Step 8 Referring to Figure 8 and Figure 4 in Figure 3, the surface of the 8-layer metal electrode is covered with 4 layers of the same thermal conductive material as the heat-dissipating layer 9 layer. The outermost surface height of this layer is the same as the channel, and the outermost surface is flush. In order to ensure that the source metal and the 9-layer thermal conductive material are in good contact with the bottom heat dissipation, so as not to affect the heat dissipation effect.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

提供一种晶体管，包括：半导体生长基底和半导体热电效应装置，半导体热电效应装置包含半导体化合物层（2）、金属层（3）、导热层（4）、热电偶导热装置和散热层（9），半导体化合物层（2）生长在半导体生长基底上，金属层（3）生长在半导体化合物层（2）上，导热层（4）生长在金属层（3）上，热电偶导热装置生长在导热层（4）上，散热层（9）生长在与导热层（4）相对的热电偶导热装置的另一面上，热电偶导热装置还包含供电臂（5），供电臂（5）生长在导热层（4）上，与热电偶导热装置电连接。该设置能够将晶体管的热快速导出并散发出去，显著的提高了功放管及其周围器件的可靠性，对高温下功放的性能指标有很大改善，同时能提升设备的使用寿命，提高竞争力。

Description

一种晶体管、 晶体管的散热结构以及晶体管的生产方法 技术领域 本发明涉及电子技术领域， 尤其涉及一种晶体管、 晶体管的散热结构以及晶体管 的生产方法。 背景技术 功率放大器是无线通讯系统、 医疗系统、 电源设备、 音响系统及军事雷达系统等 设备中不可缺少的组成部分， 主要起到对发射信号的功率进行放大的作用。 这些设备 对功率要求一般都比较高， 如无线通讯系统从几十瓦到上百瓦不等， 医疗设备能达到 上千瓦， 雷达设备甚至可以高达几千瓦。 要达到如此高的发射功率， 必须要通过大功 率功放的放大作用来完成， 而晶体管作为功率放大器的核心器件， 承受了所有功率的 放大和输出， 但限于放大器本身的工作效率， 放大后的功率并不是都作为有用信号输 出， 比如一般通讯系统中功放有用信号的功率只有 40%左右， 另外约 60%的功率以热 的形式存在， 其中小部分热量会传递到周围空气中， 对系统不会造成大的影响； 而大 部分热量集中在功放管管芯及其周围器件中， 比如陶瓷电容、 铝电解电容等， 通常这 些器件很容易接近或超过所容许的临界温度点， 过多的热量会影响器件的性能指标和 使用寿命， 对系统可靠性造成很大伤害。 对于传统通讯设备中的大功率晶体管， 目前的散热方式是这样完成的： 如图 1所 示， 为功率放大器中传统晶体管散热装置示意图， 晶体管焊接于 PCB上， PCB固定在 铜基板上， 晶体管底部源级金属焊接在铜基板上，然后再将铜基板固定于设备外壳上， 铜基板与设备外壳之间往往会涂抹导热胶或加导热衬垫等接触物， 热量从管芯通过源 级金属传递到铜基板， 再通过导热胶传递到设备外壳及散热齿上， 然后和周围环境形 成热交换。 功率晶体管与设备外壳之间的热阻受多方面的影响， 比如管子的焊接效果、 功放 铜基板的热阻、导热胶的均勾程度等等都会导致热阻变大， 从而造成热传递效率很低， 热量不能及时导出，达到热平衡后晶体管的管芯温度很高，而且热量会很快传导到 PCB 上的其它器件， 令其它器件受热而影响性能和寿命； 另外， 设备外壳上散热齿很多， 增大了整个设备的体积， 降低了竞争优势。
Peltier (珀尔帖） 效应被称为半导体热电第二效应， 基于此效应制备的热电偶制 冷装置已在业界很多领域得到应用， 它具有许多优点， 如： 快速制冷、 制热； 实现温 度控制容差在正负 0.1°C 以内； 结构紧凑并重量轻、 无噪音、 可靠； 多级级联能达到 100°C 以上的温差等。 但目前对此制冷设备全是作为附属部件来外置使用的， 需要额 外购买和安装， 特别是在大功率功放散热方面始终没有得到应用。 发明内容 本发明实施例提供了一种晶体管、 晶体管的散热装置以及该晶体管的生产方法， 以解决现有技术中晶体管的散热问题。 本发明实施例提供的技术方案如下： 一种晶体管， 包括： 半导体生长基底和半导体热电效应装置， 半导体热电效应装 置包含半导体化合物层、 金属层、 导热层、 热电偶导热装置和散热层， 半导体化合物 层生长在半导体生长基底上， 金属层生长在半导体化合物层上， 导热层生长在金属层 上， 热电偶导热装置生长在导热层上， 散热层生长在与导热层相对的热电偶导热装置 的另一面上， 热电偶导热装置还包含供电臂， 供电臂生长在导热层上， 与热电偶导热 装置电连接。 优选地， 热电偶导热装置包含成组的 N型热电偶和 P型热电偶， 在金属层上设置 有多条依次排列的沟道， 沟道的开口位于金属层和半导体化合物层结合面的相对面， 导热层生长于沟道的底部， 导热层上沿沟道生长多组 N型热电偶和 P型热电偶， 每组 中的 N型热电偶和 P型热电偶电连接， 相邻组中的 N型热电偶与 P型热电偶电连接， 形成 N型热电偶—P型热电偶—N型热电偶的通路， 供电臂分别与每个沟道一端的 N 型热电偶以及每个沟道另一端的 P型热电偶电连接。 优选地， 热电偶导热装置还包括第一供电电极和第二供电电极， 第一供电电极生 长在沟道中的导热层上相邻组的 N型热电偶与 P型热电偶顶部及之间的位置上， 电连 接相邻组中的 N型热电偶与 P型热电偶；第二供电电极生长在每组的 N型热电偶与 P 型热电偶底部及之间的位置上， 电连接每组中的 N型热电偶和 P型热电偶。 优选地， 热电偶导热装置还包括温度检测点， 温度检测点生长在金属层上的导热 层上。 一种晶体管的散热结构， 包括： 印刷电路板、 散热齿基板和晶体管， 印刷电路板 贴装在散热齿基板上， 晶体管与印刷电路板连接， 晶体管包括半导体生长基底和半导 体热电效应装置， 半导体热电效应装置包含半导体化合物层、 金属层、 导热层热电偶 导热装置和散热层， 半导体化合物层生长在半导体生长基底上， 金属层生长在半导体 化合物层上， 导热层生长在金属层上， 热电偶导热装置生长在导热层上， 散热层生长 在与导热层相对的热电偶导热装置的另一面上， 晶体管的金属层与散热齿基板上的散 热齿焊接， 散热层与散热齿接触，热电偶导热装置还包含供电臂， 供电臂生长在导热层 上， 与热电偶导热装置电连接。 优选地， 热电偶导热装置包含成组的 N型热电偶和 P型热电偶， 在金属层上设置 有多条依次排列的沟道， 沟道的开口位于金属层和半导体化合物层结合面的相对面， 导热层生长于沟道的底部， 导热层上沿沟道生长多组 N型热电偶和 P型热电偶， 每组 中的 N型热电偶和 P型热电偶电连接， 相邻组中的 N型热电偶与 P型热电偶电连接， 形成 N型热电偶—P型热电偶—N型热电偶的通路， 供电臂分别与每个沟道一端的 N 型热电偶以及每个沟道另一端的 P型热电偶电连接。 优选地， 热电偶导热装置还包括第一供电电极和第二供电电极， 第一供电电极生 长在沟道中的导热层上相邻组的 N型热电偶与 P型热电偶顶部及之间的位置上， 电连 接相邻组中的 N型热电偶与 P型热电偶；第二供电电极生长在每组的 N型热电偶与 P 型热电偶底部及之间的位置上， 电连接每组中的 N型热电偶和 P型热电偶。 优选地， 散热结构还包括直流供电装置和温度检测及控制芯片， 热电偶导热装置 还包括温度检测点， 温度检测点生长在金属层上的导热层上， 温度检测及控制芯片分 别与温度检测点和直流供电装置连接。 一种晶体管的生产方法， 包括下述步骤： a. 提供生长基底层， 生长出基底以上的部分， 包括导电沟道、 掺杂区域、 半导体 氧化物、 供电电极等， b. 在半导体生长基底层上生长一层半导体化合物层， c 在化合物层表面外延生长一层金属薄膜， 通过气相沉积技术在金属与半导体结 合的界面上形成金属层， 在金属层上蚀刻出多条规则排列的沟道， 沟道的开口位于金 属层和半导体化合物层结合面的相对面， d. 利用气相沉积技术， 在沟道底部生长出导热层， e. 采用电镀或者气相沉积技术在导热层表层外延生长出供电臂、 第一供电电极， 供电臂和第一供电电极为各个独立的部分， f. 在第一供电电极表面外延生长出 N/P电偶半导体层， 此后采用高温扩散和离子 注入法对半导体材料进行掺杂， 从而生成相间排列的 N型和 P型热电偶， g. 在热电偶半导体层 N/P型热电偶与第一供电电极相对的一端采用气相沉积技术 或电镀方法外延生长出第二供电电极， H. 在第二供电电极表面覆盖导热层。 优选地， 供电臂和第一供电电极加工为高度相等的各个独立部分。 优选地， 导热层和散热层使用相同的导热材料， 散热层最外表面高度和沟道最外 表面平齐。 优选地， 其特征在于采用电镀或者气相沉积技术， 在导热层外延生长出作为温度 检测点的导电金属薄膜层。 综上所述， 本发明实施例能够将晶体管的热快速导出并散发出去， 能够显著的提 高功放管及其周围器件的可靠性， 对高温下功放的性能指标也会有很大改善， 同时能 提升设备的使用寿命， 提高竞争力。 附图说明 图 1是传统晶体管散热装置示意图； 图 2是根据本发明实施例的基于帕尔贴效应的新型晶体管示意图； 图 3是根据本发明实施例的新型晶体管半导体工艺制作流程图； 图 4是根据本发明实施例的晶体管侧面 A-A切面示意图； 图 5是根据本发明实施例的晶体管底部 B-B切面示意图； 以及 图 6是根据本发明实施例的晶体管的散热应用示例示意图。 具体实施方式 本发明基于传统 LDMOSFET (横向扩散金属氧化物半导体）晶体管基本结构， 结 合目前半导体加工工艺技术 （如外延生长技术、 气相沉积技术等）， 将半导体 Peltier 效应应用到传统场效应晶体管结构中，由此提出了一种新型的快速导热的晶体管结构， 解决传统晶体管的导热问题。 本发明的晶体管一方面保留了现有管子的贴装方式以方 便使用， 另一方面能将管芯热量快速导出到散热齿， 并可以将温度控制在一定范围内。 与传统半导体热电偶制冷装置使用方式不同的是， 本发明采用半导体外延生长工艺， 将半导体热电偶及散热装置与场效应晶体管结合在一起， 形成一体化生长结构， 减少 了不必要的热阻影响， 从外观来看有完整的封装结构， 并且和传统晶体管有相同的贴 装方式， 优势是导热效果更佳， 并且温度可以检测和控制。 如图 2所示， 在半导体生长基底上， 采用传统的晶体管加工工艺， 生长出晶体管 工作所必须的导电沟道、 掺杂区域、 半导体氧化物、 金属电极等。 图 2所示下半部分， 是半导体热电效应装置与半导体基底结合后的示意图。 如图 4所示为 A-A切面示意图， ①层为半导体生长基底。 ②层为在半导体基底上 生长的半导体化合物。 根据金属 /半导体界面形成机理， 在②层半导体化合物上形成金 属生长层薄膜， 比如过渡磁性金属 Mn、 Cu等， 在此金属薄膜上面再形成一层厚的金 属层③层， ③层作为晶体管的源极接地金属， 并作为晶体管的传热金属层。 导热层④ 层和散热层⑨层起到传热和隔离的作用， 要求具有很好的导热性和热稳定性， 比如氮 化铝、 氧化铍等物质； ④层作为吸热端， 吸收晶体管底部热量， 同时起到隔离源级金 属层和热电偶供电极的作用； ⑨层散热端将热电偶传导的热量再传递给外部散热器。 ⑤层为热电偶正负极供电臂， 通过焊接与电源正负极相连。 第一供电电极⑥层和第二 供电电极⑧层为 N/P型热电偶的供电电极， 将 N/P型热电偶首尾串接起来， 形成电流 的流通。 ⑤、 ⑥、 ⑧层为各个独立的部分， ⑤和⑥高度相等， ⑤层为直流电源供电所 需的两个电臂； ⑥层和⑧层分别在 N/P热电偶极子的两端， 每层由相互独立的金属电 极组成， 电极连接相邻的 N型和 P型热电偶极子的两个电极， ⑥层和⑧层之间又通过 N型或 P型热电偶极子相连； 这样⑤层、 ⑥层和⑧层便组成了一个电流通路。
⑦层为 N/P型热电偶层， 由半导体掺杂工艺形成，环路中电流从 N→P→N依次流 动， 将热量从吸热端转移到散热端， 吸收热量的多少与电流大小和热电偶数量有关。 图 5中⑩点为温度检测点， 与温度检测芯片连通， 用于检测晶体管底部温度， 并控制 N/P型热电偶层两端的电流大小。 如图 5所示为晶体管底部 B-B切面示意图， 源级金属和 N/P热电偶相间排列， 既 能满足源级金属的接地要求， 又能满足热电偶的供电和散热要求。 图 2中 N/P型热电偶单层使用时，④层吸热端和⑨层散热端的温差可以到达 71°C， 多层使用时温差能达到 131°C， 最大功率耗散可达 300W。 本发明所述散热装置适合于导电沟道与接地面平行的晶体管， 以使热量能最大效 率的散出；本发明不限定半导体生长基底的类型，可以适应于 Si衬底 MOSFET、 GaAs MESFET、 GaN FET等场效应晶体管， 其它还有锗化硅、磷化铟等半导体衬底晶体管， 这些晶体管的特点是源级金属与导电沟道平行，并且源级金属紧贴于接地面和散热面。 如图 6所示为晶体管的散热应用示例。 PCB装贴于散热齿基板上， 散热齿基板为 整机设备壳体的一部分， 将晶体管栅极和漏极焊接于 PCB上， 底部源极金属与下方散 热齿良好焊接， 图 4中⑨层散热端与散热齿达到良好接触， 图 4中⑤层的正负供电极 通过导线与 PCB上电源相连， 图 5中温度检测点⑩处可以焊接导线， 导线穿过散热齿 与 PCB上的温度检测芯片接通，也可以将导线从管体内部引出形成端子并与连线相接 通。 晶体管产生的绝大部分热量由 N/P热电偶传导到散热齿上， 然后通过外部风扇将 散热齿上的热量吹散到周围空气中（风扇也可以装配到整机设备的外壳上面）， 也可以 通过水冷或其它方式等达到同样的散热效果， 这样绝大部分的热量便通过此种途径散 发掉， 小部分的热量还会通过散热齿传导到 PCB上， 但对器件影响已经很小。温度检 测芯片实时检测图 4中④层吸热端的温度， 并通过温度和电流对应关系 （使用前通过 试验采数方式获得），来达到对电流大小的自动控制，从而控制 N/P热电偶的导热效率， 以使晶体管温度控制在规定的范围之内。 为达到更好的导热效果， 可以增大晶体管底部的面积， 以增加 N/P热电偶极子的 数量， 更高效的将热量导出。 N/P热电偶极子的高度建议设置在 2.5mm~4mm之间， 如果高度太小， 热电偶材料中掺杂电荷量太少会影响导热效果； 如果高度太大， 源级 金属散热齿的长度会相应增大， 会影响源级接地效果， 特别是对高频工作的晶体管， 这种影响会更明显。 另外， 还可以通过其它方式来提高导热效果， 比如对于低频工作 的大功率晶体管， 可以制作多层 N/P热电偶极子层叠加的方式来加强导热性能， 但对 高频晶体管不建议采用多层的方式（除非在不影响源级接地效果的情况下）； 或者加工 成其它的形状， 比如折叠形式、 弯曲形式等， 晶体管上方壳体也可以进行生长， 以增 加导热通道和面积， 具体方式要根据系统设备及散热条件来扩展和约束。 如图 3所示， 是本发明新型晶体管半导体工艺制作流程图， 下面结合流程图 3和 切面图 4、 5， 对制作的实施方式进行详细分解描述。 在此说明， 下列所示出和描述的 半导体加工工艺和技术， 只是实现新型晶体管结构的一种途径， 允许用不同的或新的 半导体加工技术和处理工艺来实现此结构， 在各步骤之前或之后允许有更详细的工艺 细节和处理步骤。 步骤一： 晶体管放大功能区域的加工， 参考图 3中的框 1， 并参考图 4中的结构 示意图， 首先提供生长基底①层， 比如单晶硅、 碳化硅、 砷化镓等常见衬底材料， 按 照传统半导体工艺技术， 生长出基底以上的部分， 包括导电沟道、 掺杂区域、 半导体 氧化物、 供电电极等。 步骤二： 从本步骤开始进行晶体管导热功能区域的加工， 参考图 3中的框 2和结 构图 4， 在半导体生长基底上优先生长一层半导体化合物层②， 此化合物层要求导热 效率高、 热稳定性好， 而且利于下面金属薄膜外延层的生长， 比如 IV-VI族化合物等。 步骤三： 参考图 3中的框 3和结构图 4， 在②层化合物表面外延生长一层金属薄 膜， 形成金属 /IV-VI族半导体界面， 金属材料可以与栅极和漏极相同， 也可以不同， 但必须是良好的导电导热材料。通过气相沉积技术在金属 /半导体界面上形成纯度比较 高的厚金属层③层， 作为源级接地金属层和传热层； 然后将源级金属层蚀刻出多条规 则排列的沟道 H， 以供 N/P热电偶生长所用。 步骤四： 参考图 3中的框 4和结构图 4， 在步骤三的基础上同样利用气相沉积技 术， 可以在源级金属沟道表面生长导热效果很好的导热层④层， 如氧化铍、氮化铝等， 气相沉积技术可以有效控制化合物的密度和纯度。 步骤五： 参考图 3中的框 5和结构图 4、 5， 在步骤四描述的金属沟道内的导热化 合物表层， 采用电镀或者气相沉积技术， 外延生长出导电金属薄膜作为⑤、⑥和⑩层， 生长过程中用模具将无金属层部分挡住， 只在需要的地方形成金属层， ⑩层为温度检 测点。 步骤六： 参考图 3中的框 6和结构图 4， 在⑥层基础上外延生长出热电偶半导体 材料⑦层， 一般常用的为碲化铋化合物半导体材料， 然后采用高温扩散和离子注入法 对半导体材料进行掺杂， 从而生成相间排列的 N型和 P型热电偶。 步骤七： 参考图 3中的框 7和结构图 4， 在⑦层 N/P型热电偶顶部采用气相沉积 技术或电镀方法外延生长出金属薄膜作为第二供电电极层⑧， 金属电极将 N型和 P型 半导体首尾串联相接， 而热量以并行的方式从吸热端被传递到散热端。 步骤八： 参考图 3中的框 8和结构图 4， 在⑧层金属电极表面覆盖和④层相同的 导热材料作为散热层⑨层， 此层最外表面高度和沟道， 最外表面平齐， 以保证源级金 属和⑨层导热材料与底部散热良好接触， 以免影响散热效果。

Claims

权 利 要 求 书
1. 一种晶体管， 包括： 半导体生长基底和半导体热电效应装置， 所述半导体热电 效应装置包含半导体化合物层 （2)、 金属层 （3 )、 导热层 （4)、 热电偶导热装 置和散热层（9)， 所述半导体化合物层（2)生长在所述半导体生长基底上， 所 述金属层 （3 ) 生长在所述半导体化合物层（2)上， 所述导热层 （4)生长在所 述金属层 （3 ) 上， 所述热电偶导热装置生长在所述导热层 （4) 上， 所述散热 层 （9) 生长在与所述导热层 （4) 相对的所述热电偶导热装置的另一面上， 所 述热电偶导热装置还包含供电臂 （5 )， 所述供电臂 （5 )生长在所述导热层（4) 上， 与热电偶导热装置电连接。
2. 如权利要求 1所述的晶体管， 其中， 所述热电偶导热装置包含成组的 N型热电 偶和 P型热电偶， 在所述金属层 （3 ) 上设置有多条依次排列的沟道 （11 )， 所 述沟道 （11 ) 的开口位于所述金属层 （3 ) 和所述半导体化合物层 （2) 结合面 的相对面， 所述导热层 （4) 生长于所述沟道 （11 ) 的底部， 所述导热层 （4) 上沿所述沟道（11 )生长多组所述 N型热电偶和 P型热电偶， 每组中的 N型热 电偶和 P型热电偶电连接， 相邻组中的 N型热电偶与 P型热电偶电连接， 形成 N型热电偶—P型热电偶—N型热电偶的通路， 所述供电臂 （5 )分别与每个所 述沟道 （11 ) 一端的 N型热电偶以及每个所述沟道 （11 ) 另一端的 P型热电偶 电连接。
3. 如权利要求 2所述的晶体管， 其中， 所述热电偶导热装置还包括第一供电电极
(6) 和第二供电电极 （8)， 所述第一供电电极 （6) 生长在所述沟道 （11 ) 中 的导热层 （4) 上相邻组的 N型热电偶与 P型热电偶顶部及之间的位置上， 电 连接相邻组中的 N型热电偶与 P型热电偶； 所述第二供电电极 （8) 生长在每 组的 N型热电偶与 P型热电偶底部及之间的位置上，电连接每组中的 N型热电 偶和 P型热电偶。
4. 如权利要求 1至 3任一项所述晶体管， 其中， 所述热电偶导热装置还包括温度 检测点 （10)， 所述温度检测点 （10) 生长在所述金属层 （3 ) 上的所述导热层
(4) 上。
5. 一种晶体管的散热结构， 包括： 印刷电路板、 散热齿基板和晶体管， 所述印刷 电路板贴装在所述散热齿基板上， 所述晶体管与所述印刷电路板连接， 所述晶 体管包括半导体生长基底和半导体热电效应装置， 所述半导体热电效应装置包 含半导体化合物层（2)、金属层（3 )、导热层（4)热电偶导热装置和散热层（9)， 所述半导体化合物层 （2) 生长在所述半导体生长基底上， 所述金属层 （3 ) 生 长在所述半导体化合物层（2)上， 所述导热层（4)生长在所述金属层（3 )上， 所述热电偶导热装置生长在所述导热层 （4) 上， 所述散热层 （9) 生长在与所 述导热层（4)相对的所述热电偶导热装置的另一面上，所述晶体管的金属层（3 ) 与所述散热齿基板上的散热齿焊接， 所述散热层 （9) 与所述散热齿接触,所述 热电偶导热装置还包含供电臂 （5 )， 所述供电臂 （5 ) 生长在所述导热层 （4) 上， 与热电偶导热装置电连接。
6. 如权利要求 5所述的晶体管的散热结构， 其中， 所述热电偶导热装置包含成组 的 N型热电偶和 P型热电偶， 在所述金属层 （3 ) 上设置有多条依次排列的沟 道 （11 )， 所述沟道 （11 ) 的开口位于所述金属层 （3 ) 和所述半导体化合物层
(2) 结合面的相对面， 所述导热层 （4) 生长于所述沟道 （11 ) 的底部， 所述 导热层 （4) 上沿所述沟道 （11 ) 生长多组所述 N型热电偶和 P型热电偶， 每 组中的 N型热电偶和 P型热电偶电连接， 相邻组中的 N型热电偶与 P型热电 偶电连接，形成 N型热电偶—P型热电偶—N型热电偶的通路，所述供电臂（5 ) 分别与每个沟道 （11 ) 一端的 N型热电偶以及每个沟道 （11 ) 另一端的 P型热 电偶电连接。
7. 如权利要求 6所述的晶体管的散热结构， 其中， 所述热电偶导热装置还包括第 一供电电极 （6) 和第二供电电极 （8)， 所述第一供电电极 （6) 生长在所述沟 道 （11 ) 中的导热层 （4) 上相邻组的 N型热电偶与 P型热电偶顶部及之间的 位置上， 电连接相邻组中的 N型热电偶与 P型热电偶； 所述第二供电电极（8) 生长在每组的 N型热电偶与 P型热电偶底部及之间的位置上， 电连接每组中的 N型热电偶和 P型热电偶。
8. 如权利要求 5至 7任一项所述的晶体管的散热结构， 还包括直流供电装置和温 度检测及控制芯片， 所述热电偶导热装置还包括温度检测点（10)， 所述温度检 测点生长在所述金属层 （3 ) 上的所述导热层 （4) 上， 其中， 所述温度检测及 控制芯片分别与所述温度检测点 （10) 和所述直流供电装置连接。
9. 一种晶体管的生产方法， 包括下述步骤：
提供生长基底层（1 )， 生长出基底以上的部分， 包括导电沟道（11 )、 掺杂 区域、 半导体氧化物、 供电电极等；
在所述半导体生长基底层 （1 ) 上生长一层半导体化合物层 （2) ； 在所述化合物层（2)表面外延生长一层金属薄膜， 通过气相沉积技术在金 属与半导体结合的界面上形成金属层（3 )， 在所述金属层（3 )上蚀刻出多条规 则排列的沟道 （11 )， 所述沟道 （11 ) 的开口位于所述金属层 （3 ) 和所述半导 体化合物层 （2) 结合面的相对面;'
利用气相沉积技术， 在沟道 （11 ) 底部生长出导热层 （4) ；
采用电镀或者气相沉积技术在所述导热层（4)表层外延生长出供电臂（5 )、 第一供电电极 （6)， 所述供电臂 （5 ) 和所述第一供电电极 （6) 为各个独立的 部分；
在所述第一供电电极 （6) 表面外延生长出 N/P 电偶半导体层 （7)， 此后 采用高温扩散和离子注入法对半导体材料进行掺杂， 从而生成相间排列的 N型 和 P型热电偶；
在所述热电偶半导体层 （7) N/P型热电偶与所述第一供电电极 （6) 相对 的一端采用气相沉积技术或电镀方法外延生长出第二供电电极 （8) ；
在所述第二供电电极 （8) 表面覆盖导热层 （9)。
10. 如权利要求 9所述的一种晶体管的生产方法， 还包括将所述
供电臂 （5 ) 和所述第一供电电极 （6) 加工为高度相等的各个独立部分。
11. 如权利要求 10所述的一种晶体管的生产方法， 其中， 所述导热层 （4) 和散热 层 （9) 使用相同的导热材料， 所述散热层 （9) 最外表面高度和沟道 （11 ) 最 外表面平齐。
12. 如权利要求 9至 11任一项所述的晶体管的生产方法，还包括采用电镀或者气相 沉积技术， 在所述导热层（4)外延生长出作为温度检测点 （10) 的导电金属薄 膜层。
PCT/CN2013/082154 2012-12-19 2013-08-23 一种晶体管、晶体管的散热结构以及晶体管的生产方法 Ceased WO2014094450A1 (zh)

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