WO2014139860A1 - Composant optoélectronique, module lumineux et projecteur de véhicule automobile - Google Patents

Composant optoélectronique, module lumineux et projecteur de véhicule automobile Download PDF

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Publication number
WO2014139860A1
WO2014139860A1 PCT/EP2014/054369 EP2014054369W WO2014139860A1 WO 2014139860 A1 WO2014139860 A1 WO 2014139860A1 EP 2014054369 W EP2014054369 W EP 2014054369W WO 2014139860 A1 WO2014139860 A1 WO 2014139860A1
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WIPO (PCT)
Prior art keywords
conductive layer
component
layer
region
stacking direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2014/054369
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German (de)
English (en)
Inventor
Frank Singer
Andreas Reith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Priority to DE112014001265.3T priority Critical patent/DE112014001265A5/de
Publication of WO2014139860A1 publication Critical patent/WO2014139860A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/852—Encapsulations
    • H10H20/853—Encapsulations characterised by their shape
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S41/00—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps
    • F21S41/10—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by the light source
    • F21S41/14—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by the light source characterised by the type of light source
    • F21S41/141—Light emitting diodes [LED]
    • F21S41/151—Light emitting diodes [LED] arranged in one or more lines
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S41/00—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps
    • F21S41/10—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by the light source
    • F21S41/19—Attachment of light sources or lamp holders
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S45/00—Arrangements within vehicle lighting devices specially adapted for vehicle exteriors, for purposes other than emission or distribution of light
    • F21S45/40—Cooling of lighting devices
    • F21S45/47—Passive cooling, e.g. using fins, thermal conductive elements or openings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H10H20/8582—Means for heat extraction or cooling characterised by their shape

Definitions

  • the invention relates to an optoelectronic component, an optoelectronic light-emitting module with such a component ⁇ as a motor vehicle headlight with such a component.
  • aluminum nitride ceramics with metal tracks are frequently used in order to realize a series connection of a plurality of optoelectronic semiconductor chips (in particular LED chips).
  • These aluminum ⁇ nitride ceramics are conventionally coupled, for example, with metal core circuit boards, by means of which the structure is coupled with egg NEM heat sink.
  • an optoelectronic device suits ⁇ ben, which is simple and stable. It is further worth ⁇ wishing to provide an optoelectronic light emitting module, which is constructed a ⁇ times and has good heat dissipation.
  • the invention is characterized by a component and a lighting module having at least one such component.
  • an optoelectronic component comprises a flat-extended carrier having a first conductive layer and a second conductive layer. Between the first and the second conductive layer, an intermediate layer is arranged.
  • the intermediate ⁇ layer comprises silicon nitride.
  • the intermediate layer comprises in particular Si 3 4 .
  • the intermediate layer can essentially be formed of silicon nitride.
  • the intermediate layer may contain at least 95%, preferably at least 98%, of silicon nitride.
  • the intermediate ⁇ layer consists of silicon nitride.
  • the first conductive layer, the intermediate layer and the second conductive layer are arranged in a stacking direction in egg ⁇ nem layer stack.
  • the first conductive layer has a first surface for supporting the component on a substrate.
  • a first region of the second conductive layer extends to a first plane.
  • the first plane is spaced in the stacking direction to the first surface.
  • a second region of the second conductive layer extends to a second level.
  • the second level is further spaced apart in the stacking direction from the first level than the first level.
  • At least one optoelectronic semiconductor chip is attached to the first region of the second conductive layer.
  • the first conductive layer, the intermediate layer and / or the second conductive layer each have a uniform thickness in the stacking direction.
  • the intermediate layer is formed in egg ⁇ ner plane and having a uniform thickness equal ⁇ in the stacking direction.
  • the intermediate layer has no elevations and reductions ⁇ .
  • the intermediate layer may be free of cavities. This may mean that the interim ⁇ rule layer has no recesses and in particular not gen surrounds the optoelectronic semiconductor chip in lateral direc- but clergys extends in the stacking direction underneath the optoelectronic semiconductor chip.
  • the semiconductor chip is, in particular, a light-emitting diode which, for example, comprises a semiconductor layer sequence based on a III-V semiconductor material such as GaN.
  • the semiconductor chip is in particular designed to generate electromagnetic radiation during operation of the component, in particular white or colored light.
  • the semiconductor chip is mounted on the second conductive layer and electrically connected to the conductive layer. When a plurality of semiconductor chips arranged, these are, for example, electrically connected in series or parallel ge ⁇ on.
  • the first and second conductive layers are electrically and / or thermally conductive.
  • the first and second conductive layers comprise in particular copper. According exporting approximately ⁇ example, the first and second conductive layer each comprise other materials such as gold.
  • the optoelectronic component has a high breaking strength.
  • the component has the high breaking strength especially without further reinforcing
  • Layers such as metal core circuit boards. This makes it possible, for example, to mount the component directly on adekör ⁇ per. In particular, the component can be screwed directly onto the heat sink.
  • the conductive layers on both sides of the silicon nitride layer protecting the Silizi ⁇ umnitrid rappel against excessive mechanical stresses.
  • silicon nitride as the material for the intermediate layer can bring about the following advantages in comparison with customary materials, such as aluminum nitride or aluminum oxide.
  • the thermal conductivity of silicon nitride is only insignificantly lower than the thermal conductivity of silicon nitride Aluminum nitride and much higher than the thermal conductivity of alumina.
  • Silicon nitride is also characterized by high mechanical and chemical robustness and a high modulus of elasticity. This sometimes allows USAGE ⁇ -making of screw connections, which pass through the silicon nitride therethrough. This makes it possible that no connecting layer, such as an adhesive layer, which conducts heat poorly between the component and thedekör ⁇ per necessary.
  • silicon nitride can be applied directly with a heat sink formed of copper due to its increased compared to aluminum ⁇ umnitrid expansion coefficient.
  • common materials such as aluminum nitride, this can lead to tensions and cracks in the ceramic. This makes it possible to dispense with connecting elements that would worsen the thermal connection of the building ⁇ part with the heat sink and, accordingly, the removal of heat generated during operation of the component heat.
  • the second conductive layer has the first and second regions .
  • the second conductive layer is thinner than in the second region.
  • the first region is used in particular for electrical contacting of the at least one semiconductor chip.
  • the second region is used in particular ⁇ sondere as a frame around the first region.
  • the second area serves in particular as protection for the intermediate layer. If a screw connection is provided, the second conductive layer in the second region dampens the mechanical loading of the screw on the intermediate layer. Thus, a simple and robust optoelectronic component ⁇ part can be realized.
  • the thermal resistance is low.
  • the semiconductor chip extends to a third level.
  • the third level is in stack ⁇ direction between the first and the second plane.
  • a high utilization of the radiation of the opto-electronic semiconductor chip is possible.
  • the second conductive layer has a region projecting transversely to the stacking direction via the intermediate layer.
  • the projecting area can be used in particular as a plug for making electrical contact with the component.
  • the carrier has a recess for fastening the component on the ground.
  • the recess extends through the first conductive layer, the intermediate layer and the second conductive layer. Through the recess, it is possible to fix the optoelectronic component di ⁇ rectly with the carrier to the ground, in ⁇ example, in the screw or other fasteners are passed through the recess.
  • the thickness of the first conductive layer and / or the second conductive layer in the stacking direction is particularly evident between 0.1 mm and 0.6 mm inclusive.
  • the thickness of the second region of the second conductive layer is 0.15 mm, 0.2 mm, 0.25 mm, 0.3 mm, 0.4 mm or 0.5 mm.
  • the intermediate layer has, according to further embodiments, a fracture toughness of greater than 4.0 MPaVm. Due to the high fracture toughness, it is possible to couple the carrier directly to the ground, in particular to screw. In particular ⁇ sondere the intermediate layer has a bending strength greater than 800 MPa. For example, the intermediate layer ⁇ a flexural strength of 850 MPa and a fracture toughness of 5 MPaVm. In particular, the intermediate layer has a fracture toughness and / or flexural strength each greater than that of aluminum nitride.
  • the component comprises a potting which covers the at least one semiconductor chip and is limited at least in places transversely to the stacking direction by the second region of the second conductive layer.
  • the second conductive layer serves as a boundary for the encapsulation, so that the encapsulation is arranged in the first region of the second conductive layer which covers at least one semiconductor chip and does not flow onto the second region of the second conductive layer.
  • the component has a web, which at the first region of the second conductive
  • an optoelectronic light-emitting module comprises a heat sink.
  • the light emitting module comprises a component, such as described in connection with one or more ⁇ rer of the above embodiments.
  • the component is coupled to the first conductive layer with the cooling body.
  • the first conductive layer is in accordance with embodiments min ⁇ least locally in direct contact with the cooling ⁇ body.
  • no adhesive is present between the first conductive layer and the heat sink, for example
  • the first conductive layer is in direct contact with the heat sink with the first surface.
  • the component is with the
  • the component is coupled to the heat sink by means of an adhesive connection.
  • a motor vehicle headlight is specified.
  • the motor vehicle headlight has at least one optoelectronic component, as described in conjunction with one or more of the abovementioned embodiments.
  • the motor vehicle headlight has at least one optoelectronic light-emitting module, as described in conjunction with one or more of the abovementioned embodiments.
  • FIG. 1A and 1B is a schematic representation of an opto ⁇ electronic component or lighting module according to an embodiment
  • FIG. 2 shows a schematic representation of an optoelectronic component according to an embodiment
  • Figure 3 is a schematic representation of a bottom view ei ⁇ nes optoelectronic device according to one embodiment
  • FIG. 4 shows a schematic representation of an optoelectronic component according to an embodiment
  • FIG. 5 is a schematic representation of a bottom view ei ⁇ nes optoelectronic device according to one embodiment
  • FIG. 6 shows a schematic representation of an optoelectronic component according to an embodiment
  • Figure 7 is a schematic representation of a detail view ei ⁇ nes optoelectronic device according to one embodiment
  • Figure 8 is a schematic representation of a detail view ei ⁇ nes optoelectronic device according to one embodiment
  • FIG. 9 shows a schematic illustration of an optoelectronic component according to an embodiment
  • FIG. 10 shows a schematic representation of a rear view of an optoelectronic device according to an embodiment
  • Figure 11 is a schematic representation of a sectional view of an optoelectronic device according to one embodiment ⁇ form,
  • FIGS . 13A and 13B shows a schematic illustration of a screw connection according to an embodiment
  • FIGS. 14A to 14C are schematic representations of an opto ⁇ electronic component according to an embodiment.
  • FIGS. 15A and 15B are schematic representations of an optoelectronic device according to one embodiment.
  • Figure 1A shows a schematic representation of a optoelekt ⁇ tronic component 100.
  • the optoelectronic device 100 includes a carrier 101 which has a first conductive layer 102, an intermediate layer 103 and a second conductive layer 105th
  • the first conductive layer 102, intermediate layer 103 and the second conductive layer 105 are arranged in a stack direction S as a layer stack aufei ⁇ Nander 106th
  • the first conductive layer has a first surface 107 on the side facing away from the intermediate layer.
  • the first surface 107 is configured to be disposed on a substrate 108.
  • Figure 1B shows include an optoelectronics light emitting module 121, comprising device 100 and a sub ⁇ basic heatsink 122nd
  • the second conductive layer 105 is arranged on a side of the intermediate layer 103 facing away from the first layer 102.
  • the second conductive layer 105 has a first region 110.
  • the first region 110 extends from the intermediate layer 103 to a first plane 109.
  • the first plane 109 is spaced from the intermediate layer 103.
  • the second conductive layer 105 has a second region 112 which extends to a second plane 111.
  • the two ⁇ te plane is spaced further apart in the slice direction S of the intermediate layer 103 as the first layer 109.
  • the second conductive layer 105 has a thickness 118 between the intermediate layer 103 and the two ⁇ th level 111 at least in the second region 112th
  • the thickness is in accordancessensbei ⁇ play between 0.1 mm and 0.6 mm. According to further embodiments, the thickness is greater than 0.6 mm.
  • a plurality of optoelectronic semiconductor chips 113 is arranged.
  • a web 120 is arranged on the first region 110.
  • the web in particular connects to the second region 112, so that the first region 110 with the semiconductor chips 113 is completely surrounded by the second region 112 and the web 120.
  • the second conductive layer 105 is interrupted in particular by an etching process into a plurality of partial regions, so that the second conductive layer 105 forms conductor tracks. Egg ne electrical contact between the tracks and the optoelectronic semiconductor chips 113 is performed example ⁇ , by bonding wires.
  • the semiconductor chips 113 are
  • ESD diode 125 is provided according to embodiments. According to further embodiments, the diode 125 is dispensed with.
  • contact regions 130 are provided in corner regions of the second conductive layer 105, in particular in the second region 112.
  • the contact portions 130 are in particular respectively removablebil ⁇ det as solder pads.
  • the interlayer 103 includes a ceramic comprising silicon nitride 104.
  • the intermediate layer 103 is made of silicon nitride.
  • the intermediate layer 103 comprises in particular S1 3 N 4 or consists of S1 3 N 4 .
  • the intermediate layer 103 has, according to embodiments, a high flexural strength and fracture toughness.
  • the flexural strength of the intermediate layer according to embodiments of greater than 600 MPa, in particular greater than 700 MPa, for example RESIZE ⁇ SSER than 800 MPa, more preferably 850 MPA +/- 1%.
  • the fracture toughness of the intermediate layer 103 is in particular greater than 3 MPaVm, for example greater than 4 MPaVm, for example 5 MPaVm +/- 1%.
  • the intermediate layer 103 has a modulus of elasticity of about 300 GPa.
  • the intermediate layer has a hardness value of 1400 according to the Vickers hardness test. According from ⁇ EMBODIMENTS 103 has a thermi ⁇ 's coefficient of expansion between 2 and 3, 5 x 10 "6 K" 1 onto the intermediate layer.
  • Layer 105 each have according to embodiments of a metal on having a good electrical and / or thermal conductivity ⁇ ness.
  • the layers 102 and 105 each comprise copper.
  • copper has a thermal expansion coefficient see in the range of about 15 x 10 "6
  • the first and second conductive layers 102, 105 each have in particular a thermal conductivity ⁇ capacity of greater than 200 W / m K, for example greater than 300 W / m K, especially 400 W / m K or more.
  • the thickness of particularly the first conductive layer 102 is selected so thick that, for example, the copper of the ers ⁇ th conductive layer 102, the heat generated during operation dissipates the semiconductor chip 113 and at the same time ⁇ different extent of the intermediate layer 103 and example ⁇ , the background 108 compensates.
  • the substrate 108 is, for example, the heat sink 122 made of aluminum or copper with a correspondingly large thermal expan ⁇ coefficients. Characterized in that the thickness is arranged first conductive layer 102 between the intermediate layer 103 with a low coefficient of thermal expansion and the heat sink 108 with a high coefficient of thermal expansion, a direct mounting of the carrier 101 on the substrate 108 mög ⁇ lich.
  • the first surface 107 of the first conductive layer 102 is, according to embodiments in direct contact with the substrate 108.
  • no silicone-based adhesive is provided between the first conductive layer 102 and the substrate 108.
  • no glue is Zvi ⁇ rule of the first conductive layer 102 and the substrate 108 is provided having a layer thickness of greater than 20 ym. Due to the fact that, according to embodiments, the first conductive layer 102 of the carrier 108 is arranged directly on the substrate 108, the thermal resistance between the carrier 101 and the substrate 108 is reduced.
  • the optoelectronic semiconductor chips 113 are covered with a potting 119 (FIG. 2).
  • the potting 110 covers in particular after installation of the
  • the potting 119 covers the exposed surfaces of the first conductive Layer 102 in a region between the second region 112 of the second conductive layer 105 and the web 120.
  • the semiconductor chip 113 extend having an upper surface 114 to a third level 115, which is between the ERS th level 109 and second level 111, it is mög ⁇ Lich, that the second area 112 of the second conductive layer 105 as Limitation for the potting 119 serves.
  • the second area 112 serves as a so-called shutter edge, which defines the separation of the illuminated area from a shaded area, especially when used as a motor vehicle headlight. Because the second region 112, which is located in the immediate vicinity of the semiconductor chips 113, is used as the shutter edge, the best possible light output of the optoelectronic component 100 is possible.
  • Figure 2 shows a schematic plan view of the opto-electro ⁇ African component 100 according to embodiments.
  • the potting 119 covers the semiconductor chips 113 and is bounded by the second region 112 and the web 120.
  • the semiconductor chips 113 can be contacted via the solder pads 126, for example.
  • FIG. 3 shows a schematic illustration of the surface 107 of the optoelectronic device 100 opposite FIG. 2 according to embodiments.
  • the carrier 101 has ⁇ example, a width 129 of about 10.5 mm.
  • the carrier 101 has, for example, a width 130 of about 7 mm.
  • the underside with the surface 107 is flat, so that the carrier 101 can be connected to the surface 107 via an adhesive connection and / or a clamping connection with the substrate 108.
  • Figure 4 shows a schematic representation of a optoelekt ⁇ tronic device 100 according to further embodiments.
  • the carrier 101 according to the embodiments of FIG. 4 has two recesses 117.
  • the recesses are surrounded by the first conductive layer 102, the intermediate layer 103 and the second conductive layer 105 such that the recesses 117 each extend from one side of the carrier 101 to the opposite side of the carrier 101, in particular the surface 107.
  • the Ausappelun ⁇ gen 117 are for example arranged in the edge region of the carrier 117 one hundred and first In particular, the recesses 117 are arranged in the second region 112 of the second conductive layer 105.
  • the recesses are introduced, for example, by drilling into the layer stack 106.
  • the optoelectronic component 100 can be coupled to the substrate 108, for example by means of a screw connection 123 (FIGS. 13A and B).
  • the semiconductor chips 113 are by means of the solder pads 126
  • the semiconductor chip 113 can be controlled individually, it is JE but also possible that the semiconductor chips 113 are ge ⁇ connected in series, or in groups driven.
  • FIG. 5 shows a schematic illustration of the lower side of the optoelectronic component 100 according to the embodiments of FIG. 4.
  • the surface 107 is interrupted by recesses 127, so that three electrically and thermally isolated regions are formed.
  • the recesses 117 are respectively disposed on the sides of the recesses 127, the facing away from the central region of the surface 107.
  • the central region 107 corresponds to the area of the two ⁇ th conductive layer 105 on which the semiconductor chips are arranged 113th
  • FIG. 6 shows the optoelectronic component 100 according to further embodiments.
  • the optoelectronic device 100 in accordance with the embodiments of Figure 6 projecting portions 116 of the second leitfähi ⁇ gen layer 105th
  • the protruding portions are arranged on a component 100 116, having the Ausneh ⁇ rules 117th
  • the projecting portions 116 are arranged on a component without the recesses 117, as explained in connection with the figures 1 to 3.
  • the projecting portions 116 project across the intermediate layer 103 transversely to the stacking direction S.
  • the protruding portions 116 project beyond the intermediate layer 103 and the first conductive layer 102 according to other embodiments.
  • the projecting areas 116 are used for electrical contacting of the component 100.
  • the projecting areas 116 are designed, for example, as plugs. According to embodiments, the solder joints 126 can be dispensed with.
  • the protruding portions 116 are in accordance with embodiments part of the second region 112 of the second conductive layer 105.
  • Figure 6 shows the component 100 prior to mounting the semiconductor ⁇ chips 113.
  • the first region 110 of the second conductive layer 105 is set back in relation to the second Be ⁇ rich 112.
  • FIG. 7 shows a schematic detail view of the optoelekt ⁇ tronic component 100 according to embodiments.
  • the optoelectronic semiconductor chips 113 are arranged without potting on the first region 110 of the second conductive layer 105.
  • the semiconductor chips 113 are with bonding wires
  • the web 120 delimits the first region 110 in one direction, in particular in the direction of the solder joints 126 or the projecting regions 116.
  • the thickness of the second conductive layer 105 is reduced in the first region 110 compared to the thickness of the second region 112 conductive layer 105 is interrupted stel ⁇ lenweise on the intermediate layer 103 so that portions of the second leitfähi- gen layer 105 are electrically and / or thermally insulated from one another.
  • FIG. 8 shows a further detailed view of the optoelectronic component 100 according to embodiments.
  • the recesses 117 extend through the entire layer stack 106.
  • the recesses 117 are surrounded by the second conductive layer 105, the intermediate layer 103 and the first conductive layer 2 ⁇ .
  • Figure 8 shows the component 100 without the web 120. If no encapsulation is provided, can be dispensed onto the web 120 ⁇ the.
  • the first Area 110 introduced into the second conductive layer 105 for example, by an etching process, and subsequently arranged the web 120, so that the area in which the semiconductor ⁇ semiconductor chips 113 are arranged is also completed on the side on which the second conductive layer 105 un ⁇ interrupted is to realize electrical interconnects.
  • FIG. 9 shows the optoelectronic component 100 according to further embodiments.
  • the edge between the area 112 and the first area 110 is shown.
  • the edge acts as a shutter edge for the subsequently to be mounted semiconductor chips ⁇ 113.
  • Figure 10 shows a schematic plan view of the optoelekt ⁇ elec- tronic device 100 according to embodiments.
  • the carrier 101 has a width 129 of about 22 mm.
  • the carrier 101 has a width 130 of about 7 mm.
  • Figure 11 shows a schematic representation of a sectional view through the carrier 101 transversely to the stacking direction S.
  • the intermediate layer 103 is continuous.
  • the first leitfähi ⁇ ge layer 102 is interrupted by the recesses 127th
  • the second conductive layer 105 is interrupted by recesses 124 to provide separate regions.
  • FIG. 12 shows a schematic representation of a detailed view of the optoelectronic component 100 according to embodiments.
  • the interlayer 103 of silicon nitride also serves according to embodiments as a potential separation between the first conductive layer 102 and the second conductive
  • FIGS. 13A and 13B show a detailed view of a screw connection 123.
  • the recess 117 extends through the entire layer stack 106 of the optoelectronic component 100.
  • the screw connection 123 for example in the form of a screw, is guided through the embodiment 117 and screwed to the substrate 108.
  • the screw 123 is particularly feasible because a silicon nitride ⁇ layer is used as an intermediate layer having a high flexural strength and fracture toughness, or fracture toughness. So ⁇ it is possible to form the carrier 101 in one piece, so that it serves both for electrical contacting and as a carrier for the semiconductor chip 113. On a metal core circuit board ⁇ for the rewiring can thus waived the ⁇ .
  • the silicon nitride interlayer 103 performs the functions conventionally realized by separate devices, such as ceramics, submeasors and metal core circuit boards.
  • FIGS. 14A to 14B show exemplary dimensions for an opto-electronic component 100 that can be contacted via solder joints 126.
  • the optoelectronic component 100 has the widths A and B, so that an area of 140 to 190 mm is formed. This is in particular the area of the intermediate Layer 103.
  • the thickness D of the intermediate layer 103 at ⁇ game as 0.32 mm.
  • the thickness of the conductive layer 102 and the conductive layer 105 are respectively between 0.1 and 0.6 mm inclusive, for example 0.15 mm, 0.2 mm, 0.25 mm, 0.3 mm, 0.4 mm or 0.5 mm.
  • the distance C of the two ⁇ th conductive layer 102 from the edge of the intermediate layer 103 is more than 0.5 mm.
  • the width B of the second conductive layer 105 is, for example, greater than 0.5 mm.
  • the width of the recesses 124 is, for example, greater than 1.0 mm, in particular greater than 1.2 mm
  • the layer ⁇ stack 106 includes additional layers 128 between the intermediate layer and each of the first conductive layer 102 and the second conductive layer 105.
  • the layer 128 of play includes examples a solder, so that the conductive layers 102 and 105 reliably to the intermediate layer 103 adhere.
  • the distance D between the regions of the layer 128, which correspond to the conductor tracks, is greater than 0.6 mm, in particular greater than 0.7 mm.
  • the specified dimensions are only to be understood as examples. Other dimensions are of course possible.
  • the tolerances of the given dimensions are for the widths A, B + 0.2 and - 0.5, for the width C +/- 0.5, for the thickness D +/- 0.5 and for the widths E, F , G +/- 0.2, in particular +/- 0.3.
  • FIGS. 15A and 15B show a schematic representation of the optoelectronic component 100 according to embodiments, in which the contacting of the semiconductor chips 113 takes place by means of the projecting regions 116.
  • the width M of the conductor tracks and protruding areas 116 is, for example, greater than 1.9 mm, in particular greater than 1.2 mm. From the- stand N between the conductor tracks and the projecting portions 116, for example, greater than 1.0 mm, insbesonde ⁇ re greater than 1.2 mm.
  • the thickness H of the second conductive layer 105 is, for example, 0.15 mm, 0.2 mm, 0.25 mm, 0.3 mm, 0.4 mm or 0.5 mm.
  • the length L of the region where the second conductive layer 105 is connected to the intermediate layer 103 by means of the layer 128 is more than 3.0 mm.
  • the distance K of the layer 128 at which the part of the second conductive layer 105 with the protruding region 116 is arranged is more than 0.2 mm.
  • the projecting portion 116 protrudes so far that the length J + J x is smaller than 140 mm ⁇ 190 mm.
  • J + J x is less than 120 mm x 120 mm.
  • the dimensions mentioned are merely exemplary. Other proportions are possible.
  • the tolerance of the thickness H is +/- 0.5 mm.
  • the tolerance of the length J be ⁇ contributes +/- 0.5 mm.
  • the tolerance of the length K is +/- 0.5 mm.
  • the tolerance of the length L is +/- 0.5 mm.
  • the tolerance of the width M is +/- 0.3 mm, in particular +/- 0.4 mm.
  • the tolerance of the width N is +/- 0.3 mm, in particular +/- 0, 4 mm.
  • the thermal resistance of the component 100 is reduced in comparison to conventional components, since the metal-core circuit board for the rewiring is omitted.
  • the component 100 is, for example, by means of the solder pads 126 or by the plug pins integrated in the second conductive layer 105
  • the solder pads 126 or the plug pins 116 can be arranged both on the upper side and on the underside of the intermediate layer 103.
  • the different thicknesses of the first region 110 and second region 112 are introduced, for example by means of an etching process ⁇ in the second conductive layer 105th
  • the second conductive layer 105 is thinned in the region 110 in which the semiconductor chips 113 are arranged.
  • the higher unetched second portion 112 is disposed around the first region 110 around and is, for example, as a frame ver ⁇ turns. This framework leads in particular to an improved cut-off contrast in operation, so that the illuminated through the construction ⁇ some 100 areas and not be light ⁇ th areas are well separated.
  • the frame serves as the boundary for the potting 119.
  • the component 100 is used as the optoelectronic light module 121 on the heat sink 121 as a headlight in a motor vehicle.
  • the present application claims the priority of interpreting ⁇ rule application DE 102013102556.0, the disclosure of which is hereby incorporated by reference.
  • the invention is not limited by the description based on the embodiments of these. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes any combination of features i the patent claims, even if this feature o- this combination itself is not explicitly stated in the claims or exemplary embodiments.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un composant optoélectronique comprenant : un substrat plan (101) portant une première couche conductrice (102), une couche intermédiaire (103) contenant du nitrure de silicium (104) et une deuxième couche conductrice (105) qui sont disposées dans un empilage de couches (106) dans une direction d'empilage (S). La première couche conductrice (102) possède une première surface (107) supportant le composant (100) sur un fond (108), une première zone (110) de la deuxième couche conductrice va jusqu'à un premier plan (109) espacé de la première surface (107) dans la direction d'empilage (S), une deuxième zone (112) de la deuxième couche conductrice (105) dans la direction d'empilage (S) va jusqu'à un deuxième plan (111) davantage espacé de la première surface (107), et au moins une puce de semi-conducteur optoélectronique (113) est disposée dans la première zone (110) de la deuxième couche conductrice (105).
PCT/EP2014/054369 2013-03-13 2014-03-06 Composant optoélectronique, module lumineux et projecteur de véhicule automobile Ceased WO2014139860A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112014001265.3T DE112014001265A5 (de) 2013-03-13 2014-03-06 Optoelektronisches Bauteil, Leuchtmodul und Kraftfahrzeugscheinwerfer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102013102556.0A DE102013102556A1 (de) 2013-03-13 2013-03-13 Optoelektronisches Bauteil, Leuchtmodul und Kraftfahrzeugscheinwerfer
DE102013102556.0 2013-03-13

Publications (1)

Publication Number Publication Date
WO2014139860A1 true WO2014139860A1 (fr) 2014-09-18

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Application Number Title Priority Date Filing Date
PCT/EP2014/054369 Ceased WO2014139860A1 (fr) 2013-03-13 2014-03-06 Composant optoélectronique, module lumineux et projecteur de véhicule automobile

Country Status (2)

Country Link
DE (2) DE102013102556A1 (fr)
WO (1) WO2014139860A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015114287A1 (de) * 2015-08-27 2017-03-02 Osram Opto Semiconductors Gmbh Lichtemittierendes Bauelement

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020164475A1 (en) * 2000-09-20 2002-11-07 Hitachi Metals, Ltd. Silicon nitride powder, silicon nitride sintered body, sintered silicon nitride substrate, and circuit board and thermoelectric module comprising such sintered silicon nitride substrate
US20080023713A1 (en) * 2004-09-30 2008-01-31 Tokuyama Corporation Package for Housing Light-Emitting Element and Method for Manufacturing Package for Housing Light-Emitting Element
US20080224608A1 (en) * 2007-03-15 2008-09-18 Sharp Kabushiki Kaisha Light emitting device and method for manufacturing the same
US20090001490A1 (en) * 2004-07-26 2009-01-01 Georg Bogner Optoelectronic Component that Emits Electromagnetic Radiation and Illumination Module
US20100157583A1 (en) * 2008-12-19 2010-06-24 Toshiyuki Nakajima Led device and led lighting apparatus
EP2315284A2 (fr) * 2009-10-21 2011-04-27 Toshiba Lighting & Technology Corporation Appareil électroluminescent et luminaire
EP2346307A2 (fr) * 2010-01-18 2011-07-20 Toshiba Lighting & Technology Corporation Appareil d'éclairage
DE102010044987A1 (de) * 2010-09-10 2012-03-15 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung

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Publication number Priority date Publication date Assignee Title
JP2007180318A (ja) * 2005-12-28 2007-07-12 Matsushita Electric Ind Co Ltd 発光モジュールとその製造方法
KR100802393B1 (ko) * 2007-02-15 2008-02-13 삼성전기주식회사 패키지 기판 및 그 제조방법
DE102009025564A1 (de) * 2008-10-21 2010-05-20 Siemens Aktiengesellschaft Beleuchtungsanordnung mit einem LED-Array
EP2413392A4 (fr) * 2009-03-24 2013-12-18 Kang Kim Boîtier de diodes électroluminescentes

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020164475A1 (en) * 2000-09-20 2002-11-07 Hitachi Metals, Ltd. Silicon nitride powder, silicon nitride sintered body, sintered silicon nitride substrate, and circuit board and thermoelectric module comprising such sintered silicon nitride substrate
US20090001490A1 (en) * 2004-07-26 2009-01-01 Georg Bogner Optoelectronic Component that Emits Electromagnetic Radiation and Illumination Module
US20080023713A1 (en) * 2004-09-30 2008-01-31 Tokuyama Corporation Package for Housing Light-Emitting Element and Method for Manufacturing Package for Housing Light-Emitting Element
US20080224608A1 (en) * 2007-03-15 2008-09-18 Sharp Kabushiki Kaisha Light emitting device and method for manufacturing the same
US20100157583A1 (en) * 2008-12-19 2010-06-24 Toshiyuki Nakajima Led device and led lighting apparatus
EP2315284A2 (fr) * 2009-10-21 2011-04-27 Toshiba Lighting & Technology Corporation Appareil électroluminescent et luminaire
EP2346307A2 (fr) * 2010-01-18 2011-07-20 Toshiba Lighting & Technology Corporation Appareil d'éclairage
DE102010044987A1 (de) * 2010-09-10 2012-03-15 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung

Also Published As

Publication number Publication date
DE112014001265A5 (de) 2015-11-26
DE102013102556A1 (de) 2014-09-18

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