WO2014164742A1 - Dépôt de couches atomiques de hfalc utilisé comme matériau de travail de sortie de grille métallique dans des dispositifs à mos - Google Patents

Dépôt de couches atomiques de hfalc utilisé comme matériau de travail de sortie de grille métallique dans des dispositifs à mos Download PDF

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Publication number
WO2014164742A1
WO2014164742A1 PCT/US2014/023375 US2014023375W WO2014164742A1 WO 2014164742 A1 WO2014164742 A1 WO 2014164742A1 US 2014023375 W US2014023375 W US 2014023375W WO 2014164742 A1 WO2014164742 A1 WO 2014164742A1
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WO
WIPO (PCT)
Prior art keywords
layer
substrate
work function
site
forming
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Ceased
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PCT/US2014/023375
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English (en)
Inventor
Albert Lee
Hoon Kim
Salil Mujumdar
Edward Haywood
Kisik Choi
Paul Besser
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GlobalFoundries Inc
Intermolecular Inc
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GlobalFoundries Inc
Intermolecular Inc
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Publication of WO2014164742A1 publication Critical patent/WO2014164742A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32—Carbides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45531—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making ternary or higher compositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01342—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/669—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes

Definitions

  • the present disclosure relates generally to work function materials used in
  • MOSFET metal oxide semiconductor field effect transistor
  • 3D 3-dimensional
  • FinFETs FinFETs
  • V t h device threshold voltage
  • An alternative method to tune the V t h is to use different metals with varying work functions as the gate material in a high-k metal gate (HKMG) structure.
  • HKMG high-k metal gate
  • the metal gate is typically deposited using physical vapor deposition (PVD), but as device dimensions are shrinking and becoming 3D, atomic layer deposition (ALD) will become necessary to deposit the metal gate in a conformal manner.
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • Metals and compounds such as tantalum-silicon-nitride, ruthenium, tantalum carbide, molybdenum nitride, and titanium aluminide with band-edge work functions have been evaluated as candidates to be used as gate p- and n- metals in MOSFET devices.
  • materials with mid-gap work functions are also desired.
  • Nickel silicide, titanium silicide, hafnium carbide, and hafnium aluminide have been found to possess mid-gap work functions.
  • Many of the metal gate materials have been deposited using PVD. However, it is difficult to tune the work function of these materials when deposited using PVD techniques.
  • ALD of Hf x Al y C z films using hafnium chloride (HfC ) and Trimethylaluminum (TMA) precursors can be combined with post- deposition anneal processes and ALD liners to control the device characteristics in high-k metal- gate devices.
  • Variation of the HfCU pulse time allows for control of the Al % incorporation in the Hf x Al y C z film in the range of 10-13%.
  • Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks.
  • EWF effective work function
  • MOSCAP metal oxide semiconductor capacitor
  • FIG. 1 is a schematic diagram for implementing combinatorial processing and evaluation.
  • FIG. 2 is a schematic diagram for illustrating various process sequences using combinatorial processing and evaluation.
  • FIG. 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HPC) system.
  • FIG. 4 illustrates a physical vapor deposition (PVD) system according to some embodiments.
  • FIG. 5 is a simplified schematic diagram illustrating a cross section of a device according to some embodiments.
  • FIG. 6 is a simplified schematic diagram illustrating a cross section of a device according to some embodiments.
  • FIG. 7 is a simplified schematic diagram illustrating a design of experiments according to some embodiments.
  • FIG. 8 presents data for XRF Hf counts and thickness versus HfCl 4 pulse time according to some embodiments.
  • FIG. 9 presents data for XRF Al/Hf count ratio versus HfCU pulse time according to some embodiments.
  • FIG. 10 presents data for XRF Hf counts and thickness versus TMA pulse time according to some embodiments.
  • FIG. 11 presents data for XRF Al/Hf count ratio versus TMA pulse time according to some embodiments.
  • FIG. 12 presents data for film composition according to some embodiments.
  • FIG. 13 presents XRD data according to some embodiments.
  • FIG. 14 presents data for HfC resistivity according to some embodiments.
  • FIG. 15 presents data for capacitance versus voltage according to some embodiments.
  • FIG. 16 presents data for flat band voltage according to some embodiments.
  • FIG. 17 presents data for flat band voltage and effective work function according to some embodiments.
  • FIG. 18 presents data for capacitance equivalent thickness according to some embodiments.
  • FIG. 19 presents data for leakage current density according to some embodiments.
  • horizontal as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate.
  • vertical will refer to a direction perpendicular to the horizontal as previously defined. Terms such as “above”, “below”, “bottom”, “top”, “side” (e.g. sidewall), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane.
  • on means there is direct contact between the elements. The term “above” will allow for intervening elements.
  • a material e.g. a dielectric material or an electrode material
  • crystalline if it exhibits greater than or equal to 30% crystallinity as measured by a technique such as x-ray diffraction (XRD).
  • each of the layers discussed herein and used in the device may be formed using any common formation technique such as physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PE- ALD), atomic vapor deposition (AVD), ultraviolet assisted atomic layer deposition (UV-ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), pulsed laser deposition (PLD), or evaporation.
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • PE- ALD plasma enhanced atomic layer deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • ALD atomic vapor deposition
  • SIR site-isolated region
  • the SIRs can be formed using many different methods such as scribing, deposition through a shadow mask, deposition using isolated deposition heads, lithography, and the like. The present disclosure is not limited by the method used to form the SIRs.
  • film and “layer” will be understood to represent a portion of a stack. They will be understood to cover both a single layer as well as a multilayered structure (i.e. a nanolaminate). As used herein, these terms will be used synonymously and will be considered equivalent.
  • substrate may refer to any workpiece on which formation or treatment of material layers is desired.
  • Substrates may include, without limitation, silicon, germanium, silicon-germanium alloys, gallium arsenide, indium gallium arsenide, indium gallium antimonide, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, Spinel, coated silicon, silicon on oxide, silicon carbide on oxide, glass, gallium nitride, indium nitride, and combinations (or alloys) thereof.
  • substrate or “wafer” may be used interchangeably herein.
  • Semiconductor wafer shapes and sizes can vary and include commonly used round wafers of 50 mm, 100 mm, 150 mm, 200 mm, 300 mm, or 450 mm in diameter.
  • semiconductor manufacturing entails the integration and sequencing of many unit processing steps.
  • semiconductor manufacturing typically includes a series of processing steps such as cleaning, surface preparation, deposition, patterning, etching, thermal annealing, and other related unit processing steps.
  • processing steps such as cleaning, surface preparation, deposition, patterning, etching, thermal annealing, and other related unit processing steps.
  • the precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as efficiency, power production, and reliability.
  • each unit process it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as semiconductor devices.
  • FIG. 1 illustrates a schematic diagram, 100, for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening.
  • the schematic diagram, 100 illustrates that the relative number of combinatorial processes run with a group of substrates decreases as certain materials and/or processes are selected.
  • combinatorial processing includes performing a large number of processes during a primary screen, selecting promising candidates from those processes, performing the selected processing during a secondary screen, selecting promising candidates from the secondary screen for a tertiary screen, and so on.
  • feedback from later stages to earlier stages can be used to refine the success criteria and provide better screening results.
  • Materials discovery stage, 102 is also known as a primary screening stage performed using primary screening techniques.
  • Primary screening techniques may include dividing substrates into coupons and depositing materials using varied processes. The materials are then evaluated, and promising candidates are advanced to the secondary screen, or materials and process development stage, 104. Evaluation of the materials is performed using metrology tools such as electronic testers and imaging tools (i.e., microscopes).
  • the materials and process development stage, 104 may evaluate hundreds of materials (i.e., a magnitude smaller than the primary stage) and may focus on the processes used to deposit or develop those materials. Promising materials and processes are again selected, and advanced to the tertiary screen or process integration stage, 106, where tens of materials and/or processes and combinations are evaluated.
  • the tertiary screen or process integration stage, 106 may focus on integrating the selected processes and materials with other processes and materials.
  • the most promising materials and processes from the tertiary screen are advanced to device qualification, 108.
  • device qualification the materials and processes selected are evaluated for high volume manufacturing, which normally is conducted on full substrates within production tools, but need not be conducted in such a manner. The results are evaluated to determine the efficacy of the selected materials and processes. If successful, the use of the screened materials and processes can proceed to pilot manufacturing, 110.
  • the schematic diagram, 100 is an example of various techniques that may be used to evaluate and select materials and processes for the development of new materials and processes.
  • the descriptions of primary, secondary, etc. screening and the various stages, 102-110, are arbitrary and the stages may overlap, occur out of sequence, be described and be performed in many other ways.
  • FIG. 2 is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration that includes site isolated processing and/or conventional processing in accordance with one embodiment of the invention.
  • the substrate is initially processed using conventional process N.
  • the substrate is then processed using site isolated process N+l .
  • an HPC module may be used, such as the HPC module described in US Patent Application Serial Number 1 1/352,077 filed on February 10, 2006.
  • the substrate can then be processed using site isolated process N+2, and thereafter processed using conventional process N+3. Testing is performed and the results are evaluated.
  • the testing can include physical, chemical, acoustic, magnetic, electrical, optical, etc. tests. From this evaluation, a particular process from the various site isolated processes (e.g.
  • a next process sequence can include processing the substrate using site isolated process N, conventional processing for processes N+l, N+2, and N+3, with testing performed thereafter.
  • the combinatorial process sequence integration can be applied to any desired segments and/or portions of an overall process flow. Characterization, including physical, chemical, acoustic, magnetic, electrical, optical, etc. testing, can be performed after each process operation, and/or series of process operations within the process flow as desired. The feedback provided by the testing is used to select certain materials, processes, process conditions, and process sequences and eliminate others. Furthermore, the above flows can be applied to entire monolithic substrates, or portions of monolithic substrates such as coupons.
  • a processing material delivered to a first and second region can be the same or different. If the processing material delivered to the first region is the same as the processing material delivered to the second region, this processing material can be offered to the first and second regions on the substrate at different concentrations. In addition, the material can be deposited under different processing parameters.
  • Parameters which can be varied include, but are not limited to, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, atmospheres in which the processes are conducted, an order in which materials are deposited, hardware details of the gas distribution assembly, etc. It will be appreciated that these process parameters are exemplary and not meant to be an exhaustive list as other process parameters commonly used in semiconductor manufacturing may be varied.
  • FIG. 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HPC) system in accordance with some embodiments of the invention.
  • the HPC system includes a frame 300 supporting a plurality of processing modules. It will be appreciated that frame 300 may be a unitary frame in accordance with some embodiments. In some embodiments, the environment within frame 300 is controlled.
  • a load lock 302 provides access into the plurality of modules of the HPC system.
  • a robot 314 provides for the movement of substrates (and masks) between the modules and for the movement into and out of the load lock 302.
  • Modules 304 - 312 may be any set of modules and preferably include one or more combinatorial modules.
  • module 304 may be an orientation/degassing module
  • module 306 may be a clean module, either plasma or non-plasma based
  • modules 308 and/or 310 may be combinatorial/conventional dual purpose modules.
  • Module 312 may provide conventional clean or degas as necessary for the experiment design.
  • a centralized controller i.e., computing device 316, may control the processes of the HPC system. Further details of one possible HPC system are described in US Application Serial Nos.
  • a process chamber for combinatorial processing of a substrate includes one or more assemblies for sputtering material from targets (such as sputter guns); a power source coupled to the one or more sputter guns; a substrate support; a power source (e.g. RF, DC, pulsed, or the like) coupled to the substrate support; and a grounded shield comprising an aperture disposed between the substrate support and the one or more sputter guns to form a dark-space gap between the substrate support and the aperture.
  • the aperture may be configured to allow sputter deposition or plasma processing of a site-isolated region on the substrate.
  • the process chamber may further include a plasma confinement ring between the substrate support and the grounded shield.
  • the plasma confinement ring may be thicker than the substrate.
  • the plasma confinement ring fills the dark-space gap between the substrate support and the grounded shield.
  • the process chamber may further include a dielectric material in the dark-space gap.
  • the dielectric material may be coated with a metal layer for grounding and RF shielding.
  • the dark- space gap may be between about 1 mm and about 3 mm.
  • the process chamber may further include a controller to selectively apply power to the one or more sputter guns from the power source and apply power to bias the substrate support from a power source.
  • the controller may be configured to control the power source to perform one or both of plasma processing and PVD deposition on a site-isolated region on the substrate.
  • other sputter mechanisms can be used instead of the sputter guns.
  • a semiconductor processing system for combinatorial processing of a substrate includes a process chamber having a dark-space region configured to prevent plasma leaks in a region adjacent the substrate.
  • the process chamber can be configured to perform both plasma processing and sputter deposition on a site-isolated region on the substrate.
  • the process chamber may include a dielectric material in the dark-space gap.
  • the dark-space region may be between about 1 mm and about 3 mm.
  • the process chamber may include a plasma confinement ring positioned around the substrate to prevent plasma leak in a region adjacent the substrate.
  • the plasma confinement ring may be thicker than the substrate.
  • the plasma confinement ring may be a conductive material or ceramic material which may or may not be partially coated with a metal layer.
  • a method of combinatorial processing of a substrate in which site-isolated sputter deposition and plasma processing are performed in the same process chamber.
  • the site-isolated sputter deposition may include site-isolated co-sputtering deposition.
  • Cleaning, site-isolated sputter deposition, and plasma processing may be performed in the same process chamber.
  • Cleaning, site-isolated sputter deposition, and plasma processing, and full wafer sputter deposition may be performed in the same process chamber.
  • a method of combinatorial processing of a substrate in which sputter deposition and plasma processing are performed in the same process chamber.
  • the sputter deposition may include co-sputtering deposition. Cleaning, sputter deposition, and plasma processing may be performed in the same process chamber.
  • the sputter deposition may result in a gradient in material properties across the length and/or width of the substrate. Physical methods such as scribing or lithography may be used to define the SIRs after the deposition.
  • FIG. 4 is a simplified schematic diagram illustrating an exemplary process chamber 400 configured to perform combinatorial processing and full substrate processing in accordance with some embodiments of the invention. It will be appreciated that the processing chamber shown in FIG. 4 is merely exemplary and that other process or deposition chambers may be used with the invention. Further details on exemplary deposition chambers that can be used with the invention can be found in U.S. Patent Application No. 11/965,689, now U.S. Patent No. 8,039,052, entitled “Multi-region Processing System and Heads", filed December 27, 2007, and claiming priority to U.S. Provisional Application No. 60/970,500 filed on September 6, 2007, and U.S. Patent Application No. 12/027,980, entitled “Combinatorial Process System", filed February 7, 2008 and claiming priority to U.S. Provisional Application No. 60/969,955 filed on September 5, 2007, the entireties of which are hereby incorporated by reference.
  • the processing chamber 400 includes a bottom chamber portion 402 disposed under a top chamber portion 418.
  • a substrate support 404 is provided within the bottom chamber portion 402.
  • the substrate support 404 is configured to hold a substrate 406 disposed thereon and can be any known substrate support, including but not limited to a vacuum chuck, electrostatic chuck or other known mechanisms.
  • the substrate 406 may be a conventional 200 mm and 300 mm wafers, or any other larger or smaller size. In some embodiments, substrate 406 may be a square, rectangular, or other shaped substrate. The substrate 406 may be a blanket substrate, a coupon (e.g., partial wafer), or even a patterned substrate having predefined regions. In some embodiments, substrate 406 may have regions defined through site-isolated processing as described herein.
  • the top chamber portion 418 of the chamber 400 includes a process kit shield 412, which defines a confinement region over a portion of the substrate 406.
  • the process kit shield 412 includes a sleeve having a base (optionally integrated with the shield) and an optional top. It will be appreciated, however, that the process kit shield 412 may have other configurations.
  • the process kit shield 412 is configured to confine plasma generated in the chamber 400 by sputter guns 416. The positively-charged ions in the plasma strike a target and dislodge atoms from the target. The sputtered neutrals are deposited on an exposed surface of substrate 406.
  • the process kit shield 412 may be partially moved in and out of chamber 400, and, in other embodiments, the process kit shield 412 remains in the chamber for both full substrate and combinatorial processing. When used in the full substrate
  • a gradient in the material properties can be introduced across the length and/or width of the substrate.
  • the base of process kit shield 412 includes an aperture 414 through which a surface of substrate 406 is exposed for deposition processing.
  • the chamber may also include an aperture shutter 420 which is moveably disposed over the base of process kit shield 412.
  • the aperture shutter 420 slides across a bottom surface of the base of process kit shield 412 in order to cover or expose aperture 414.
  • the aperture shutter 420 is controlled by an arm extension (not shown) which moves the aperture shutter to expose or cover aperture 414.
  • the chamber 400 includes two sputter guns 416. While two sputter guns are illustrated, any number of sputter guns may be included, e.g., one, three, four or more sputter guns may be included. Where more than one sputter gun is included, the plurality of sputter guns may be referred to as a cluster of sputter guns. In addition, other sputter systems can be used, such as magnetron sputter systems.
  • the sputter guns 416 are moveable in a vertical direction so that one or both of the guns may be lifted from the slots of the shield.
  • sputter guns 416 are oriented or angled so that a normal reference line extending from a planar surface of the target of the process gun is directed toward an outer periphery of the substrate in order to achieve good uniformity for full substrate deposition film.
  • the target/gun tilt angle depends on the target size, target-to- substrate spacing, target material, process power/pressure, etc. and the tilt angle may be varied.
  • the chamber may also include a gun shutter 422, which seals off the deposition gun when the process gun 416 is not needed during processing.
  • the gun shutter 422 allows one or more of the sputter guns 416 to be isolated from certain processes as needed. It will be appreciated that the gun shutter 422 may be integrated with the top of the process kit shield 412 to cover the opening as the process gun 416 is lifted or individual gun shutter 422 can be used for each process gun 416.
  • the sputter guns 416 may be fixed to arm extensions 416a to vertically move sputter guns 416 toward or away from top chamber portion 418.
  • the arm extensions 416a may be attached to a drive, e.g., lead screw, worm gear, etc.
  • the arm extensions 416a may be pivotally affixed to sputter guns 416 to enable the sputter guns to tilt relative to a vertical axis.
  • sputter guns 416 tilt toward aperture 414 when performing combinatorial processing and tilt toward a periphery of the substrate being processed when performing full substrate processing. It will be appreciated that sputter guns 416 may alternatively tilt away from aperture 414.
  • the chamber 400 also includes power sources 424 and 426.
  • Power source 424 provides power for sputter guns 416, and power source 426 provides RF power to bias the substrate support 404.
  • the output of the power source 426 is synchronized with the output of power source 424.
  • the power source, 424 may output a direct current (DC) power supply, a direct current (DC) pulsed power supply, a radio frequency (RF) power supply or a DC- RF imposed power supply.
  • the power sources 424 and 426 may be controlled by a controller (not shown) so that both deposition and etch can be performed in the chamber 400, as will be described in further detail hereinafter.
  • the chamber 400 may also include an auxiliary magnet 428 disposed around an external periphery of the chamber 400.
  • the auxiliary magnet 428 is located between the bottom surface of sputter guns 416 and proximity of a substrate support 404.
  • the auxiliary magnet may be positioned proximate to the substrate support 404, or, alternatively, integrated within the substrate support 404.
  • the magnet 428 may be a permanent magnet or an electromagnet.
  • the auxiliary magnet 428 improves ion guidance as the magnetic field above substrate 406 is re-distributed or optimized to guide the metal ions.
  • the auxiliary magnet 428 provides more uniform bombardment of ions and electrons to the substrate and improves the uniformity of the film being deposited.
  • the substrate support 404 is capable of both rotating around its own central axis 408 (referred to as "rotation" axis), and rotating around an exterior axis 410 (referred to as
  • substrate support 404 may move in a vertical direction. It will be appreciated that the rotation and movement in the vertical direction may be achieved through one or more known drive mechanisms, including, for example, magnetic drives, linear drives, worm screws, lead screws, differentially pumped rotary feeds, and the like.
  • any region of a substrate 406 may be accessed for combinatorial processing.
  • the dual rotary substrate support 404 allows any region (i.e., location or site) of the substrate 406 to be placed under the aperture 414; hence, site-isolated processing is possible at any location on the substrate 406. It will be appreciated that removal of the aperture 414 and aperture shutter 420 from the chamber 400 or away from the substrate 406 and enlarging the bottom opening of the process kit shield 412 allows for processing of the full substrate.
  • embodiments of the invention allow for both sputter deposition and plasma etch to be performed in the same process chamber (e.g., chamber 400).
  • the chamber 400 is configured so that both sputter deposition and plasma etch can be performed in the chamber 400, and, in particular, the chamber 400 is configured to allow for both site-isolated sputter deposition and plasma etch to be performed in the chamber.
  • full wafer sputter deposition and plasma etch may also be performed in the chamber 400 by removing the aperture 414 away from the chamber 400 or moving the aperture 414 away from the substrate 406 and enlarging the bottom opening of the process kit shield 412.
  • plasma etch may be performed in the chamber 400 by applying RF power from the power source 426 to bias the substrate support (e.g., an electrostatic chuck) 404 with or without DC plasma near the sputter target. Plasma is then ignited on top of the substrate 406, which is confined by the aperture 414 and shield 412 above the substrate 406 so that site-isolated plasma etch of the substrate 406 can occur in the chamber 400.
  • Sputter deposition may similarly be performed in the chamber 400 by applying DC power from the power source 424 to the sputter gun(s) 416.
  • Three modes of processing can be performed in chamber 400: sputter deposition only, simultaneous sputter deposition and plasma etch, and plasma etch only.
  • the RF power is any value or range of values between about 50W and about 2000W.
  • DC or pulsed DC power applied to sputter sources can have peak powers as high as 1 OkW, for example, for high metal ionization in sputter deposition.
  • the RF power frequency may be any value or range of values between about 40 kHz and about 60MHz. It will be appreciated that the RF power frequency may be less than about 40 kHz or greater than about 60MHz.
  • plasma etch can be used to clean the substrate 406.
  • An exemplary process according to some embodiments of the invention may begin by cleaning the substrate, performing site-isolated sputter deposition, performing site -isolated plasma etch, performing full substrate sputter deposition and then performing a subsequent full substrate plasma etch, all within the same chamber (e.g., chamber 400).
  • Another exemplary process according to some embodiments of the invention may begin by cleaning the substrate, performing a full substrate sputter deposition, performing site-isolated sputter deposition, performing site-isolated plasma etch, performing full substrate sputter deposition, and performing a subsequent full substrate plasma etch, all within the same chamber (e.g., chamber 400). It will be appreciated that the above processes are merely exemplary and that processes according to the invention may include fewer steps or additional steps and that the order of the steps may vary.
  • Hafnium oxide is a candidate for silicon dioxide replacement as a gate dielectric material. It has a dielectric constant of about 25 at room temperature or about six times greater than that of silicon dioxide. While this dielectric constant is more than an order of magnitude smaller than for strontium titanium oxide (SrTiC ), which has a dielectric constant of about 300, hafnium oxide has a conduction band offset of about 1.5 - 2.0 eV with respect to silicon, which is more than one order of magnitude higher than that of strontium titanium oxide.
  • hafnium oxide makes it a leading candidate for a gate dielectric application also give hafnium oxide a high potential for other applications, such as insulating dielectrics in capacitive elements of various memory devices or, more specifically, of dynamic random-access memory (DRAM) capacitor stacks.
  • DRAM dynamic random-access memory
  • a thick layer of hafnium oxide can be used to achieve the same performance as a much thinner silicon dioxide layer.
  • thicker hafnium oxide layers have much lower leakage currents in comparison with thinner silicon oxide layers.
  • hafnium oxide is thermodynamically stable with respect to silicon, with which it may be in contact in many semiconductor applications.
  • CMOS complementary metal-oxide- semiconductor
  • DRAM dynamic random access memory
  • high temperatures e.g., 1000 °C
  • Other applications of hafnium oxide include optical coatings, catalysts, and protective coatings (due to its hardness and thermal stability).
  • Hafnium oxide layers or structures may be deposited by a variety of physical vapor deposition (PVD) methods, including laser pulse ablation and sputtering.
  • PVD physical vapor deposition
  • Other deposition techniques include CVD using ⁇ -diketonate precursors, alkoxide precursors, and chloride precursors.
  • Atomic layer deposition (ALD) techniques may be used to prepare layers using both chloride and iodide precursors. Different deposition techniques yield different layer structures that may have different susceptibilities to etching.
  • Metal layers may be converted to metal compounds by the reaction with ions or reactive neutral species to form metal oxides, metal nitrides, metal carbides, metal silicides, metal chlorides, metal fluorides, and the like. These metal compounds may be used as diffusion barriers, local conductors, adhesion layers, work function (WF) tuning layers, and the like.
  • the ions and/or reactive neutral species may be formed using a remote plasma source.
  • FIG. 5 illustrates a schematic representation of substrate portions including MOS device, 500, in accordance with some embodiments.
  • MOS device 500 includes a p-doped substrate, 501, and an n-doped well, 502, disposed within substrate, 501.
  • Substrate, 501 is typically a part of an overall wafer that may include other devices. Some of these devices may include silicon nitride, silicon oxide, polysilicon, or titanium nitride structures.
  • P-doped substrate, 501 may include any suitable p-type dopants, such as boron and indium, and may be formed by any suitable technique.
  • N-doped well, 502 may include any suitable n-type dopants, such as phosphorus and arsenic, and may be formed by any suitable technique.
  • n-doped well, 502 may be formed by doping substrate, 501, by ion implantation, for example.
  • MOS device, 500 also includes a conductive gate electrode, 512, that is separated from n- doped well, 502, by gate dielectric, 517.
  • Gate electrode, 512 may include any suitable conductive material.
  • gate electrode, 512 may comprise polysilicon.
  • gate electrode, 512 may include polysilicon doped with a p-type dopant, such as boron.
  • Gate dielectric, 517 is formed from a high-k material (e.g. hafnium oxide). Other dielectric materials include zirconium oxide or aluminum oxide.
  • a semiconductor material with high mobility such as germanium or a silicon-germanium alloy (not shown) is formed beneath the gate dielectric.
  • MOS device, 500 also includes p-doped source region, 504, and drain region, 506, (or simply the source and drain) disposed in n-doped well, 502.
  • Source, 504, and drain, 506, are located on each side of gate electrode, 512, forming channel, 508, within n-doped well, 502.
  • Source, 504, and drain, 506, may include a p-type dopant, such as boron.
  • Source, 504, and drain, 506, may be formed by ion implantation. After forming source, 504, and drain, 506, MOS device, 500, may be subjected to an annealing and/or thermal activation process.
  • source, 504, drain, 506, and gate electrode, 512 are covered with a layer of self-aligned silicide portions, 514, which may be also referred to as salicide portions or simply salicides.
  • a layer of cobalt may be deposited as a blanket layer and then thermally treated to form these silicide portions, 514.
  • suitable materials include nickel and other refractory metals, such as tungsten, titanium, platinum, and palladium.
  • RTP rapid thermal process
  • the RTP process may be performed at 700°C to 1000°C.
  • MOS device, 500 may also include shallow trench isolation (STI) structures, 510, disposed on both sides of source, 504, and drain, 506.
  • STI structures, 510 may include liners formed on the side and bottom walls by, for example, thermal oxidation of silicon of n-doped well, 502.
  • the main body of STI structures is formed by filling a trench within n-doped well, 502, with a dielectric material, such as silicon oxide. Silicon oxide may be filled using high density plasma (HDP) deposition process.
  • HDP high density plasma
  • gate dielectric, 517 may protrude beyond gate electrode, 512. As such, gate dielectric, 517, may need to be partially etched such that it does not extend past electrode, 512, and does not interfere with subsequent formation of liners and spacers on sidewalls of gate electrode, 512.
  • Hf x Al y C z was deposited in an ALD single-wafer chamber with gas delivery through a showerhead above 300mm diameter silicon wafers. Depositions were performed at substrate temperatures of about 270C.
  • Trimethylaluminum (TMA) precursors were used, with the HfCU bubbler heated to about 160C and the TMA bubbler maintained at room temperature.
  • HfCU was delivered into the chamber using Ar carrier gas, and TMA was delivered using a vapor draw method, without the use of a carrier gas.
  • HfCU pulse times in the range of 10-60s were used, while the TMA pulse times were typically about Is.
  • Ar was used to purge the chamber after each of the HfCU and TMA pulses during the ALD cycles.
  • the substrate was transferred (with minimum queue time to minimize the exposure of the Hf x Al y C z film to air) to a single-wafer chamber used to deposit titanium nitride using an ALD process.
  • TiCU and NH 3 were used as precursors and reactants to deposit the titanium nitride liner layer at a substrate temperature of about 375C (300-550 C).
  • In-situ vacuum, Ar, or NH 3 anneal treatments were performed for between 5 to 10 minutes in the ALD TiN chamber at the same substrate temperature as the ALD TiN deposition temperature or annealed in a separate chamber.
  • the films were characterized using X-Ray Fluorescence (XRF), Spectroscopic
  • RBS and XRF were used to provide film composition
  • the crystal structure was characterized using XRD
  • AFM was used to characterize the surface roughness.
  • Thicknesses were measured using XRR, Ellipsometry, and XRF measurements, where the XRF counts were calibrated to ellipsometer thickness measurements to calculate XRF thicknesses.
  • the resistivity of the films was characterized by depositing 30 ⁇ Hf x Al y C z films on 3kA thermal oxide, followed by 20-50 ⁇ ALD TiN liner deposition on top of the Hf x Al y C z films.
  • the sheet resistance (Rs) of the stack was measured and the resistivity of the Hf x Al y C z films was calculated using the known Rs of the ALD TiN liner films and knowing the thickness of each of the Hf x Al y C z and TiN films.
  • FIG. 6 illustrates simple MOSCAP devices prepared for determining electrical performance of the stacks.
  • P-type silicon substrates, 601 were used, and the device features formed within the thermal oxide layer, 602, were defined using typical photolithography and etch processes.
  • Hf0 2 layers, 604, deposited using ALD were used as the high-k dielectric material, followed by a thin titanium nitride barrier layer, 606, deposited before the Hf x Al y C z and/or titanium nitride work function metal layers, 608, were deposited.
  • the work function layers may include a single layer or may include multiple layers.
  • the Hf x Al y C z layers had the titanium nitride liner layers deposited on top for adhesion and to protect against oxidation.
  • Tungsten layers, 610 were deposited above the work function metal layers to allow for the probe contacts during testing. Other layers such as adhesion and/or barrier layers (not shown) may also be included in the stack.
  • the MOSCAP devices Prior to electrical testing, the MOSCAP devices underwent a forming gas anneal at temperatures up to 500C.
  • High Productivity Combinatorial (HPC) platforms for site-isolated wet etching and PVD deposition are used and multiple experiments can be performed on each substrate for faster cycles-of-learning.
  • the substrate is a full wafer.
  • the substrate is a coupon (e.g. a small portion of a wafer).
  • FIG. 1 schematically illustrates how isolated sites on each of two MOSCAP substrates (e.g. coupon a or b) are created, and that a different materials stack (e.g. stacks A - E) can be fabricated as a distinct experimental split.
  • two MOSCAP substrates e.g. coupon a or b
  • a different materials stack e.g. stacks A - E
  • a high-k dielectric layer of HfO x is deposited on an active region of "coupon a" using an ALD process as discussed previously.
  • a titanium nitride barrier layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • a titanium nitride work function metal layer is deposited above the titanium nitride barrier layer using a PVD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the titanium nitride work function metal layer using an ALD process as discussed previously.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • Stack - A may be repeated in several of the site-isolated regions to allow the repeatability and uniformity of the processes and measured results to be determined.
  • a high-k dielectric layer of HfO x is deposited on an active region of "coupon a" using an ALD process as discussed previously.
  • a titanium nitride barrier layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the titanium nitride barrier layer using an ALD process as discussed previously.
  • the aluminum concentration in the Hf x Al y C z work function metal layer can be varied in a range between 10 atomic % and 13 atomic % among the various site-isolated regions.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • Stack - B may be repeated in several of the site-isolated regions to allow the repeatability and uniformity of the processes and measured results to be determined.
  • a high-k dielectric layer of HfO x is deposited on an active region of "coupon b" using an ALD process as discussed previously.
  • a titanium nitride barrier layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • a titanium nitride work function metal layer is deposited above the titanium nitride barrier layer using a PVD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the titanium nitride work function metal layer using an ALD process as discussed previously.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • Stack - C may be repeated in several of the site-isolated regions to allow the repeatability and uniformity of the processes and measured results to be determined.
  • a high-k dielectric layer of HfO x is deposited on an active region of "coupon b" using an ALD process as discussed previously.
  • a titanium nitride barrier layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the titanium nitride barrier layer using an ALD process as discussed previously.
  • ALD deposition parameters can be varied among the various site -isolated regions during the deposition of the Hf x Al y C z work function metal layers.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • Stack - D may be repeated in several of the site-isolated regions to allow the repeatability and uniformity of the processes and measured results to be determined.
  • a high-k dielectric layer of HfO x is deposited on an active region of "coupon b" using an ALD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • ALD deposition parameters can be varied among the various site-isolated regions during the deposition of the Hf x Al y C z work function metal layers.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • Stack - E may be repeated in several of the site-isolated regions to allow the repeatability and uniformity of the processes and measured results to be determined.
  • FIG. 8 presents data that illustrate the ALD growth behavior of Hf x Al y C z as a function of HfC precursor pulse times.
  • Plotted in FIG. 8 are XRF hafnium raw counts (kilo-cycles per second - kcps) on the left y-axis and Hf x Al y C z film thickness in angstroms on the right y-axis.
  • the data presented in FIG. 8 indicate that 40 seconds of HfCU precursor pulse time is sufficient for ALD saturation (e.g. the thickness does not continue to change for longer pulse times).
  • FIG. 9 plots the XRF raw counts of aluminum normalized by the hafnium raw counts. The data in FIG.
  • the concentration of aluminum was varied within a range between 10 atomic % and 13 atomic % by adjusting the HfCU pulse time.
  • the composition of Al can be changed by varying other process parameters such as temperature or pressure. Without being limited by any particular theory, it is believed that the longer pulse times of the HfCU precursor allows more of the active sites on the substrate surface to be blocked, thereby limiting the number of sites available for the deposition of the aluminum species.
  • the concentration of aluminum was confirmed by RBS measurements of the film compositions.
  • FIG. 10 presents data that illustrate the ALD growth behavior of Hf x Al y C z as a function of TMA precursor pulse times. Plotted in FIG. 10 are XRF hafnium raw counts (kilo-cycles per second - kcps) on the left y-axis and Hf x Al y C z film thickness in angstroms on the right y-axis.
  • FIG. 10 plots the XRF raw counts of aluminum normalized by the hafnium raw counts.
  • the aluminum concentration is not a strong function of the TMA pulse times, as seen in FIG. 11. Therefore, the HfCU pulse time can be used to vary the aluminum concentration in the Hf x Al y C z films.
  • the titanium nitride adhesion layer deposited above the Hf x Al y C z work function metal layer using an ALD process discussed previously provides enhanced adhesion between the Hf x Al y C z work function metal layer and the electrodes used for electrical testing.
  • An alternative method for enhancing the adhesion to the Hf x Al y C z work function metal layer includes incorporating a series of vacuum anneal steps within the deposition process of the Hf x Al y C z work function metal layer. As an example, about 10A of the Hf x Al y C z work function metal layer can be deposited followed by a vacuum anneal (e.g. about 5 minutes). This sequence can be repeated 5 times to yield a Hf x Al y C z work function metal layer with a thickness of about 50A.
  • FIG. 12 presents compositional data determined using RBS after about one week of exposure to ambient air. Data is presented for samples deposited using 60 second HfC pulses and samples deposited using 60 second HfCU pulses. Data is presented for samples that included the titanium nitride adhesion layer and samples that did not include the titanium nitride adhesion layer. As discussed previously, the samples deposited using the longer HfCU pulse time exhibited lower aluminum concentration.
  • the samples that included the titanium nitride adhesion layer contained low levels of oxygen and carbon was present as expected.
  • FIG. 13 presents XRD data for various Hf x Al y C z films having different concentrations of aluminum (e.g. different deposition conditions). These data indicate the presence of crystalline peaks for hafnium carbide for the as-deposited films that also included the titanium nitride adhesion layer. The hafnium carbide peaks are broad, indicating a poly-crystalline phase.
  • FIG. 14 presents data for the resistivity of the Hf x Al y C z layer as a function of various deposition conditions, in-situ anneal conditions before the titanium nitride adhesion layer deposition, and the thickness of the titanium nitride adhesion layer.
  • the samples that included a titanium nitride adhesion layer with a thickness of 5 OA exhibited lower resistivities than the samples that included a titanium nitride adhesion layer with a thickness of 20A. Both thicknesses of the titanium nitride adhesion layer provide sufficient prevention of oxidation, which would have significantly increased the film resistivity.
  • the resistivity was independent of the various in- situ anneal conditions (e.g.
  • Hf x Al y C z resistivity was >4000 ⁇ -cm, but could be decreased by reducing the impurity level in the film, or by implementing the titanium nitride adhesion layer deposition without air break between the Hf x Al y C z and titanium nitride chambers (e.g. vacuum transfer within the cluster system).
  • MOSCAP structures were formed to determine the electrical performance of multilayer stacks incorporating Hf x Al y C z work function metal layers.
  • the multilayer stacks were similar to those described with reference to FIG. 7.
  • a high-k dielectric layer of HfO x is deposited on an active region using an
  • a titanium nitride barrier layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • a titanium nitride work function metal layer is deposited above the titanium nitride barrier layer using a PVD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the titanium nitride work function metal layer using an ALD process as discussed previously.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • a high-k dielectric layer of HfO x is deposited on an active region using an ALD process as discussed previously.
  • a titanium nitride barrier layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the titanium nitride barrier layer using an ALD process as discussed previously.
  • the thin titanium nitride barrier between the HfO x high-k dielectric layer and the Hf x Al y C z work function metal was sufficiently thin such that the titanium nitride barrier layer did not contribute to the effective work function (EWF) (i.e.
  • the EWF is determined by the work function metal that is on top of the thin titanium nitride barrier layer).
  • the aluminum concentration in the Hf x Al y C z work function metal layer can be 10 atomic %.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • a high-k dielectric layer of HfO x is deposited on an active region using an
  • a titanium nitride barrier layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the titanium nitride barrier layer using a deposition-anneal ALD process as discussed previously.
  • the thin titanium nitride barrier between the HfO x high-k dielectric layer and the Hf x Al y C z work function metal was sufficiently thin such that the titanium nitride barrier layer did not contribute to the effective work function (EWF) (i.e. the EWF is determined by the work function metal that is on top of the thin titanium nitride barrier layer).
  • EWF effective work function
  • ALD deposition parameters can be varied among the various site-isolated regions during the deposition of the Hf x Al y C z work function metal layers.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • a high-k dielectric layer of HfO x is deposited on an active region using an ALD process as discussed previously.
  • a titanium nitride barrier layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • the Hf x Al y C z work function metal layer has an aluminum concentration of about 10 atomic %.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • a high-k dielectric layer of HfO x is deposited on an active region using an ALD process as discussed previously.
  • a titanium nitride barrier layer is deposited above the HfO x high-k dielectric layer using an ALD process as discussed previously.
  • a Hf x Al y C z work function metal layer is deposited above the titanium nitride barrier layer using an ALD process as discussed previously.
  • the thin titanium nitride barrier between the HfO x high-k dielectric layer and the Hf x Al y C z work function metal was sufficiently thin such that the titanium nitride barrier layer did not contribute to the effective work function (EWF) (i.e.
  • the EWF is determined by the work function metal that is on top of the thin titanium nitride barrier layer).
  • the aluminum concentration in the Hf x Al y C z work function metal layer can be 13 atomic %.
  • a titanium nitride adhesion layer is deposited above the Hf x Al y C z work function metal layer using an ALD process as discussed previously.
  • a tungsten layer is deposited above the titanium nitride adhesion layer using a PVD process as discussed previously.
  • FIG. 15 presents capacitance - voltage (C-V) data for Stacks I - V described previously, from which the flat band voltage (Vfb) values summarized in FIG. 16 were extracted. From FIGs. 15 and 16, a clear 220 - 250mV shift in the Vfb was observed in the negative direction for the Hf x Al y C z samples (Stacks II - V), relative to the Vfb of the titanium nitride reference sample (Stack I). The Vfb distributions of Stacks II - V in FIG. 16 were comparable to that of Stack I.
  • FIG. 17 summarizes the EWF values that were calculated from the Vfb values.
  • the EWF of the devices with the Hf x Al y C z work function metal layers was 4.6eV, which is mid-gap relative to the titanium nitride reference, which has an EWF of 4.83eV.
  • the EWF was similar for all the Hf x Al y C z splits with varying Al content and deposition conditions, indicating a robust process with a wide process window.
  • CET capacitance equivalent thickness
  • FIG. 18 presents data for the CET values for the various samples (i.e. Stacks I - V).
  • the CET and CET distributions for the samples with the Hf x Al y C z work function metal layers (i.e. Stacks II - V) are similar to the sample with the titanium nitride work function metal layer (i.e. Stack I), except for the sample where the CET values are significantly higher due to the removal of the titanium nitride barrier between the HfCh high-k dielectric layer and the Hf x Al y C z work function metal layer (e.g. the Hf x Al y C z layer is in direct contact with the HfCh layer - Stack IV).
  • FIG. 19 presents data for the Jg values for the various samples (i.e. Stacks I - V).
  • the leakage current density is also lower due to the removal of the titanium nitride barrier between the Hf0 2 high-k dielectric layer and the Hf x Al y C z work function metal layer (e.g. the Hf x Al y C z layer is in direct contact with the HfCh layer - Stack IV), relative to the other samples that included the Hf x Al y C z work function metal layer.
  • the high CET and the low leakage current density indicate a physical re-growth of a dielectric material when the Hf x Al y C z work function metal layer is in direct contact with the Hf(3 ⁇ 4 high-k dielectric material. It is possible that the Hf x Al y C z work function metal layer was prone to oxidation, and a portion of the layer may have been oxidized due to oxygen transferred from the underlying HfC>2 high-k dielectric layer, leading to an overall increase in the thickness of the dielectric layer.
  • the thin titanium nitride barrier between the Hf x Al y C z work function metal layer and HfC>2 high-k dielectric layer prevented this oxidation.
  • the leakage current density (and distributions) of the samples that included the Hf x Al y C z work function metal layer are generally higher than that of the sample with the titanium nitride reference (i.e. Stack I), but acceptable at ⁇ lA/cm 2 .
  • the Hf x Al y C z work function metal layer is not expected to cause significant device degradation, and the Hf x Al y C z work function metal layer will be thermally stable up to the 500C forming gas anneals that were performed on the MOSCAP devices prior to electrical testing.

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Abstract

L'invention porte sur le dépôt de couches atomiques (ALD) de films d'HfxAlyCz à l'aide de précurseurs de chlorure d'hafnium (HfC14) et de triméthylaluminium (TMA), qui peuvent être combinés avec des processus de recuit après dépôt et des doublures formées par ALD pour régler les caractéristiques de dispositif dans des dispositifs à grille métallique à haut coefficient k. Des variations de la durée de l'impulsion de HfCl4 permettent le réglage du % d'incorporation d'Al dans le film d'HfxAlyCz dans la plage de 10-13 %. Des outils de traitement combinatoire peuvent être utilisés pour la caractérisation rapide des propriétés électriques et de matériau de divers empilements de matériaux. Le travail de sortie effectif (EWF) dans des dispositifs à condensateur à semi-conducteur en oxyde métallique (MOSCAP) renfermant la couche de travail de sortie en HfxAlyCz couplée à des couches diélectriques de grille à haut coefficient k en HfO2 déposées par ALD a été quantifié comme étant à mi-bande interdit à ~4,6 eV. Ainsi, HfxAlyCz est un matériau de travail de sortie de grille métallique prometteur permettant la mise au point de tensions de seuil de dispositif (Vth) pour des dispositifs à circuit intégré (IC) multi-Vth prévus.
PCT/US2014/023375 2013-03-11 2014-03-11 Dépôt de couches atomiques de hfalc utilisé comme matériau de travail de sortie de grille métallique dans des dispositifs à mos Ceased WO2014164742A1 (fr)

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CN114551357A (zh) * 2022-02-21 2022-05-27 中国科学院微电子研究所 堆叠纳米片环栅cmos器件及其制备方法

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