WO2014169681A1 - Diviseur de fréquence programmable multimode - Google Patents

Diviseur de fréquence programmable multimode Download PDF

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Publication number
WO2014169681A1
WO2014169681A1 PCT/CN2013/090479 CN2013090479W WO2014169681A1 WO 2014169681 A1 WO2014169681 A1 WO 2014169681A1 CN 2013090479 W CN2013090479 W CN 2013090479W WO 2014169681 A1 WO2014169681 A1 WO 2014169681A1
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WO
WIPO (PCT)
Prior art keywords
terminal
frequency
frequency dividing
frequency division
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/090479
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English (en)
Chinese (zh)
Inventor
易律凡
彭关超
刘永才
谢豪律
周栋梁
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ZTE Corp
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ZTE Corp
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Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage

Definitions

  • the present invention relates to the field of frequency divider design, and more particularly to a multimode programmable frequency divider. Background technique
  • the frequency synthesizer provides the carrier signal for the transceiver
  • the programmable frequency divider is the core device in the frequency synthesizer. It directly controls the channel selection and is the key to the overall tunable chip design. Therefore, high operating frequencies, wide division ratio ranges, low power consumption, etc. are usually the general requirements of the system for the divider.
  • the multimode programmable frequency divider is a programmable frequency divider designed based on the cascade of 2/3 frequency division units.
  • the range of the frequency division ratio is easy to expand, and the module circuits in this structure are basically the same. Strong use.
  • a wide-range multi-mode programmable frequency divider in the prior art is shown in FIG. 1, and the total number n of the 2/3 frequency dividing unit is determined according to the maximum value of the required frequency dividing ratio, and then according to the minimum frequency dividing ratio.
  • the value determines that there is no need to add the number of 2/3 frequency division units Ne, and each 2/3 frequency division unit is connected in series, wherein the front Ne level is a standard 2/3 frequency division cascade, and the subsequent levels are bands
  • the 2/3 division of the extension bits is cascaded. This circuit can effectively extend the division ratio of the multimode programmable divider.
  • the structure of the conventional 2/3 frequency dividing unit is as shown in FIG. 2, and the conventional 2/3 frequency dividing unit has a trigger signal input terminal f in , a mode control signal input terminal modi, a set terminal P, and a trigger signal. Output f. And a mode control signal output terminal mod. ; Trigger signal output terminal f.
  • the trigger signal input terminal f in is connected to the second-stage 2/3 frequency dividing unit of the second stage, and the digitizing terminal P is configured to receive the divisor signal to select the frequency dividing unit to perform the divide by 2 or divide the 3 working mode, the first level 2/3
  • the trigger signal input terminal of the frequency dividing unit is connected to the source pulse.
  • the 2/3 divider with extension bits is a traditional 2/3 division
  • the element is improved, and its structure is shown in Figure 3.
  • the 2/3 of the part is disabled by the multi-mode programmable frequency divider that achieves the highest division ratio.
  • the frequency unit implements a downward expansion of the frequency division range.
  • the traditional multi-mode programmable frequency divider is a circuit with a current mode logic (CML) structure, which consumes a lot of power and is complicated.
  • a multimode programmable frequency divider based on a True Single Phase Clock (TSPC) architecture circuit can effectively reduce the power consumption of the circuit compared to a multimode programmable frequency divider using a CML architecture circuit.
  • TSPC True Single Phase Clock
  • the existing multimode programmable frequency dividers are in a different frequency division ratio, and each 2/3 frequency division unit is in the working mode, which will inevitably result in waste of power consumption of the multimode programmable frequency divider. Summary of the invention
  • embodiments of the present invention provide a multi-mode programmable frequency divider.
  • the embodiment of the invention provides a multi-mode programmable frequency divider, comprising: a main frequency dividing stage composed of cascaded 2/3 frequency dividing units, wherein the cascaded 2/3 frequency dividing unit does not have a frequency dividing unit
  • the number of 2/3 division units of the extension bit is Ne
  • the number of 2/3 division units with the division ratio extension bit is n-Ne
  • Ne is the effective number of bits of the multimode programmable frequency divider
  • the multimode programmable frequency divider further includes: a real-time power consumption control circuit and a power switch control transistor.
  • the real-time power consumption control circuit is composed of two-input AND gates of n-Ne-1 level, and the reverse signal Pinv[n] of the frequency division ratio control bit P[n] of the n-th stage 2/3 frequency division unit is connected to the nth
  • the aspect is connected to the Power_Ctrl terminal of the n-1th 2/3 frequency dividing unit, and on the other hand, the inverse of the frequency dividing ratio control bit P[n-2] of the n-2th 2/3 frequency dividing unit.
  • the signal Pinv[n-2] is connected to the n-1th level and the gate Two inputs; and so on, until the n-Ne stage 2/3 frequency dividing unit and the n-Ne-1 level AND gate; the power switch control transistor has a drain connected to the corresponding band division ratio extension bit
  • the power supply terminal of the 2/3 frequency dividing unit, the source is connected to the power supply, and the gate is connected to the Power_Ctrl terminal of the 2/3 frequency dividing unit with the frequency dividing ratio extension bit.
  • the total number n of the cascaded 2/3 frequency division units is determined according to a required maximum frequency division ratio, the maximum frequency division ratio is 2 n+1 ⁇ l , and the minimum of the multimode programmable frequency divider is The division ratio is determined according to the effective number of bits Ne of the multimode programmable frequency divider, and the minimum division ratio is 2 Ne+1 .
  • the 2/3 frequency division unit with the frequency division ratio extension bit, the reverse signal output P2inv of the extension bit is a real-time control signal
  • power_Ctrl is the controlled end
  • the three triggers DFF1, DFF2, DFF3 are Trigger with dual input D1, D2, DFF4 is a single input trigger, the clock of all the triggers is derived from the trigger signal input terminal fin;
  • the QB terminal of DFF4 contacts the signal output terminal fo;
  • the D2 terminal of DFF3 is connected to the mode control signal input Terminal modi, Dl terminates the Q end of DFF4;
  • DFF2 D2 terminal is connected to the terminal PI, D1 is terminated to the Q terminal of DFF3;
  • DFF1 D2 is connected to the QB end of DFF2, D1 is terminated to the QB end of DFF4, that is, fo;
  • the D terminal of DFF4 is connected to the Q terminal of DFF1;
  • the terminal P2 is connected to the input terminal of inverter I
  • the output terminal of AND1 is connected to the mode control signal output terminal modo; PI and P2 are also connected to the input terminal of AND gate AND2, and the output terminal of AND2 is connected to P0 12 ; the source terminal Vt of all DFF is connected to the power switch control transistor. Drain, the gate of the power switch control transistor is connected to power-Ctrl, the power switch controls the transistor To the power source.
  • the 2/3 frequency division unit with the frequency division ratio extension bit adopts a true single phase clock D flip-flop TSPC DFF.
  • the 2/3 frequency division unit with the frequency division ratio extension bit adopts a TSPC DFF with a built-in AND gate.
  • the power switch control transistor is a P-channel field effect transistor PMOS.
  • a multi-mode programmable frequency divider provided by an embodiment of the present invention can control a multi-mode frequency divider in different frequency divisions by adding a real-time power consumption control circuit and a power switch control transistor. Compared with the working condition of the 2/3 frequency dividing unit, the power consumption of the multi-mode programmable frequency divider is effectively avoided.
  • FIG. 1 is a schematic structural view of a wide-range multi-mode programmable frequency divider in the prior art
  • FIG. 2 is a schematic structural view of a conventional 2/3 frequency dividing unit in the prior art
  • FIG. 3 is a schematic structural diagram of a 2/3 frequency division unit with an extension bit in the prior art
  • FIG. 4 is a schematic structural diagram of a multimode programmable frequency divider according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a 2/3 frequency division unit according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a circuit of a TSPC DFF according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a circuit structure of a TSPC DFF with a built-in AND gate according to an embodiment of the present invention. detailed description
  • a multi-mode programmable frequency divider provided by an embodiment of the present invention includes: a primary frequency division level composed of cascaded 2/3 frequency division units, and 2/3 points of the cascade
  • the number of 2/3 frequency division units without frequency division extension bits in the frequency unit is Ne
  • the number of 2/3 frequency division units with frequency division ratio extension bits is n-Ne
  • Ne is the multimode programmable
  • the effective number of bits of the frequency divider; the total number n of the cascaded 2/3 frequency dividing units is determined according to a required maximum frequency dividing ratio, and the maximum frequency dividing ratio is 2 n+1 -l
  • the multimode can be
  • the minimum division ratio of the programming frequency divider is determined according to the effective number of bits Ne of the multimode programmable frequency divider, and the minimum division ratio is 2 Ne+1 ; in the structure diagram shown in FIG. 4, the front Ne
  • the level is a standard 2/3 frequency division unit (
  • the multi-mode programmable frequency divider further includes: a real-time power consumption control circuit and a power switch control transistor, wherein
  • the real-time power consumption control circuit is composed of two-input and gates of n-Ne-1 level, and the inverse signal Pinv[n] of the frequency division ratio control bit P[n] of the n-th stage 2/3 frequency division unit is connected to the nth stage 2 /3 frequency division unit power control Positioning power— Ctrl; the ratio of the inverse signal Pinv[n] of the division ratio control bit P[n] of the nth stage 2/3 division unit and the division ratio of the n-1th stage 2/3 division unit
  • the inverted signal Pinv[n-1] of the control bit P[n-1] is connected to the two input terminals of the nth AND gate, and the output of the nth AND gate is connected to the n-1th level 2 on the one hand.
  • the Power_ Ctrl terminal of the /3 frequency division unit is connected to the reverse signal Pinv[n-2] of the division ratio control bit P[n-2] of the n-2th 2/3 division unit.
  • the power_ Ctrl terminal of the /3 frequency division unit is connected to the reverse signal Pinv[n-2] of the division ratio control bit P[n-2] of the n-2th 2/3 division unit.
  • ⁇ denotes the trigger signal input
  • f Indicates the trigger signal output
  • modi represents the mode control signal input
  • mod. Indicates the mode control signal output
  • power—Ctrl indicates the power control bit.
  • the drain of the power switch control transistor is connected to the power supply terminal of the 2/3 frequency dividing unit with the frequency division ratio extension bit, and the source is connected to the power supply.
  • the power switch control transistor may be a P-channel field effect transistor (PMOS transistor).
  • the multi-mode programmable frequency divider has a 2/3 frequency division unit with a frequency division ratio extension bit, and the structure thereof is as shown in FIG. 5, and the frequency division ratio extension bit of the embodiment of the present invention is 2
  • the /3 frequency division unit is implemented based on the improvement of the 2/3 frequency division unit with the frequency division ratio extension bit in the prior art; the 2/3 frequency division unit with the frequency division ratio extension bit in the embodiment of the present invention,
  • the reverse signal output P2inv of the extension bit P[n] is the real-time control signal
  • power_Ctrl is the controlled terminal
  • three flip-flops DFF1, DFF2, DFF3 are triggers with dual inputs D1, D2, and DFF4 is single-input trigger
  • the trigger of all the triggers is derived from the trigger signal input terminal fin; the QB terminal of DFF4 is connected to the output fo (ie, the trigger signal output terminal); the D2 terminal of the DFF3 is connected to the mode control signal input terminal modi, and the D1 terminal is
  • the output of AND1 is connected to the mode control signal output terminal modo; PI and P2 are also connected to the input terminal of AND2 (AND gate), and the output terminal of AND2 is connected to P0 12 ;
  • the source Vt of all DFFs is connected
  • the power switch controls the drain of the transistor (such as PMOS transistor PM1), the gate of the power switch control transistor (such as PM1) is connected to ower ctrl, and the source of the power switch control transistor (such as PM1) is connected to the power supply.
  • the drain of the power switch control transistor PM1 is connected to the source terminal Vt of the 2/3 frequency dividing unit, and the source is connected to the power supply. Then, the power switch control transistor controls the corresponding 2/3 frequency dividing unit according to the signal received by the power Ctrl.
  • the power supply is connected or disconnected for real-time control of the power consumption of the multimode programmable divider.
  • the 2/3 frequency division unit with the frequency division ratio extension bit in the embodiment of the present invention can adopt the circuit structure of the TSPC DFF as shown in FIG. 6, which adopts a technique for optimizing the glitch and charge sharing effect, thereby Can improve the working speed of multi-mode programmable frequency divider;
  • the 2/3 frequency division unit with the frequency division ratio extension bit in the embodiment of the present invention can also adopt the circuit structure of the TSPC DFF with built-in AND gate shown in FIG. 7, and usually, the AND gate and the D flip-flop It is two different parts, and the structure shown in Figure 7 is an improvement on the structure shown in Figure 6. It will be combined with the gate and the D flip-flop, that is, only the PMOS tube PM1 and the NMOS tube NM1 connected to the D2 terminal are added. The function of the AND gate and Figure 6 is realized, thereby shortening the length of the critical path, reducing the number of transistors, increasing the operating frequency, and reducing power consumption.
  • the multi-mode programmable frequency divider of the embodiment of the present invention can control the multi-mode frequency divider in different frequency division ratios by 2/3 in real time by adding a real-time power consumption control circuit and a power switch control transistor.
  • the working condition of the frequency dividing unit effectively avoids waste of power consumption of the multimode programmable frequency divider; in addition, the circuit structure of the embodiment of the invention is simple, and only a series of AND gates are added on the basis of the original multimode programmable frequency divider.
  • the PMOS transistor, and the added gate operates at the output signal frequency, without adding additional power.

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention concerne un diviseur de fréquence programmable multimode, comprenant : des unités de division de fréquence 2/3 montées en cascade, un circuit de régulation de la consommation d'énergie en temps réel et un transistor de commande de commutateur de puissance, le nombre d'unités de division de fréquence non dotées du bit d'extension du rapport de division de fréquence et le nombre d'unités de division de fréquence dotées du chiffre d'extension étant respectivement Ne et n-Ne ; le circuit de régulation de la consommation d'énergie en temps réel est composé de n-Ne-1 niveaux de portes ET à deux entrées ; le signal inverse du bit de commande du rapport de division de fréquence du n-ème niveau de l'unité de division de fréquence est connecté au bit de régulation d'énergie du n-ème niveau de l'unité de division de fréquence ; le signal inverse, et le signal inverse du bit de commande du rapport de division de fréquence du (n-1)-ème niveau de l'unité de division de fréquence sont connectés à l'extrémité d'entrée du n-ème niveau de la porte ET ; l'extrémité de sortie du n-ème niveau de la porte ET est connectée au bit de régulation d'énergie du (n-1)-ème niveau de l'unité de division de fréquence et le signal inverse du bit de commande du rapport de division de fréquence du (n-2)-ème niveau de l'unité de division de fréquence est par conséquent connecté à l'extrémité d'entrée du (n-1)-ème niveau de la porte ET ; les connexions suivantes sont réalisées d'une manière similaire jusqu'à ce que le signal inverse du bit de commande du rapport de division de fréquence du (n-Ne)-ème niveau de l'unité de division de fréquence soit connecté à l'extrémité d'entrée du (n-Ne-1)-ème niveau de la porte ET ; le drain du transistor de commande de commutateur de puissance est connecté aux extrémités d'alimentation des unités de division de fréquence dotées du bit d'extension, la source du transistor de commande de commutateur de puissance est connectée à une alimentation électrique et la grille du transistor de commande de commutateur de puissance est connectée aux bits de régulation d'énergie des unités de division de fréquence dotées du bit d'extension.
PCT/CN2013/090479 2013-04-19 2013-12-25 Diviseur de fréquence programmable multimode Ceased WO2014169681A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310138544.X 2013-04-19
CN201310138544.XA CN104113325B (zh) 2013-04-19 2013-04-19 一种多模可编程分频器

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106209071B (zh) * 2015-04-29 2019-02-19 珠海全志科技股份有限公司 可任意编程的双模分频器
US9577646B1 (en) * 2015-08-07 2017-02-21 Qualcomm Incorporated Fractional phase locked loop (PLL) architecture
CN107565964B (zh) * 2017-08-26 2020-12-18 复旦大学 一种扩展分频比的可编程分频器
CN110677153A (zh) * 2019-10-15 2020-01-10 成都振芯科技股份有限公司 可扩展分频比范围的高速分频器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969548A (en) * 1997-09-18 1999-10-19 Siemens Aktiengesellschaft Frequency divider with low power consumption
US6067339A (en) * 1997-09-18 2000-05-23 Siemens Aktiengesellschaft Frequency divider with lower power consumption
CN1604475A (zh) * 2003-09-29 2005-04-06 联发科技股份有限公司 可编程多模数分频器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969548A (en) * 1997-09-18 1999-10-19 Siemens Aktiengesellschaft Frequency divider with low power consumption
US6067339A (en) * 1997-09-18 2000-05-23 Siemens Aktiengesellschaft Frequency divider with lower power consumption
CN1604475A (zh) * 2003-09-29 2005-04-06 联发科技股份有限公司 可编程多模数分频器

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CN104113325A (zh) 2014-10-22

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