WO2014169690A1 - Méthode et dispositif de traitement de mappage d'adresse - Google Patents

Méthode et dispositif de traitement de mappage d'adresse Download PDF

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Publication number
WO2014169690A1
WO2014169690A1 PCT/CN2013/090967 CN2013090967W WO2014169690A1 WO 2014169690 A1 WO2014169690 A1 WO 2014169690A1 CN 2013090967 W CN2013090967 W CN 2013090967W WO 2014169690 A1 WO2014169690 A1 WO 2014169690A1
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Prior art keywords
address
physical
segment
logical
addresses
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PCT/CN2013/090967
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English (en)
Chinese (zh)
Inventor
黄苏
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ZTE Corp
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ZTE Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Definitions

  • the present invention relates to address mapping technology in the field of data communication, and in particular, to a method and apparatus for address mapping processing. Background technique
  • Double Data Rate Synchronous Random Access Memory is a new generation of memory technology standards issued by the Joint Commission on Electronic Equipment (JEDEC) and 2004. Due to its low price, high bandwidth data throughput and low power consumption, DDR SDRAM is widely used in the field of data communication where storage is demanding. However, in the field of data communication chips, the chip's key performance index is the number of packets per second (PPS), which determines that the DDR SDRAM used for packet buffering must achieve the lowest read and write efficiency to meet the processing power of the chip. At the same time, because of cost factors, it is not possible to increase the data throughput of the entire chip simply by increasing the number of physical slices of DDR SDRAM.
  • PPS packets per second
  • DDR SDRAM is widely used in the field of data communication chips. It is used to buffer packet data during message processing. It is currently the third generation of DDR, namely DDR3 SDRAM. This article is referred to as DDR3.
  • the general processing mode of the data communication chip is as follows: After the data packet is processed by the MAC layer, the packet is first buffered into the off-chip DDR3 chip, and the DDR3 physical address of the buffered data packet is generated, and is continued as part of the packet characteristic information. Protocol and handling of QoS functions. For Ethernet data packets, the minimum length of the packet is 64B. At the same time, the current DDR3 burst address width is 16B. You can see that at least 4 burst addresses are required for a data packet. If the DDR3 physical address of the data packet is directly used as its The feature information needs to carry at least 4 physical addresses, resulting in an increase in resources.
  • a logical address represents a number of DDR3 physical addresses. This scheme requires a mapping relationship between the logical address and the physical address of DDR3.
  • the solution wastes RAM resources and does not enable efficient management of physical addresses.
  • the main purpose of the embodiments of the present invention is to provide a method and an apparatus for address mapping processing, which not only saves RAM resources, but also implements efficient management of physical addresses.
  • a method for address mapping processing comprising:
  • mapping between the logical address and the physical address is performed according to the logical addresses of the interval segments after the partition.
  • the partitioning the logical address according to the currently configured number of DDRs specifically includes: obtaining a total physical bank number according to the number of DDRs and the number of physical bank banks included in each DDR;
  • the total logical address is divided into a plurality of logical address segments, and the number of segments is a maximum value of 2n among all the common divisors of the total physical bank number, and the n refers to the number of linked lists in the segment.
  • mapping between the logical address and the physical address according to the logical addresses of the interval segments after the partitioning includes:
  • each logical address segment corresponds to a physical bank, and is a one-to-one mapping between a logical address and a physical address;
  • each logical address segment corresponds to multiple physical banks, which is a one-to-many mapping between logical addresses and physical addresses.
  • the method further includes: configuring, in the one-to-many mapping, each segment of the physical bank Offset base address, the number of offset base addresses in the segment is nl.
  • the method further includes: obtaining, according to the offset base address and the intra-segment offset address in the segment, an intra-segment offset physical bank address corresponding to the intra-segment offset address.
  • the method further includes: obtaining a corresponding physical row address and a physical column address according to the offset physical bank address in the segment.
  • An apparatus for address mapping processing comprising: a partition processing unit and a mapping processing unit; wherein
  • the partition processing unit is configured to partition the logical address according to the currently configured DDR number; the mapping processing unit is configured to perform mapping processing between the logical address and the physical address according to the logical addresses of the interval segments after the partition.
  • the partition processing unit and the mapping processing unit use a central processing unit (CPU) and a digital signal processor (DSP, Digital Singnal) when performing processing.
  • CPU central processing unit
  • DSP digital signal processor
  • the partition processing unit is further configured to obtain a total physical bank number according to the number of DDRs and the number of physical bank banks included in each DDR, and divide the total logical address into multiple logical address segments, and segment the segments.
  • the number is the maximum value of 2n among all the common divisors of the total physical bank number, and the n refers to the number of linked lists in the segment.
  • mapping processing unit is further configured to have a value of 2n, and if each logical address segment corresponds to one physical bank, the one-to-one mapping between the logical address and the physical address; when the value is not 2n, Making each logical address segment correspond to multiple physical banks is a one-to-many mapping between logical addresses and physical addresses.
  • the mapping processing unit is further configured to configure an intra-segment offset base address for each physical bank when the one-to-many mapping is performed, and the number of the offset base addresses in the segment is n-1; Offset base address and intra-segment offset address, get the intra-segment offset physical bank location corresponding to the offset address within the segment Address: obtaining a corresponding physical row address and a physical column address according to the offset physical bank address in the segment.
  • the solution of the embodiment of the present invention partitions the logical address according to the currently configured DDR number; and performs mapping processing between the logical address and the physical address according to the logical address of each interval segment after the partition.
  • the embodiment of the present invention does not directly map the logical address to the physical address for the total logical address, but performs the mapping processing after the total logical address is partitioned, thereby reducing the occupation of the logical address, thereby saving RAM resources. Fewer logical addresses make address addressing easier, and efficient management of physical addresses.
  • FIG. 3 is a schematic structural diagram of a mapping device of an application example 2 of the present invention.
  • FIG. 4 is a schematic diagram showing the structure of a decoding apparatus based on a mapping implementation decoding process according to the third application example of the present invention. detailed description
  • the solution of the embodiment of the present invention is a one-to-many mapping processing scheme between the logical address and the physical address of the DDR3, and uses the least logical address resource to meet the system design requirement, and divides the logical address into interval segments according to the number of DDR3s configured by the current system. Then, the mapping between the logical address and the physical address is performed separately by the interval segment.
  • the logical address is simply referred to as PMAU description when it is represented in the form of a linked list, and the bank of the full text refers to the physical bank instead of the logical physical bank.
  • n refers to the number of linked lists in the segment.
  • FIG. 1 is a schematic flowchart of a method according to an embodiment of the present invention, where the process includes the following steps: Step 101: Partition the logical address according to the currently configured number of DDRs.
  • Step 102 Perform one-to-many mapping processing between the logical address and the physical address according to the logical addresses of the interval segments after the partitioning.
  • mapping process of the embodiment of the present invention is specifically described by taking the total number of logical addresses as 128k and the number of variable groups of off-chip DDR3 being 1 ⁇ 5.
  • Step 201 Perform the segmentation processing on the total logical address, and adopt the equalization mode.
  • step 201 the specific process of step 201 is as follows: According to the current system configuration DDR3 group number, the total logical address idle node interval is equally divided into n segments (each segment is represented by a segment number of a logical address), wherein the number of segments is the total number of physical banks The median value of all the common divisors is 2n, so that PMAU[16:15-n] represents the segmentation address.
  • the total number of physical banks is 40, and the common divisor of 4 is 2n, which is 8, which means that when the number of DDR3 is At 5 o'clock, 40 physical banks are divided into 8 segments.
  • Step 202 For each segment, according to the intra-segment offset address and the intra-segment offset base address configured by the system, the logical address is offset from the physical bank address in the segment corresponding to the segment, that is, the intra-segment offset corresponding to the logical address. Move the physical bank number.
  • the logical address and the physical address are mapped one-to-one, according to the prior art; in the case of non- 2n, the logical address and the physical address are one-to-many mapping.
  • each segment includes only one physical bank, and the segment in the table of FIG. No. Represents the physical bank number to which the logical address belongs.
  • the segmentation interval of each logical address includes a plurality of physical banks.
  • the number of DD3s is 5 when each segment contains physics. The largest number of banks, each segment includes 5 physical banks.
  • the embodiment of the present invention sets an offset base address for each physical bank, and assumes that the number of linked lists in the segment is n, then the required physical bank
  • the number of offset base addresses is nl. Therefore, in the current example, when the number of DDR3s is 5, the required intra-segment offset base address is the most, and the number is 4.
  • the number of DDR3s is 3, under the above-mentioned segmentation rule, because each segment contains only 3 physics. Bank, so only 2 offset base addresses are needed.
  • the purpose of the partition is to obtain partition partitioning with the system-configured offset base address, such as partitions (0-1) and (1-2) identified by offset base addresses 0, 1, and 2, offset.
  • the relationship between the address and the offset base address is: continue to divide in any partition of each partition (0-1) and (1-2), and identify with an offset base address, such as partition (0-1) It is further refined by 0.1, 0.2, 0.3 0.9. It should be pointed out here that "0.1” and so on are for convenience of explanation and are described in digital form. In practical applications, the form of address representation is used, similar to the description of PMAU[13:0], which is not mentioned here.
  • the first 9 on the left represents all physical banks with a segment address of 3.
  • the physical bank base address (each segment contains 3 physical banks), and 1 indicates the offset physical bank address within the segment.
  • the intra-segment offset physical bank address corresponding to the logical address in various configurations can be obtained, which can also be referred to as the physical bank number of the logical address.
  • Step 203 Obtain the base address of the specific row and column of the offset physical bank address in the segment according to the offset physical bank address in the segment.
  • the row and column addresses can be obtained according to the current logical address and the length of each row of DDR3. For example, if the logical address and the length of each row of DDR3 are 2 KB, since each row has only one logical address, then PMAU[13:0] is Row address, the base address of the column is all 0s.
  • the calculation method of the row and column base address under various other configurations is similar.
  • the third embodiment DDR that is, DDR3, is used as an example to describe the mapping of logical addresses to physical addresses in the data chip domain, thereby implementing external cache management, but the partial cache is managed, thereby quickly and efficiently managing Implement decoding.
  • a fixed number of logical addresses is generally required for implementation.
  • a simple mapping relationship between a logical address bit field and a DDR3 physical address bit field is generally adopted.
  • the corresponding physical bank address, row address, and burst column address width are 3bit, 14bit, and 7bit, respectively, if each logical address Fixed to 2KB and the number of logical addresses is fixed at 128K, because DDR3 is 2KB per line, so the logical address is the base address of each row, and the decoding method of logical address to physical base address is simpler.
  • the highest 3bit corresponds to the physical bank.
  • the address, the middle 14bit corresponds to the row address, and the lowest bit low bit is 0, which is the column base address method to complete the decoding.
  • the number of DDR3s required for actual use is often not an integer power of two, such as three groups. If such a simple decoding method is still required, a 19-bit representation is required for the number of 128K logical addresses.
  • the system solution requirements of the shared cache generally require the use of a table to manage the logical address, and the logical address needs to be the addressing pointer of the RAM, which will result in a waste of four times the required RAM resources.
  • the mapping between the logical address and the physical address is performed separately in the segment, and the system design requirement can be satisfied by using the minimum logical address resource, for example, the number of logical addresses of 128K, and the 17-bit representation is fixedly used, thereby adopting the embodiment of the present invention.
  • the system RAM resources are saved to the greatest extent, and the efficient management of physical addresses can be realized, mainly by address mapping to implement address addressing.
  • Application Example 2 A mapping device based on a mapping scheme that implements an embodiment of the present invention.
  • the mapping device is located on the cache side, and includes: a partition processing unit and a mapping processing unit; wherein, the partition processing unit is configured to partition the logical address according to the currently configured DDR number; and the mapping processing unit is configured to The logical address of the interval segment performs mapping processing between the logical address and the physical address.
  • the partition processing unit is further configured to obtain the total physical bank number according to the number of DDRs and the number of physical bank banks included in each DDR, and divide the total logical address into a plurality of logical address segments, and the number of segments is The value of all the common divisors of the total physical bank number is 2n A large value, the n refers to the number of linked lists in the segment.
  • each logical address segment corresponds to one physical bank, and is a one-to-one mapping between the logical address and the physical address; if the value is not 2n, each is made
  • a logical address segment corresponding to multiple physical banks is a one-to-many mapping between a logical address and a physical address.
  • mapping processing unit in the one-to-many mapping is: the mapping processing unit is configured to configure an intra-segment offset base address for each physical bank, and the number of offset base addresses in the segment is n- 1; according to the offset base address and the intra-segment offset address in the segment, obtain an intra-segment offset physical bank address corresponding to the intra-segment offset address; and obtain a corresponding physical row address according to the offset physical bank address in the segment And the physical column address.
  • Application Example 3 A decoding process implemented by a mapping scheme according to an embodiment of the present invention.
  • App_pmau_vld a valid indication of the logical address to be decoded
  • App_pmau the logical address to be decoded
  • DFF D trigger
  • Pmau fld the segment number of the logical address to be decoded parsed according to the number of DDR groups
  • pmau-fld_offset the intra-segment offset address of the logical address to be decoded
  • Pmau farld—physical bank: offset the physical bank number according to the intra-segment offset address and the intra-segment base address comparison;
  • Ddr physical bank— addr: the resolved physical bank address
  • Ddr row addr the resolved physical row address
  • Ddr col addr the resolved physical column address
  • Pmau physical bank—offset: the physical bank internal offset address of the ddr logical address to be parsed
  • Cfg physical bank—addr[i]: the user-configured intra-segment base address for comparison, the total number is i;
  • Cfg ddrc num Number of configured DDR groups.
  • the decoding process (decoding from logical address to physical address) implemented by the above decoding apparatus includes the following contents:
  • the intra-segment offset address belongs to the first physical bank in the segment, that is, the segment Internal offset physical bank number ( pmau - fld - physical bank [2:0] ) and offset physical address ( pmau - physical bank - offset ) in the corresponding physical bank.
  • the row number and the column number of the physical address are obtained according to the offset physical address in the physical bank (the specific row address and column address of the physical address are obtained);
  • the solution of the embodiment of the present invention partitions the logical address according to the currently configured DDR number; and performs mapping processing between the logical address and the physical address according to the logical address of each interval segment after the partition.
  • the embodiment of the present invention does not directly map the logical address to the physical address for the total logical address, but performs the mapping processing after the total logical address is partitioned, thereby reducing the occupation of the logical address, thereby saving RAM resources. Fewer logical addresses make address addressing easier, and efficient management of physical addresses.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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Abstract

L'invention concerne une méthode et un dispositif de traitement de mappage d'adresse. La méthode comprend les étapes suivantes : selon le nombre de mémoires vives dynamiques synchrones à double débit binaire (DDR) qui sont configurées actuellement, partitionner une adresse logique ; et en fonction de l'adresse logique de chaque segment de plage partitionnée, effectuer un traitement de mappage respectivement entre l'adresse logique et une adresse physique. Une unité de traitement de mappage du dispositif est configurée pour effectuer un traitement de mappage respectivement entre une adresse logique et une adresse physique en fonction de l'adresse logique de chaque segment de plage partitionnée. Grâce à la présente invention, on peut économiser des ressources de RAM, et on peut gérer efficacement une adresse physique.
PCT/CN2013/090967 2013-04-15 2013-12-30 Méthode et dispositif de traitement de mappage d'adresse Ceased WO2014169690A1 (fr)

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CN106547702B (zh) * 2016-09-27 2019-09-10 中国电子科技集团公司第三十八研究所 一种双模8访存地址计算方法
CN107870870B (zh) * 2016-09-28 2021-12-14 北京忆芯科技有限公司 访问超过地址总线宽度的内存空间
CN107870867B (zh) * 2016-09-28 2021-12-14 北京忆芯科技有限公司 32位cpu访问大于4gb内存空间的方法与装置
CN110851372B (zh) * 2018-08-20 2023-10-31 慧荣科技股份有限公司 储存装置及快取区定址方法
CN111367461B (zh) * 2018-12-25 2024-02-20 兆易创新科技集团股份有限公司 一种存储空间管理方法及装置
CN110781101A (zh) * 2019-10-25 2020-02-11 苏州浪潮智能科技有限公司 一种一对多映射关系的存储方法、装置、电子设备及介质
CN114328286B (zh) * 2022-03-14 2022-07-15 南京芯驰半导体科技有限公司 一种提升系统访存性能的方法
CN114707478B (zh) * 2022-06-06 2022-09-02 飞腾信息技术有限公司 映射表生成方法、装置、设备及存储介质
CN119621606B (zh) * 2024-11-13 2025-09-30 深圳市德明利技术股份有限公司 数据处理方法、装置及电子设备

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