WO2014188643A1 - Système d'ordonnancement, procédé d'ordonnancement et support d'enregistrement - Google Patents

Système d'ordonnancement, procédé d'ordonnancement et support d'enregistrement Download PDF

Info

Publication number
WO2014188643A1
WO2014188643A1 PCT/JP2014/001558 JP2014001558W WO2014188643A1 WO 2014188643 A1 WO2014188643 A1 WO 2014188643A1 JP 2014001558 W JP2014001558 W JP 2014001558W WO 2014188643 A1 WO2014188643 A1 WO 2014188643A1
Authority
WO
WIPO (PCT)
Prior art keywords
communication
task
instruction
resource
accelerator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2014/001558
Other languages
English (en)
Japanese (ja)
Inventor
孝道 宮本
岳生 細見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2013109843A external-priority patent/JP2014078215A/ja
Application filed by NEC Corp filed Critical NEC Corp
Priority to US14/787,830 priority Critical patent/US20160077882A1/en
Publication of WO2014188643A1 publication Critical patent/WO2014188643A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/5014—Reservation

Definitions

  • the system 54 includes a server 40 having a processor 41, a processor 42, a processor 43, a processor 44, and the like, a task scheduler 45, and a server resource management unit 46.
  • the task scheduler 45 receives a task to be executed as an input.
  • the task scheduler 45 refers to the number of processors necessary for executing the received task and the usage status of the plurality of processors (processors 41 to 44) held by the server resource management unit 46. Allocate a processor necessary for execution.
  • the task scheduler 45 updates information held by the server resource management unit 46 and inputs tasks to the server 40.
  • the task scheduler 45 detects that the server 40 has completed the execution of the task, the task scheduler 45 updates information held by the server resource management unit 46, and then releases a processor reserved for processing the task.
  • the task scheduler 45 uses the processors (processors 41 to 44) included in the server 40 for processing a plurality of tasks by performing the above-described operation. For this reason, the processing performance in the server 40 is improved.
  • FIG. 19 is a block diagram showing a configuration of a task scheduler for a system having a many-core accelerator related to the present invention.
  • the system 55 includes a task scheduler 52, a server resource management unit 53, and a server 47.
  • FIG. 20 shows processing when the server having the many-core accelerator shown in FIG. 18 adopts the task schedule method as described above.
  • FIG. 20 is a flowchart (sequence diagram) showing the flow of processing in the task scheduler related to the present invention.
  • the task scheduler 52 receives a task to be executed as an input, and refers to resource information related to the host processor 48 and the many-core accelerator 49 necessary for executing the task.
  • the task scheduler 52 secures resources necessary for processing the task by referring to the usage status of the resources managed by the server resource management unit 53 in the resource information (step S40).
  • the task scheduler 52 inputs the task to the server 47 by designating the secured resource (step S41).
  • the task scheduler 52 detects that the server 47 has completed the processing of the task, the task scheduler 52 then transmits the fact that the completion has been detected to the server resource management unit 53 and releases resources reserved for processing the task. (Step S42).
  • FIG. 21 is a flowchart showing the flow of processing in a system having a many-core accelerator related to the present invention.
  • the program execution control method disclosed in Patent Document 1 is a method for performing power saving control in a system having different types of processors. That is, the execution control method is a control method that improves performance. According to the execution control method, the clock frequency is changed so that the tasks divided by the processors are completed simultaneously.
  • Patent Document 2 reduces the overhead required for saving / restoring according to the progress state of the interrupted process when the process is interrupted in the middle of the data process and another process is given priority.
  • Patent Document 3 further increases the processing efficiency related to task switching by performing processing according to priority by software executed on a processor and hardware dedicated to specific processing.
  • the task scheduler 52 manages the resources in the many-core accelerator 49 when the tasks are submitted, thereby allocating the tasks to the resources, and then releases the allocated resources when completing the tasks.
  • the task scheduler 52 secures the resources of the many-core accelerator 49 when a task is submitted, and then keeps securing the resources until the task is completed. For this reason, the task scheduler 52 continues to secure the resource while the host processor 48 executes the task processing in step S43 or step S47. Alternatively, the task scheduler 52 continues to secure the resource while the host processor 48 transmits data between the main memory 50 and the accelerator memory 51 in step S44, step S46, and the like.
  • the task scheduler 52 secures the maximum resources for processing the series of tasks when starting the task. For this reason, when a specific task that uses only part of the resource is processed in a series of tasks, there is a resource that is not processed in step S45. As described above, when processing a series of tasks, a problem in which there is a resource that does not perform a specific process is represented as a resource non-use problem.
  • the task scheduler 52 that employs the processing method as described above cannot avoid the resource unavailability problem. For this reason, the many-core accelerator 49 has its processing performance lowered or fails to process the task.
  • a main object of the present invention is to provide a schedule system or the like that more efficiently exhibits the processing performance of resources.
  • the schedule system according to the present invention has the following configuration.
  • the scheduling method includes: A many-core accelerator as a resource, an accelerator memory accessed by the many-core accelerator, a processor controlling the resource, a memory accessed by the processor, and a first capable of transmitting and receiving data between the many-core accelerator and the processor
  • the first communication includes a second communication path that is included in a task that is processed by a computer having a communication path, and that is capable of transmitting and receiving first data processed by the task between the memory and the accelerator memory.
  • the second communication path is secured as a second communication resource in response to a fifth instruction secured from the path, and the second communication resource is transmitted / received via the second communication resource in accordance with the first instruction to secure the resource.
  • a specific resource for processing the task is determined based on one data. To.
  • this object is also realized by such a schedule program and a computer-readable recording medium for recording the program.
  • the processing performance of resources can be exhibited more efficiently.
  • FIG. 20 is a sequence diagram illustrating a flow of processing executed by a schedule system when a scheduler secures a storage area in an accelerator memory in the eighth embodiment.
  • FIG. 1 is a block diagram showing a configuration of a schedule system 1 according to the first embodiment of the present invention.
  • FIG. 2 is a sequence diagram showing a flow of processing in the schedule system 1 according to the first embodiment.
  • the system 38 includes a server 3 (also referred to as “computer”, “calculation processing device”, and “information processing device”) that performs processing for a task 6 that is a series of processing performed by a computer, 1 has a schedule system 1 according to one embodiment.
  • the schedule system 1 has a scheduler 2.
  • the server 3 includes a host processor 4 (hereinafter also simply referred to as “processor”) and a many-core accelerator 5.
  • the host processor 4 performs processing such as control regarding the many-core accelerator 5.
  • the host processor 4 starts processing of task 6.
  • the host processor 4 reads from the task 6 an instruction to secure a resource (a many-core accelerator 5) (also referred to as an instruction; hereinafter, an instruction to secure a resource is also referred to as a “first instruction”).
  • the host processor 4 transmits a command for securing resources to the schedule system 1 in accordance with the read first instruction (step S1).
  • the scheduler 2 confirms whether or not resources can be secured for the task 6 (hereinafter abbreviated as “resource securing”) in response to receiving the instruction (step S2). .
  • resource securing determines that the resource can be secured (YES in step S2)
  • the scheduler 2 secures the resource (step S3).
  • the scheduler 2 confirms again whether the resource can be secured (step S2).
  • the many-core accelerator 5 executes a task when the scheduler 2 determines that the resource can be secured (YES in step S2) (step S4).
  • step S2 When it is determined that the resource cannot be secured (NO in step S2), the scheduler 2 waits for the resource to be released by performing the above-described processing. Next, the scheduler 2 releases the secured resources (step S5).
  • the schedule system 1 can be realized as one function in the operating system, for example.
  • the schedule system 1 can perform the above-described processing by transmitting and receiving parameters related to resources with the operating system.
  • Patent Literature 1 to Patent Literature 3 secure the maximum resources for processing a series of tasks in a period from the start of processing a task to the completion of processing the task. Keep doing. For this reason, when a series of task processing uses only some resources, some resources are not processed.
  • the schedule system 1 secures resources in response to a request from a task, and then the secured resources perform processing. Thereafter, when the host processor 4 commands the release of the resource, the schedule system 1 releases the resource. Even when the server 3 processes a series of tasks, the scheduling system 1 can allocate resources for processing each task according to the task processing. For this reason, according to the schedule system 1 which concerns on 1st Embodiment, even if it is a case where a series of tasks are processed, the situation where only some resources are processed can be reduced.
  • the processing performance of the resource can be exhibited more efficiently.
  • FIG. 3 is a block diagram showing the configuration of the schedule system 7 according to the second embodiment of the present invention.
  • FIG. 4 is a sequence diagram showing a flow of processing in the schedule system 7 according to the second embodiment.
  • the system 39 includes a schedule system 7 and a server 3. Further, the schedule system 7 includes a scheduler 8 and a management unit 9.
  • the management unit 9 manages the usage status related to the resources of the many-core accelerator 5.
  • the scheduler 8 receives a request to secure resources (step S1), it reads the management unit 9 (step S6).
  • the scheduler 8 determines whether or not resources can be allocated based on the read information (step S2).
  • the scheduler 8 can determine whether or not resources can be allocated without referring to the outside. For this reason, according to the schedule system 7 which concerns on 2nd Embodiment, a resource can be managed efficiently. Furthermore, since the second embodiment includes a configuration similar to that of the first embodiment, the second embodiment can enjoy the same effects as those of the first embodiment.
  • the processing performance of the resource can be exhibited more efficiently.
  • FIG. 5 is a block diagram showing a configuration of the schedule system 10 according to the third exemplary embodiment of the present invention.
  • FIG. 6 is a sequence diagram illustrating a processing flow in the schedule system 10 according to the third embodiment.
  • the schedule system 10 includes a scheduler 11.
  • the system 56 performs processing related to the task 12 having the first part and the second part in the server 3.
  • the host processor 4 executes the first part of the task 12 that is processed by the host processor 4 (step S7). Next, the host processor 4 transmits a command for securing resources to the scheduler 11 in response to the first instruction (step S8). Next, when the scheduler 11 determines that the resource can be secured (YES in Step S9), the scheduler 11 secures the resource (Step S10). If the scheduler 11 determines that the resource cannot be secured (NO in step S9), the scheduler 11 again determines whether the resource can be secured (step S9).
  • the resource secured by the scheduler 11 executes the second part processed by the resource (step S11).
  • the host processor 4 instructs the scheduler 11 to release the resource in response to reading an instruction for releasing the resource secured by the scheduler 11 (hereinafter, this instruction is referred to as “second instruction”).
  • this instruction is referred to as “second instruction”.
  • the scheduler 11 releases the secured resources (step S13).
  • the first instruction has information on the number of processors, for example.
  • the scheduler 11 determines the amount of resources according to the number of processors described above, but the amount of resources does not necessarily have to be the same as the above-described numerical values. Further, the scheduler 11 may transmit information on the secured resource.
  • the information on the reserved resource may include information on the number of reserved processors or a list of available processor numbers.
  • the task 12 has a first part processed by the host processor 4, a second part, and a first instruction for securing a resource for executing the second part. For this reason, the scheduler 11 secures necessary resources before the processing of the second portion, and releases the resources after the secured resources complete the processing of the second portion. That is, the schedule system 10 according to the third embodiment makes it possible to manage resources more finely than the systems disclosed in Patent Documents 1 to 3.
  • the processing performance of the resource can be exhibited more efficiently.
  • the third embodiment is based on the first embodiment, but may be based on the second embodiment. Even in that case, the third embodiment can enjoy the same effects as those of the second embodiment.
  • FIG. 7 is a block diagram showing a configuration of the schedule system 13 according to the fourth exemplary embodiment of the present invention.
  • FIG. 8 is a sequence diagram showing the flow of processing in the schedule system 13 according to the fourth embodiment.
  • the system 57 includes a server 16 that processes the task 15 and a schedule system 13 that manages resources in the server 16.
  • the server 16 includes a host processor 18, a main memory 19 that stores data processed by the host processor 18, a many-core accelerator 17, and an accelerator memory 20 that stores data processed by the many-core accelerator 17.
  • the schedule system 13 has a scheduler 14.
  • the task 15 includes a third part for transmitting data from the main memory 19 to the accelerator memory 20, and the accelerator memory 20 to the main memory 19. And a fourth portion for transmitting data.
  • the host processor 18 After executing the first part, the host processor 18 transmits a request for securing a specific resource to the schedule system 13 in accordance with the first instruction (step S14).
  • the scheduler 14 secures a specific resource in response to receiving the request (step S15).
  • Step S15 collectively represents a series of processes in Step S2 and Step S3 in FIG. 2 or a series of processes in Step S2, Step S3, and Step S6 in FIG.
  • the host processor 18 transmits data to be processed by the many-core accelerator 17 from the main memory 19 to the accelerator memory 20 (step S16).
  • step S17 the specific resource secured by the scheduler 14 executes the second part.
  • the host processor 18 transmits the data processed by the specific resource from the accelerator memory 20 to the main memory 19 (step S18).
  • step S19 the host processor 18 transmits a request for releasing a specific resource to the schedule system 13 (step S19).
  • the scheduler 14 releases a specific resource in response to receiving the request (step S20).
  • the scheduler 14 can also secure the accelerator memory 20 in addition to the processing device in the many-core accelerator 17.
  • the specific many-core accelerator 17 refers to the specific accelerator memory 20.
  • FIG. 9 is a sequence diagram showing the flow of the second process in the schedule system according to the fourth embodiment.
  • the host processor 18 After executing the first part, the host processor 18 transmits a request for securing a specific accelerator memory 20 to the schedule system 13 in accordance with the first instruction (step S30). The scheduler 14 secures a specific accelerator memory 20 in response to receiving the request (step S31). Next, the host processor 18 transmits data to be processed by the many-core accelerator 17 from the main memory 19 to the specific accelerator memory 20 (step S16).
  • Step S15 collectively represents a series of processes in Step S2 and Step S3 in FIG. 2 or a series of processes in Step S2, Step S3, and Step S6 in FIG.
  • step S17 the specific resource secured by the scheduler 14 executes the second part.
  • the host processor 18 transmits a request for releasing a specific resource to the schedule system 13 (step S19).
  • step S19 the scheduler 14 releases a specific resource in response to receiving the request (step S20).
  • step S18 the host processor 18 transmits the data processed by the specific resource from the accelerator memory 20 to the main memory 19 (step S18).
  • the host processor 18 transmits a request to release the specific accelerator memory 20 to the scheduler 14 (step S32).
  • the scheduler 14 releases the specific accelerator memory 20 in response to receiving the request (step S33).
  • the scheduling system 13 can effectively manage the resources processed by the many-core accelerator 17 and the resources or the accelerator memory 20 in the system 57 as well.
  • the processing performance of the resource can be exhibited more efficiently.
  • the fourth embodiment is based on the first embodiment, but may be based on the second embodiment or the third embodiment. Even in that case, the fourth embodiment can enjoy the same effect.
  • FIG. 10 is a block diagram showing the configuration of the schedule system 21 according to the fifth embodiment of the present invention.
  • FIG. 11 is a sequence diagram showing a flow of processing in the schedule system 21 according to the fifth embodiment.
  • the system 58 includes a schedule system 21 and a server 3 that processes the task 23.
  • the schedule system 21 has a scheduler 22.
  • the task 23 includes a fifth part to be processed by the host processor 4 instead of the many-core accelerator 5 when the scheduler 22 cannot secure a specific resource.
  • the process in the fifth part is the same as the process in the second part. That is, the result of the host processor 4 executing the fifth part matches the result of the specific resource executing the second part.
  • the host processor 4 executes the fifth part when determining that the scheduler 22 cannot allocate resources (NO in step S9) (step S21).
  • the scheduler 22 determines that the scheduler 22 can allocate resources (YES in step S9), the scheduler 22 secures specific resources (step S10).
  • the processing performance of the resource can be exhibited more efficiently.
  • FIG. 12 is a block diagram showing the configuration of the schedule system 24 according to the sixth embodiment of the present invention.
  • FIG. 13 is a sequence diagram showing the flow of processing in the schedule system 24 according to the sixth embodiment.
  • the system 59 includes a schedule system 24, a second task scheduler 26 that controls input of the task 6 to the server 3, and the server 3.
  • the schedule system 24 has a scheduler 25.
  • the second task scheduler 26 transmits information related to the task such as the number of tasks in the task 6 to the schedule system 24 (step S23).
  • the scheduler 25 calculates the amount of resources according to the received information (step S24). For example, the scheduler 25 uses the number of logical processors that the many-core accelerator 5 has divided by the number of tasks that the second task scheduler 26 inputs to the server 3 as the amount of resources, or the value calculated as described above. 2 times the resource amount.
  • the method by which the schedule system 24 calculates the amount of resources is not limited to the above-described example.
  • the schedule system 24 receives from the second task scheduler 26 information that can be used for control to allocate resources. Thereby, the scheduling system 24 can further increase the efficiency of scheduling, and can give an appropriate load to the many-core accelerator 5.
  • the processing performance of the resource can be more efficiently exhibited.
  • FIG. 14 is a block diagram showing the configuration of the schedule system 27 according to the seventh embodiment of the present invention.
  • FIG. 15 is a sequence diagram showing the flow of processing in the schedule system 27 according to the seventh embodiment.
  • the system 60 includes a schedule system 27, a second task scheduler 30, and a server 3 that processes the task 6.
  • the schedule system 27 includes a scheduler 28 and a management unit 29.
  • the scheduler 28 reads the resource load status in the many-core accelerator 5 from the management unit 29 (step S25). Next, the scheduler 28 compares the predetermined second threshold value with a load value representing the load. When the scheduler 28 determines that the load value is smaller than the predetermined second threshold value, that is, determines that the load state is low (determined YES in step S26), the scheduler 28 is configured to input more tasks. A signal is transmitted to the second task scheduler 30 (step S27). The scheduler 28 compares a predetermined first threshold value with a load value representing the load.
  • the scheduler 28 determines that the load value is greater than a predetermined first threshold value, that is, determines that the load status is high (determined NO in step S26)
  • the scheduler 28 inputs a smaller number of tasks.
  • a signal is transmitted to the two-task scheduler 30 (step S28).
  • the second task scheduler 30 adjusts the task amount according to the signal (step S29).
  • an appropriate load can be applied to the many-core accelerator 5. it can.
  • the processing performance of the resource can be exhibited more efficiently.
  • FIG. 22 is a block diagram showing the configuration of the schedule system 114 according to the eighth embodiment of the present invention.
  • FIG. 23 is a sequence diagram showing the flow of processing in the schedule system 114 according to the eighth embodiment.
  • the system 117 includes a server 100 and a schedule system 114.
  • the server 100 includes a host processor 101, a main memory 103, a many-core accelerator 102, an accelerator memory 104, and a communication path 105 that connects the host processor 101 and the many-core accelerator 102.
  • the host processor 101 and the many-core accelerator 102 communicate (referred to as access and transmission / reception) data to be referred to via the communication path 105.
  • the schedule system 114 further includes a communication channel scheduler 116 that secures communication resources of the communication channel 105.
  • the host processor 101 makes a first instruction 201 for securing resources in the many-core accelerator 102 to the schedule system 114 (step S14).
  • the scheduling system 114 secures specific resources in the many-core accelerator 102 according to the first instruction 201 (step S15).
  • the host processor 101 receives the fifth instruction 110 for the task 106 to secure the communication path 105, and secures the communication resources of the communication path 105 in the communication path scheduler 116 according to the received fifth instruction 110. (Step S101).
  • the communication path scheduler 116 receives from the host processor 101 a command for securing communication resources capable of communicating the communication amount according to the fifth instruction 110.
  • the communication channel scheduler 116 measures the communication amount on the communication channel 105 until the communication channel 105 can communicate the communication amount according to the fifth instruction 110. Thereafter, when the communication path 105 can communicate the communication amount according to the fifth instruction 110, the communication path scheduler 116 secures communication resources according to the fifth instruction 110 from the communication path 105 (step S102).
  • the host processor 101 transmits the data accessed by the many-core accelerator 102 from the main memory 103 to the accelerator memory 104 via the communication resource secured by the communication path scheduler 116 (step S16).
  • the host processor 101 transmits data from the main memory 103 to the accelerator memory 104.
  • the host processor 101 transmits a request for releasing the reserved communication resource to the communication path scheduler 116 (step S103). .
  • the communication path scheduler 116 receives a request to release the reserved communication resource, and releases the reserved communication resource in response to the received request (step S104).
  • step S17 the specific resource secured by the scheduler 115 executes the second part 107 in the task 106 by accessing the data stored in the accelerator memory 104.
  • the host processor 101 requests the communication path scheduler 116 to secure a communication resource capable of communicating the communication amount according to the seventh instruction 112 in response to the seventh instruction 112 that secures the communication resource of the communication path 105. Is transmitted (step S105).
  • the communication path scheduler 116 receives a command for securing communication resources from the host processor 101. Next, the communication path scheduler 116 measures the communication volume on the communication path 105 until a communication resource capable of communicating the communication volume indicated by the seventh instruction 112 can be secured. Thereafter, when the communication path 105 can communicate the communication amount according to the seventh instruction 112, the communication path scheduler 116 secures communication resources according to the seventh instruction 112 from the communication path 105 (step S106).
  • the host processor 101 transmits data or the like processed by a specific resource from the accelerator memory 104 to the main memory 103 via the communication resource secured by the communication path scheduler 116 (step S18).
  • the host processor 101 receives the eighth instruction 113 for releasing the secured communication resource from the task 106, and in response to the received eighth instruction 113, instructs the communication path scheduler 116 to release the secured communication resource. Transmit (step S107).
  • the communication path scheduler 116 receives the command from the host processor 101, and releases the reserved communication resources according to the received command (step S108).
  • the host processor 101 transmits an instruction to release a specific resource to the schedule system 114 in accordance with the second instruction 202 described above (step S19).
  • the schedule system 114 receives the command from the host processor 101, and releases the reserved specific resource in accordance with the received command (step S20).
  • the fifth instruction 110, the sixth instruction 111, the seventh instruction 112, and the eighth instruction 113 are instructions for securing communication resources or releasing communication resources. May be included.
  • the fifth instruction to the eighth instruction may include information for identifying the task 106 that gives the instruction or the time when the instruction is received.
  • the fifth instruction to the eighth instruction may include the size of data transmitted / received between the main memory 103 and the accelerator memory 104, information on the data structure in the main memory 103, or the like.
  • the fifth instruction 110 and the seventh instruction 112 are different instructions, but the same instruction may be used.
  • the sixth instruction 111 and the eighth instruction 113 are different instructions, they may be the same instruction.
  • the task 106 performs the fifth instruction 110 instead of performing the seventh instruction 112 and performs the eighth instruction 113 instead of performing the sixth instruction 111.
  • the communication path scheduler 116 secures processing related to the fifth instruction 110, that is, communication resources, according to the seventh instruction 112. Similarly, in response to the eighth instruction 113, the communication channel scheduler 116 releases processing related to the sixth instruction 111, that is, communication resources.
  • the third portion 108 may include a process for securing a storage area in the accelerator memory 104.
  • the fourth portion 109 may include a process for releasing a storage area in the accelerator memory 104.
  • the scheduler 115 may secure the storage area in the accelerator memory 104.
  • the schedule system 114 performs the process shown in FIG. FIG. 24 is a sequence diagram showing a flow of processing executed by the schedule system 114 when the scheduler secures a storage area in the accelerator memory in the eighth embodiment.
  • the host processor 101 transmits a command for securing a storage area having a certain size in the accelerator memory 104 to the schedule system 114 (step S30).
  • the scheduler 115 receives the command from the host processor 101, and secures a storage area having a certain size in the accelerator memory 104 in accordance with the received command (step S31).
  • the host processor 101 receives the fifth instruction 110 for the task 106 to secure the communication path 105, and secures the communication resources of the communication path 105 in the communication path scheduler 116 according to the received fifth instruction 110.
  • a command to transmit is transmitted (step S101).
  • the communication path scheduler 116 receives from the host processor 101 a command for securing communication resources according to the fifth instruction 110.
  • the communication channel scheduler 116 transmits and receives the communication amount in the communication channel 105 until the communication channel 105 can communicate the communication amount according to the fifth instruction 110 (hereinafter, “communication band” is used as a synonymous word). Measure. Thereafter, when the communication path 105 can communicate the communication amount according to the fifth instruction 110, the communication path scheduler 116 secures communication resources according to the fifth instruction 110 (step S102).
  • the host processor 101 transmits data to be processed by the many-core accelerator 102 from the main memory 103 to a specific storage area in the accelerator memory 104 via the communication resource secured by the communication path scheduler 116 (step S16).
  • the host processor 101 transmits an instruction for releasing the reserved communication resource to the communication path scheduler 116 (step S103).
  • the communication path scheduler 116 receives a command for releasing the reserved communication resource, and releases the reserved communication resource according to the received command (step S104).
  • a command for securing resources is transmitted to the schedule system 114 (step S14).
  • the scheduler 14 secures specific resources in the many-core accelerator 102 in response to receiving the command (step S15).
  • the specific resource secured by the scheduler executes the second part 107 in the task 106 by processing the data transmitted to the accelerator memory 104 (step S17).
  • the host processor 101 commands the schedule system 114 to release the specific resource in response to the second instruction 202 to release the reserved resource (Ste S19).
  • the scheduler 14 releases a specific resource according to the command (step S20).
  • the host processor 101 secures a communication resource corresponding to the seventh instruction 112 in the communication path scheduler 116 in response to the seventh instruction 112 that secures the communication resource of the communication path 105 in the task 106.
  • a command is transmitted (step S105).
  • the communication path scheduler 116 receives a command for securing communication resources from the host processor 101. Next, the communication channel scheduler 116 measures the communication amount transmitted / received in the communication channel 105 until the communication channel 105 can communicate the communication amount according to the seventh instruction 112. After that, the communication path scheduler 116 secures communication resources according to the seventh instruction 112 when the communication path 105 can communicate the communication amount according to the seventh instruction 112 (step S106).
  • the host processor 101 receives the eighth instruction 113 for releasing the reserved communication resource from the task 106, and instructs the communication path scheduler 116 to release the reserved communication resource in accordance with the received eighth instruction 113. (Step S107).
  • the communication path scheduler 116 receives the command from the host processor 101, and releases the reserved communication resources according to the received command (step S108).
  • the communication channel scheduler 116 secures communication resources in accordance with instructions in the task 106.
  • the host processor 101 and the many-core accelerator 102 transmit and receive data between the main memory 103 and the accelerator memory 104 via the communication resource. For this reason, according to the present embodiment, the possibility of communication delay in the communication path 105 is reduced. Further, when the communication channel scheduler 116 cannot secure an amount of communication resources that can handle the instruction in the task 106, transmission / reception of data necessary to process the task 106 is temporarily stopped in advance. As a result, according to the present embodiment, there is a low possibility that transmission / reception of data in tasks other than the task is hindered.
  • the scheduler 115 includes the communication channel scheduler 116, but the scheduler 115 may realize the function of the communication channel scheduler 116.
  • FIG. 25 is a block diagram showing a configuration of a schedule system 251 according to the ninth exemplary embodiment of the present invention.
  • FIG. 26 is a flowchart illustrating a process flow when the fifth instruction 110 or the seventh instruction 112 is received in the schedule system 251 according to the ninth embodiment.
  • FIG. 27 is a flowchart illustrating a process flow when the sixth instruction 111 or the eighth instruction 113 is received in the schedule system 251 according to the ninth embodiment.
  • the system 255 includes a server 100 and a schedule system 251.
  • the schedule system 251 includes a scheduler 115 and a communication path scheduler 252. Further, the communication path scheduler 252 includes a communication information unit 254 and a communication control unit 253.
  • the host processor 101 transmits a command for securing communication resources to the communication path scheduler 252 in response to the fifth instruction 110 in step S101 or the seventh instruction 112 in step S105.
  • the communication path scheduler 252 receives a command for securing communication resources from the host processor 101 (step S201).
  • the communication control unit 253 in the communication path scheduler 252 determines whether or not the communication path 105 has a communication path in an idle state (or also expressed as “sleeping”, “idle”, “standby”, etc.). Check out.
  • the “idle state” represents a state in which a target device is not assigned to a task or the like.
  • the communication control unit 253 checks whether or not the communication path 105 has an idle communication path based on the number of communication path uses that represents the total number of communication paths used by the task. In this case, the communication control unit 253 adds 1 to the number of used communication paths in accordance with the received command, and compares the calculated value with the number of communication paths that the communication path 105 originally has (step S202).
  • the communication path scheduler 252 secures communication resources from the idle communication path in accordance with the received command (step S204).
  • the communication control unit 253 stores the task identifier in the communication information unit 254 when the calculated number of used communication channels is larger than the number of communication channels included in the communication channel 105 (determined as NO in step S202). (Step S205). That is, the communication control unit 253 saves, in the communication information unit 254, the task identifier associated with the task 106 that has performed the fifth instruction 110 or the seventh instruction 112 for starting the received instruction, as shown in FIG. (Step S205).
  • the task identifier is an identifier that can uniquely identify the task.
  • FIG. 28 is a diagram conceptually illustrating an example of a task identifier that can be stored in the communication information unit 254.
  • the communication information unit 254 stores a task identifier “1”, a task identifier “3”, a task identifier “4”, and a task identifier “2”.
  • the communication path scheduler 252 allocates communication resources in the process in step S205. Not secured.
  • the host processor 101 receives the sixth instruction 111 or the eighth instruction 113 from the task 106.
  • the host processor 101 transmits an instruction to release the reserved communication resources to the communication path scheduler 252 in accordance with the received sixth instruction 111 or eighth instruction 113.
  • the communication path scheduler 252 receives a command for releasing the secured communication resource from the host processor 101 (step S211).
  • the communication control unit 253 in the communication path scheduler 252 determines whether or not the communication information unit 254 stores a task identifier (step S212).
  • the communication control unit 253 reads a specific task identifier from the communication information unit 254 (step S213).
  • the communication control unit 253 controls communication with respect to the task with the read task identifier, as shown in steps S202 to S205 in FIG. 26 (step S214).
  • the communication path scheduler 252 subtracts 1 from the number of used communication paths and sets the calculated number of used communication paths (step S215). At the same time, the communication path scheduler 252 releases the reserved communication resource in response to the command to release the communication resource (step S216). The communication path scheduler 252 may process step S216 before step S215.
  • the function implemented using the number of communication channels used in the above-described example can be implemented with the same value such as the number of communication channels in an idle state.
  • the communication information unit 254 may have a queue structure capable of storing a task identifier. That is, the communication information unit 254 may have a data structure in which task identifiers are stored in the order of reception times and the stored task identifiers can be output in the order of reception times.
  • the communication control unit 253 performs the processes shown in step S212 and subsequent steps in the order of the time when the command for securing the communication resources is received.
  • the ninth embodiment includes the same configuration as that of the eighth embodiment, the ninth embodiment can enjoy the same effects as those of the eighth embodiment.
  • the schedule system 251 according to the ninth embodiment the processing performance of resources can be more efficiently exhibited.
  • the communication channel scheduler 252 allocates communication resources to the task 106 that cannot allocate communication resources to the instruction to secure the communication channel 105 in accordance with processing for releasing communication resources for other tasks. For this reason, according to this embodiment, it becomes possible to allocate a communication resource more efficiently. As a result, it is possible to access the accelerator memory 104 and the main memory 103 more efficiently. That is, according to the schedule system 251 according to the ninth embodiment, it is possible to further reduce the deterioration of the processing performance.
  • the communication channel scheduler 252 manages communication resources in the communication channel 105 using the number of communication channels used, but the communication channel measurement function that measures the communication band used in the communication channel 105 performs communication. Resources may be managed.
  • the communication channel scheduler 252 compares the communication bandwidth measured by the communication channel measurement function with the communication bandwidth available on the communication channel 105. If the measured communication bandwidth is smaller than the available communication bandwidth, the communication channel scheduler 252 secures communication resources in response to a request to secure the communication channel 105 (step S203 in FIG. 26). On the other hand, when the measured communication bandwidth is larger than the available communication bandwidth, the communication channel scheduler 252 stores the task identifier of the task 106 that requested the communication channel 105 in the communication information unit 254 (step S205 in FIG. 26). .
  • FIG. 29 is a block diagram showing a configuration of a schedule system 301 according to the tenth embodiment of the present invention.
  • FIG. 30 is a flowchart showing the flow of processing in the priority order setting unit 303 according to the tenth embodiment.
  • FIG. 31 is a flowchart showing a flow of processing in the communication control unit 305 according to the tenth embodiment.
  • the system 306 includes a server 100 and a schedule system 301.
  • the schedule system 301 includes a scheduler 115 and a communication path scheduler 302.
  • the communication path scheduler 302 includes a communication control unit 305, a communication information unit 304, and a priority order setting unit 303.
  • first data indicates that the task with the task identifier “1” is 2048 kilobytes (hereinafter referred to as “KB”) according to the fifth instruction 110 at time “10”. Represents a request for communication resources to transmit / receive data.
  • second data is that the task with the task identifier “3” transmits / receives 100 KB data in accordance with the seventh instruction 112 at time “20”. Represents a request for communication resources.
  • the first data and the second data are associated with the priority “1” and the priority “2”, respectively. Since the priority order of the first data is lower than the priority order of the second data, the communication control unit 305 processes the first data before the second data.
  • the priority order setting unit 303 determines whether or not the data stored in the communication information unit 304 is updated (step S261). For example, when the communication control unit 305 updates the value in the communication information unit 304 in response to the fifth instruction 110 or the seventh instruction 112, the priority order setting unit 303 updates the data stored in the communication information unit 304. It is determined that
  • the communication control unit 305 determines that the data stored in the communication information unit 304 has been updated (YES in step S261), the communication control unit 305 assigns the priority to the task 106 according to the type of instruction in the task 106, and the like.
  • the rank is calculated (step S262). In this case, the communication control unit 305 calculates the priority according to a predetermined priority calculation method. Further, when the communication control unit 305 determines that the data stored in the communication information unit 304 has not been updated (NO in step S261), the communication control unit 305 does not perform the above-described processing.
  • a predetermined priority order calculation method there is a method in which a higher priority order is assigned to a task whose instruction type is “5” than a task whose instruction type is “7”.
  • the communication control unit 305 processes the task with the instruction type “5” in preference to the instruction type “7”.
  • the instruction type “7” represents the seventh instruction.
  • the instruction type “5” represents the fifth instruction.
  • the communication control unit 305 receives an instruction to release the reserved communication resource from the host processor 101 (step S211).
  • the communication control unit 305 reads whether or not the communication information unit 304 stores a task identifier (step S212).
  • the communication control unit 305 releases the reserved communication resource (step S216).
  • the communication control unit 305 calculates a value obtained by subtracting 1 from the number of communication paths used.
  • the usage number may be updated with the calculated value (step S215).
  • the communication control unit 305 determines a task identifier associated with a higher priority from the communication information unit 304. Read (step S313). For example, the communication control unit 305 may read the task identifier having the highest priority in the communication information unit 304. Next, the communication control unit 305 executes processing such as securing communication resources as shown in FIG. 26 for the task associated with the read task identifier (step S214). Thereafter, the communication control unit 305 releases the communication resource to be released according to the received command (step S216).
  • the communication control unit 305 may calculate a value obtained by subtracting 1 from the number of used communication paths, and update the value using the calculated number of used communication paths (Step S215).
  • the predetermined priority order calculation method is, for example, a calculation method as shown in FIGS. FIG. 33 to FIG. 36 are flowcharts showing an example of the processing flow in the predetermined priority order calculation method according to the tenth embodiment.
  • the task identifier stored in the communication information unit 304 has a higher priority than the task of the instruction type “7” to the task of the instruction type “5” associated with the task identifier.
  • the rank is calculated (step S271).
  • the communication control unit 305 gives priority to the task requesting the communication resource according to the fifth instruction 110 from the task requesting the communication resource prior to the task requesting the communication resource according to the seventh instruction 112. Allocate communication resources.
  • the schedule system 301 allocates the processing of the second portion 107 to the many-core accelerator 102 after securing communication resources according to the fifth instruction 110.
  • the schedule system 301 secures communication resources according to the seventh instruction 112 after the many-core accelerator 102 finishes the processing of the second portion 107.
  • the scheduling system 301 processes the task 106 that commands the fifth instruction 110 in preference to the task 106 that commands the seventh instruction 112.
  • the many-core accelerator 102 can transmit / receive the data according to the second portion 107 at an early stage via the communication resource.
  • the processing efficiency is further increased compared to the ninth embodiment.
  • the communication resources are requested in ascending order when they are associated with the same instruction type.
  • This is a method for calculating a high priority. That is, the predetermined priority order calculation method is a method of calculating a higher priority order in the order of earlier time in the task 106 associated with the instruction type “5” (step S272). . Further, the predetermined priority order calculation method is a method of calculating a higher priority order in the order from the earliest time in the task 106 associated with the instruction type “7” (step S273). Note that step S273 may be processed before step S272.
  • the predetermined priority order calculation method shown in FIG. 34 a higher priority order is assigned in order from the earliest time when communication resources are requested. Thereby, in the predetermined priority order calculation method, in addition to the effects of the predetermined priority order calculation method shown in FIG. 33, the average turnaround time required for processing the task can be further reduced. it can.
  • the predetermined priority order calculation method shown in FIG. 35 is a method of performing the subsequent processing when associated with the same time in addition to the predetermined priority order calculation method shown in FIG.
  • the predetermined priority order calculation method is a method for calculating a high priority order for the task 106 with a small size of data transmitted and received between the accelerator memory 104 and the main memory 103.
  • the predetermined priority order calculation method assigns a high priority order to the task 106 having the small data size in the task associated with the instruction type “5” and the same time (step S274). Further, the predetermined priority order calculation method assigns a higher priority order to a task having the smaller data size among the tasks associated with the instruction type “7” and the same time (step S275). Processing may be performed in the order of step S271, step S273, step S275, step S272, and step S274.
  • the time for which the task 106 waits for communication resource allocation can be shortened.
  • the scheduling system 301 assigns communication resources to the first task
  • the second task in the communication information unit 304 waits for the communication resources to be released.
  • the above-described waiting time is short.
  • the predetermined priority order calculation method in FIG. 36 is the following method. According to this method, for example, when there is a storage area in the accelerator memory 104 in an idle state (determined as YES in step S281), a priority is assigned (step S282). In this case, the predetermined priority order calculation method is a method of assigning a higher priority order to the task associated with the fifth instruction 110 than the task associated with the seventh instruction 112.
  • the predetermined priority order calculation method is a method of assigning a higher priority order to the task associated with the seventh instruction 112 than the task associated with the fifth instruction 110.
  • the schedule system 301 can allocate communication resources according to the fifth instruction 110.
  • the host processor 101 cannot transmit data necessary for processing in the second portion 107 to the accelerator memory 104.
  • the schedule system 301 creates a storage area in an idle state in the accelerator memory 104, and transmits necessary data to the storage area in the idle state. Thereby, the many-core accelerator 102 starts processing in the second portion 107.
  • the communication path scheduler 302 assigns a higher priority to the task 106 associated with the seventh instruction 112 when there is no storage area in the accelerator memory 104 in an idle state.
  • the communication path scheduler 302 first creates a storage area in an idle state in the accelerator memory 104.
  • the host processor 101 transmits reference data from the main memory 103 to the storage area in the idle state.
  • the many-core accelerator 102 performs processing in the second portion 107 based on the data.
  • the communication path scheduler 302 allocates communication resources according to the usage status of the accelerator memory 104. Therefore, the communication path scheduler 302 may allocate communication resources for transmitting the data to the task even though the accelerator memory 104 does not have a sufficient storage area for storing the data processed by the task. Reduce sexuality. That is, according to the communication path scheduler 302 according to the present embodiment, since the accelerator memory 104 cannot store the data processed by the task 106, it is possible to reduce the possibility that the processing in the many-core accelerator 102 stops.
  • the tenth embodiment includes the same configuration as that of the ninth embodiment, the tenth embodiment can enjoy the same effects as those of the ninth embodiment.
  • the schedule system 301 according to the tenth embodiment the processing performance of resources can be exhibited more efficiently.
  • FIG. 37 is a block diagram showing a configuration of a schedule system 3004 according to the eleventh embodiment of the present invention.
  • FIG. 38 is a sequence diagram showing the flow of processing in the schedule system 3004 according to the eleventh embodiment.
  • the system 3006 includes a server 100 and a schedule system 3004.
  • the schedule system 3004 has a scheduler 3005.
  • the scheduler 3005 controls the server 100 based on a task 3001 including a first instruction 3002 for securing the resources possessed by the many-core accelerator 102 and a fifth instruction 3003 for securing communication resources possessed by the communication path 105.
  • the host processor 101 transmits to the scheduler 3005 a request to secure communication resources capable of communicating the amount designated in the fifth instruction 3003 (step S3201).
  • the scheduler 3005 determines whether or not there is an idle communication resource in the communication path 105 (step S3202). If the scheduler 3005 determines that a communication resource capable of communicating the amount instructed by the fifth instruction from the communication path 105 can be allocated (YES in step S3202), the scheduler 3005 secures the communication resource (step S3202). S3203).
  • the host processor 101 reads data to be processed in the task 3001 from the main memory 103, and transmits the read data to the many-core accelerator 102 (step S3204).
  • the many-core accelerator 102 receives the data, and stores the received data in the accelerator memory 104 (step S3205).
  • the host processor 101 transmits a request for securing a resource for processing the task 3001 from the many-core accelerator 102 to the scheduler 3005 (step S3206).
  • the scheduler 3005 receives the request, and determines whether or not the many-core accelerator 102 can secure the resource according to the first instruction 3002 (step S3207). If the many-core accelerator 102 determines that the many-core accelerator 102 has an idle resource that can process the task 3001 (YES in step S3207), the scheduler 3005 secures a specific resource (step S3208). ).
  • the specific resource performs processing related to the task 3001 based on the received data in the accelerator memory 104 (step S3209).
  • the eleventh embodiment includes a configuration similar to that of the fourth embodiment, the eleventh embodiment can enjoy the same effects as those of the fourth embodiment. That is, according to the schedule system 3004 according to the eleventh embodiment, the processing performance of the resource can be more efficiently exhibited.
  • the schedule system 3004 secures a communication channel resource for transmitting the first data related to the task 3001 from the communication channel 105.
  • the scheduler 3005 secures communication resources
  • the host processor can store the first data in the main memory 103 in the accelerator memory 104 without delay.
  • the scheduler 3005 secures a specific resource, a situation in which the specific resource cannot perform the process related to the task 3001 due to the delay of the first data does not occur.
  • the non-volatile recording medium 35 can be read by a computer such as a compact disc (Compact Disc), a digital versatile disc (Digital Versatile Disc), a Blu-ray Disc (registered trademark), a universal serial bus memory (USB memory). ), Solid state drive (Solid State Drive), etc., and the program can be retained and carried even without power supply.
  • a computer such as a compact disc (Compact Disc), a digital versatile disc (Digital Versatile Disc), a Blu-ray Disc (registered trademark), a universal serial bus memory (USB memory). ), Solid state drive (Solid State Drive), etc.
  • the nonvolatile recording medium 35 is not limited to the above-described medium. Further, instead of the nonvolatile recording medium 35, the program may be carried via a communication network.
  • the CPU 32 copies a software program (computer program: hereinafter simply referred to as “program”) stored in the disk 34 to the memory 33 when executing it, and executes arithmetic processing.
  • the CPU 32 reads data necessary for program execution from the memory 33. When display is necessary, the CPU 32 displays the output result on the output device 37. When inputting a program from the outside, the CPU 32 reads the program from the input device 36.
  • the CPU 32 performs functions (processes) represented by the respective units shown in FIGS. 1, 3, 5, 7, 10, 10, 12, 14, 22, 25, 29, or 37 described above.
  • Schedule program FIG. 2, FIG. 4, FIG. 6, FIG. 8, FIG. 9, FIG. 9, FIG. 13, FIG. 15, FIG. 23, FIG. 24, FIG. 26, FIG. 27, FIG. 30, FIG. 33 to 36 and 38, the processing performed by the schedule system is interpreted and executed.
  • the CPU 32 sequentially performs the processes described in the above-described embodiments of the present invention.
  • the present invention can also be achieved by such a schedule program. Furthermore, it can be understood that the present invention can also be realized by a computer-readable recording medium on which such a schedule program is recorded.
  • a many-core accelerator as a resource an accelerator memory accessed by the many-core accelerator, a processor controlling the resource, a memory accessed by the processor, and a first capable of transmitting and receiving data between the many-core accelerator and the processor
  • the first communication includes a second communication path that is included in a task that is processed by a computer having a communication path, and that is capable of transmitting and receiving first data processed by the task between the memory and the accelerator memory.
  • the second communication path is secured as a second communication resource in response to a fifth instruction secured from the path, and the second communication resource is transmitted / received via the second communication resource in accordance with the first instruction to secure the resource.
  • a specific resource for processing the task is determined based on one data. Scheduling system with a scheduler that.
  • (Appendix 2) A first part of the task to be processed by the processor, the fifth instruction, and the first data transmitted from the memory to the accelerator memory via the second communication resource.
  • the scheduler secures the second communication resource according to the fifth instruction, releases the second communication resource according to the sixth instruction, and receives the third communication path according to the seventh instruction.
  • As a third communication resource and in response to the eighth instruction, has a channel scheduler that releases the third communication resource,
  • a resource for processing the task is secured as a specific resource
  • the processor transmits the first data from the memory to the accelerator memory via the second communication resource, and transmits the second data from the accelerator memory to the memory via the third communication resource.
  • Send data The schedule system according to claim 1, wherein the specific resource creates the second data by processing the task while accessing the first data according to the second part.
  • the task is associated with a task identifier that identifies the task;
  • the channel scheduler is Communication information means capable of storing the task identifier; If the fourth communication resource cannot be secured for the task that executes the fifth instruction or the seventh instruction, the task identifier associated with the task is stored in the communication information means, When a communication resource can be secured, a communication control process is performed to secure the communication resource from the first communication path in the idle state before the fourth communication resource, In response to the sixth instruction or the eighth instruction, the fourth communication resource is released, and then the task identifier is read from the communication information means, and the task associated with the read task identifier is The schedule system according to claim 3, further comprising: a communication control unit that performs communication control processing.
  • Priority order setting means for calculating a priority order for processing a task associated with a task identifier in the communication information means according to a predetermined priority order calculation method according to a type of instruction executed by the task;
  • the predetermined priority order calculation method is a method for calculating a higher priority order for a task whose instruction type is the fifth instruction than for a task whose instruction type is the seventh instruction. Schedule system as described in.
  • the predetermined priority order calculation method is a method for calculating a higher priority order for a task that first executes the fifth instruction in a task whose instruction type is the fifth instruction. system.
  • the predetermined priority order calculation method is a method of calculating a high priority order for a task with a small amount of data transmitted via the communication path in a task whose instruction type is the fifth instruction or the seventh instruction.
  • the schedule system according to appendix 5.
  • the instruction type is a task that is the fifth instruction.
  • the priority level is higher than the task whose type is the seventh instruction and it is determined that the storage area does not exist, the task whose instruction type is the seventh instruction has the instruction type
  • a many-core accelerator as a resource an accelerator memory accessed by the many-core accelerator, a processor controlling the resource, a memory accessed by the processor, and a first capable of transmitting and receiving data between the many-core accelerator and the processor
  • the first communication includes a second communication path that is included in a task that is processed by a computer having a communication path, and that is capable of transmitting and receiving first data processed by the task between the memory and the accelerator memory.
  • the second communication path is secured as a second communication resource in response to a fifth instruction secured from the path, and the second communication resource is transmitted / received via the second communication resource in accordance with the first instruction to secure the resource.
  • a specific resource for processing the task is determined based on one data. Schedule how to.
  • a many-core accelerator as a resource an accelerator memory accessed by the many-core accelerator, a processor controlling the resource, a memory accessed by the processor, and a first capable of transmitting and receiving data between the many-core accelerator and the processor
  • the first communication includes a second communication path that is included in a task that is processed by a computer having a communication path, and that is capable of transmitting and receiving first data processed by the task between the memory and the accelerator memory.
  • the second communication path is secured as a second communication resource in response to a fifth instruction secured from the path, and the second communication resource is transmitted / received via the second communication resource in accordance with the first instruction to secure the resource.
  • a specific resource for processing the task is determined based on one data. Recording medium storing a schedule program for implementing the schedule function to computers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

La présente invention concerne un système d'ordonnancement, etc., capable d'exploiter plus efficacement les performances de traitement dont dispose une ressource. Ce système d'ordonnancement (3004) possède un ordonnanceur (3005) servant à réserver un deuxième canal d'émission en tant que deuxième ressource de communication selon une cinquième instruction servant à réserver le deuxième canal d'émission d'après un premier canal d'émission (105), le deuxième canal d'émission étant capable d'émettre/recevoir des premières données entre une mémoire (103) et une mémoire d'accélérateur (104), les premières données étant traitées par une tâche, et la cinquième instruction étant contenue dans des tâches traitées par un dispositif de traitement de calcul (100) possédant des ressources telles qu'un accélérateur à noyaux multiples (102), la mémoire d'accélérateur (104), un processeur, une mémoire, et le premier canal d'émission (105), le premier canal d'émission (105) étant capable d'émettre/recevoir des données entre l'accélérateur à noyaux multiples (102) et le processeur (101). L'ordonnanceur (3005) détermine également une ressource spécifique d'après les premières données émises/reçues par l'intermédiaire du deuxième canal d'émission, selon une première instruction servant à réserver une ressource.
PCT/JP2014/001558 2012-09-20 2014-03-18 Système d'ordonnancement, procédé d'ordonnancement et support d'enregistrement Ceased WO2014188643A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/787,830 US20160077882A1 (en) 2012-09-20 2014-03-18 Scheduling system, scheduling method, and recording medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013109843A JP2014078215A (ja) 2012-09-20 2013-05-24 スケジュールシステム、スケジュール方法、スケジュールプログラム、及び、オペレーティングシステム
JP2013-109843 2013-05-24

Publications (1)

Publication Number Publication Date
WO2014188643A1 true WO2014188643A1 (fr) 2014-11-27

Family

ID=51939002

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/001558 Ceased WO2014188643A1 (fr) 2012-09-20 2014-03-18 Système d'ordonnancement, procédé d'ordonnancement et support d'enregistrement

Country Status (1)

Country Link
WO (1) WO2014188643A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017119098A1 (fr) * 2016-01-07 2017-07-13 株式会社日立製作所 Système informatique et procédé de commande d'ordinateur
CN109426566A (zh) * 2017-08-22 2019-03-05 英特尔公司 使用开关来连接加速器资源
CN111459645A (zh) * 2020-04-22 2020-07-28 百度在线网络技术（北京）有限公司 一种任务调度方法、装置和电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11249910A (ja) * 1998-02-27 1999-09-17 Hitachi Ltd 記憶サブシステム及びデータ転送制御方法
JP2005018620A (ja) * 2003-06-27 2005-01-20 Toshiba Corp 情報処理システムおよびメモリ管理方法
JP2005309534A (ja) * 2004-04-16 2005-11-04 Sony Corp 画像表示装置
JP2007220064A (ja) * 2006-01-17 2007-08-30 Hitachi Ltd 制御装置および情報システムの制御方法
EP2442228A1 (fr) * 2010-10-13 2012-04-18 Thomas Lippert Agencement de grappe d'ordinateur pour traiter une tâche informatique et son procédé de fonctionnement
JP2012164050A (ja) * 2011-02-04 2012-08-30 Canon Inc 情報処理装置、タスク管理方法、及びプログラム

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11249910A (ja) * 1998-02-27 1999-09-17 Hitachi Ltd 記憶サブシステム及びデータ転送制御方法
JP2005018620A (ja) * 2003-06-27 2005-01-20 Toshiba Corp 情報処理システムおよびメモリ管理方法
JP2005309534A (ja) * 2004-04-16 2005-11-04 Sony Corp 画像表示装置
JP2007220064A (ja) * 2006-01-17 2007-08-30 Hitachi Ltd 制御装置および情報システムの制御方法
EP2442228A1 (fr) * 2010-10-13 2012-04-18 Thomas Lippert Agencement de grappe d'ordinateur pour traiter une tâche informatique et son procédé de fonctionnement
JP2012164050A (ja) * 2011-02-04 2012-08-30 Canon Inc 情報処理装置、タスク管理方法、及びプログラム

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017119098A1 (fr) * 2016-01-07 2017-07-13 株式会社日立製作所 Système informatique et procédé de commande d'ordinateur
JPWO2017119098A1 (ja) * 2016-01-07 2018-11-08 株式会社日立製作所 計算機システム及び計算機の制御方法
CN109426566A (zh) * 2017-08-22 2019-03-05 英特尔公司 使用开关来连接加速器资源
CN111459645A (zh) * 2020-04-22 2020-07-28 百度在线网络技术（北京）有限公司 一种任务调度方法、装置和电子设备
CN111459645B (zh) * 2020-04-22 2023-06-30 百度在线网络技术（北京）有限公司 一种任务调度方法、装置和电子设备

Similar Documents

Publication Publication Date Title
US9135060B2 (en) Method and apparatus for migrating task in multicore platform
US9933951B2 (en) Reducing read latency using a pool of processing cores
US9442763B2 (en) Resource allocation method and resource management platform
JP5972363B2 (ja) デュアル動作システムに対する複数のリソースのためのリソース割り当て
US8429666B2 (en) Computing platform with resource constraint negotiation
US20140250440A1 (en) System and method for managing storage input/output for a compute environment
CN120144326B (zh) 一种数据处理系统、方法、设备、介质及程序产品
US11489735B2 (en) Dynamic network allocation apparatus, dynamic network allocation method and non-transitory computer-readable medium
CN108228482B (zh) 用于管理存储系统中的缓存设备的方法和系统
JP2014078215A (ja) スケジュールシステム、スケジュール方法、スケジュールプログラム、及び、オペレーティングシステム
US8726039B2 (en) Reducing decryption latency for encryption processing
JP6007516B2 (ja) リソース配分システム、リソース配分方法、及びリソース配分プログラム
CN111352735A (zh) 数据加速方法、装置、存储介质及设备
WO2014188643A1 (fr) Système d'ordonnancement, procédé d'ordonnancement et support d'enregistrement
CN113010309B (zh) 集群资源调度方法、装置、存储介质、设备和程序产品
JP2015143943A (ja) 情報処理装置、制御方法、および制御プログラム
JP2012059152A (ja) データ処理を行うシステムおよびメモリを割り当てる方法
WO2014188642A1 (fr) Systeme d'ordonnancement, procede d'ordonnancement et support d'enregistrement
JP6191361B2 (ja) 情報処理システム、情報処理システムの制御方法及び制御プログラム
CN119806840A (zh) 一种资源调控方法和装置
CN117707796B (zh) 资源管理方法、装置、电子设备以及存储介质
US11061733B2 (en) Shared and exclusive accelerator access
US20170083258A1 (en) Information processing device, information processing system, memory management method, and program recording medium
WO2015052823A1 (fr) Dispositif de gestion en nuage, son procédé de gestion et système associé
JP2015156158A (ja) 命令処理装置、命令処理方法、命令処理プログラム、及び、情報処理装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14801167

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14787830

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14801167

Country of ref document: EP

Kind code of ref document: A1