WO2014194669A1 - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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Publication number
WO2014194669A1
WO2014194669A1 PCT/CN2014/070150 CN2014070150W WO2014194669A1 WO 2014194669 A1 WO2014194669 A1 WO 2014194669A1 CN 2014070150 W CN2014070150 W CN 2014070150W WO 2014194669 A1 WO2014194669 A1 WO 2014194669A1
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Prior art keywords
electrode
semiconductor device
shape control
control layer
layer
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PCT/CN2014/070150
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English (en)
French (fr)
Inventor
程凯
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Enkris Semiconductor Inc
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Enkris Semiconductor Inc
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Priority to JP2016517130A priority Critical patent/JP6195979B2/ja
Priority to EP14807330.7A priority patent/EP3010043B1/en
Priority to DK14807330.7T priority patent/DK3010043T3/da
Priority to KR1020157037194A priority patent/KR101780890B1/ko
Priority to SG11201510008UA priority patent/SG11201510008UA/en
Priority to US14/896,364 priority patent/US9640624B2/en
Publication of WO2014194669A1 publication Critical patent/WO2014194669A1/zh
Anticipated expiration legal-status Critical
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
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    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/699—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having the gate at least partly formed in a trench
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
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    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
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    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method of fabricating the same.
  • the distribution of the electric field can be controlled by a number of methods, such as modulation doping of the active region, addition of the field plate to reduce the maximum value of the electric field, and control of the distribution of the electric field by controlling the shape of the electrode.
  • Gallium nitride-based high electron mobility transistor which belongs to a planar channel field effect transistor, whose gate shape control is one of the most important device manufacturing processes.
  • the planar structure of a high electron mobility transistor causes a non-uniform distribution of the electric field strength, especially in the case where the voltage between the source and the drain is high, an extremely high electric field is generated at the edge of the gate close to the drain. strength.
  • Figure 1 shows the electric field intensity distribution between the source and the drain of a gallium nitride-based high electron mobility transistor.
  • the electric field strength is 4 ⁇ at the edge of the gate near the drain, once the peak electric field exceeds the nitridation.
  • the critical electric field of the gallium material the device will be broken down.
  • the withstand voltage of the device is the integral of the electric field between the gate and the drain, the higher the electric field at the gate edge, the lower the voltage the device will withstand than the evenly distributed electric field. This phenomenon can greatly reduce the performance of the device, such as the breakdown voltage of the device and the reliability of the device.
  • the distribution of the electric field can be controlled by many methods, such as modulation doping of the active region, using the field plate to reduce the maximum value of the electric field, and also by controlling the shape of the electrode. Constrain the distribution of the electric field.
  • the field plate expands the horizontal depletion region of the planar device by vertical depletion of the active region of the planar device, thereby causing a change in the electric field intensity distribution of the planar device.
  • the position of the field plate can be at the source, gate or drain, and a single or multiple field plates can be used in the device to vary the distribution of the electric field strength and reduce the maximum electric field strength at the gate edge near the drain.
  • the T-gate changes the electric field distribution at the gate by making the shape of the gate into a T-shape, using the shape characteristics of the T-gate itself.
  • the dielectric layer is indispensable, and the most common dielectric layer is silicon nitride. Due to the limitations of the manufacturing process, the complex shape of the field plate is difficult to implement in the process, or the manufacturing process is complicated or impossible. Due to the limitations of the manufacturing process, the shape of the gate is also relatively simple, and the gates of various shapes are also difficult to manufacture, or the fabrication process is complicated or impossible. Therefore, there is an urgent need to develop new fabrication processes to implement complex shaped field plates and gates of various shapes.
  • the invention discloses an electrode shape control layer, wherein the electrode shape control layer contains aluminum element, and the content of the aluminum element in the layer can be adjusted.
  • the electrode shape control layer is etched, the lateral and longitudinal etching speeds are As the content of aluminum changes, the shape of the etched section can be controlled, and the etched sections of different shapes can be designed and fabricated. After the electrodes are deposited, electrodes of corresponding shapes are formed, thereby achieving the purpose of controlling the shape of the electrodes.
  • the content of aluminum in the shape control layer of the adjustment electrode is gradually decreased from bottom to top, for example: when the downward trend is linearly decreased, the side of the groove is sloped, and the shape of the etching section is trapezoidal, deposition After the electrode, the electrode section is also trapezoidal, dispersing the distribution of the electric field peak; when the downward trend is decelerating and decreasing, the side of the groove is an arc-shaped slope that is concave toward both sides, and the shape of the etching section is U-shaped, after depositing the electrode
  • the electrode cross section is also U-shaped, and the electric field distribution at the edge of the electrode changes correspondingly, smoothing the electric field distribution; when the downward trend is accelerated, the side of the groove is an arc-shaped slope protruding toward the middle, after depositing the electrode
  • the electrode section also has the same groove interface, and the electric field distribution at the edge of the electrode changes correspondingly, which smoothes the electric field distribution.
  • a semiconductor device comprising:
  • Electrode shape control layer on the active region of the semiconductor device, wherein the electrode shape control layer contains an aluminum element, and the content of the aluminum element in all or part of the electrode shape control layer gradually decreases from the bottom to the top of the active region of the semiconductor device Reducing, the electrode shape control layer is provided with an electrode region, and the groove, the side surface of the groove is all or part of a slope, or an arc slope which is trapped to both sides, or an arc-shaped slope which protrudes toward the middle;
  • the electrode shape is corresponding to the shape of the groove, and the bottom of the electrode is in contact with the active region of the semiconductor device.
  • the electrode shape control layer is a combination of one or both of a semiconductor layer and a first dielectric layer.
  • the semiconductor layer in the active region of the semiconductor device and the electrode shape control layer is a combination of one or more of a group III nitride, a silicon, a germanium, a silicon, a mv compound, and an oxide. .
  • the first dielectric layer comprises a combination of one or more of SiN, SiAIN, SiAlGaN, SiA10x, AlMgON, HfAlOx.
  • the electrode shape control layer is a semiconductor layer and a first dielectric layer
  • the first dielectric layer is located above the semiconductor layer, and the content of the aluminum element in any one of the semiconductor layers is higher than the first medium. The content of any aluminum element in the layer.
  • the content of the aluminum element in all or part of the electrode shape control layer is linearly decreased from the bottom to the top of the active region of the semiconductor device, or is accelerated down, or decelerated. Drop, or first linearly fall and then remain unchanged, or decelerate and then remain unchanged, or accelerate down and then remain unchanged.
  • the groove portion in the electrode shape control layer extends into the active region of the semiconductor device.
  • the inner wall of the groove in the electrode shape control layer and the surface of the electrode shape control layer are all or partially deposited with a second dielectric layer, and the electrodes are all or partially located on the second dielectric layer.
  • the second dielectric layer comprises a combination of one or more of A1203, A10N, SiN, SiON, SiO2, HfA10x, Hf02.
  • the semiconductor device comprises a diode and a triode, the electrode comprising an anode and a cathode of the diode and a source, a drain and a gate of the transistor.
  • the active region of the semiconductor device comprises: a high electron mobility transistor formed by an aluminum gallium nitride/gallium nitride heterostructure, a high electron mobility formed by an aluminum gallium indium nitride/gallium nitride heterostructure Rate transistor, high mobility triode with aluminum nitride/gallium nitride heterostructure, gallium nitride MOSFET, device with indium gallium nitride/gallium nitride multiple quantum well structure, light emitting diode composed of p-type nitride, UV- LED, photodetector, hydrogen generator, solar cell, LDMOS, UMOSFET, Schottky diode or avalanche breakdown diode.
  • a method for fabricating a semiconductor device comprising:
  • an electrode shape control layer on the active region of the semiconductor device, wherein the electrode shape control layer contains aluminum element, and the content of aluminum element in all or part of the electrode shape control layer is from the active region of the semiconductor device
  • the electrode shape control layer is provided with an electrode region; the electrode of the pole shape control layer, the side surface of the groove is all or part of a slope, or an arc slope which is trapped to both sides, or protrudes toward the middle. Curved slope
  • the steps S3 and S4 are specifically: 531, applying a first mask layer on the electrode shape control layer, performing photolithography to expose the electrode region;
  • the electrode shape control layer in the step S2 is a combination of one or two of a semiconductor layer and a first dielectric layer, and the growth mode of the first dielectric layer includes MOCVD, PECVD, LPCVD, MBE, CVD, or GCIB.
  • the method further includes:
  • Second dielectric layer in whole or in part on the inner wall of the groove and the surface of the electrode shape control layer in the electrode shape control layer, the second dielectric layer comprising one or more of A1203, A10N, SiN, SiON, SiO2, HfA10x, Hf02 Combination of species.
  • the beneficial effects of the present invention are as follows:
  • the semiconductor device of the present invention and the method of fabricating the same use an electrode shape control layer on the active region of the semiconductor device, and the content of the aluminum element in the electrode shape control layer varies with the thickness.
  • Controlling the ratio of the lateral and longitudinal etching speeds during the etching process by controlling the change in the content of the elements in the shape control layer of the electrode, thereby changing the shape of the etching section during the etching process to achieve the electrode during the formation of the control electrode
  • the shape from the process to achieve control of a variety of electrode shapes.
  • the etching speed is controlled by the material of the material, it is not necessary to change the process parameters in the etching process, so the controllability and repeatability are good, and the cylinder is easy to operate.
  • some special shapes can be realized, which is not possible with ordinary etching processes.
  • FIG. 1 is a schematic diagram showing the electric field intensity distribution between a source and a drain when a gallium nitride-based high electron mobility transistor operates;
  • FIG. 2 is a schematic structural view of a semiconductor device according to Embodiment 1 of the present invention.
  • 3A to 3G are schematic flowcharts showing a method of fabricating a semiconductor device according to Embodiment 1 of the present invention.
  • FIGS. 4A to 4H are schematic flow charts showing a method of fabricating a semiconductor device according to a second embodiment of the present invention.
  • FIG. 5 is a schematic view showing a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 6 is a schematic view showing a semiconductor device in Embodiment 4 of the present invention.
  • FIG. 7 is a schematic view showing a semiconductor device in Embodiment 5 of the present invention.
  • Embodiment 8 is a schematic view showing a semiconductor device in Embodiment 6 of the present invention.
  • Embodiment 7 of the present invention is a schematic view showing a semiconductor device in Embodiment 7 of the present invention.
  • FIG. 10 is a schematic view showing a semiconductor device according to Embodiment 8 of the present invention.
  • Figure 11 is a schematic view showing a semiconductor device in a ninth embodiment of the present invention.
  • Figure 12 is a schematic view showing a semiconductor device in a tenth embodiment of the present invention.
  • the embodiment of the invention discloses a semiconductor device, comprising:
  • the electrode shape control layer on the active region of the semiconductor device contains aluminum element, and the content of aluminum element in all or part of the electrode shape control layer is from the active region of the semiconductor device From the bottom to the top, the electrode shape control layer is provided with an electrode region, and the electrode region is provided with a groove extending toward the active region of the semiconductor device and extending longitudinally through the electrode shape control layer, and the sides of the groove are all or part of a slope, or both sides a curved slope of a depression, or an arcuate slope that protrudes toward the center;
  • the electrode is wholly or partially located in the recess in the electrode region, and the shape of the electrode is corresponding to the shape of the recess, and the bottom of the electrode is in contact with the active region of the semiconductor device.
  • the present invention also discloses a method for fabricating a semiconductor device, including:
  • an electrode shape control layer on the active region of the semiconductor device, wherein the electrode shape control layer contains aluminum element, and the content of the aluminum element in all or part of the electrode shape control layer is gradually reduced from the bottom to the top of the active region of the semiconductor device, and the electrode shape
  • the control layer is provided with an electrode area; the groove of the control layer, the side of the groove is all or part of a slope, or an arc-shaped slope which is trapped to both sides, or an arc-shaped slope which protrudes toward the middle;
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the semiconductor device includes: a semiconductor device active region 1;
  • the electrode shape control layer 2 on the active region 1 of the semiconductor device contains aluminum element, and the content of the aluminum element gradually decreases from the bottom to the top of the active region of the semiconductor device, and the downward trend is linear decrease, and the electrode shape control layer 2 is defined with an electrode region, the electrode region is provided with a groove extending toward the active region of the semiconductor device and extending longitudinally through the electrode shape control layer, the groove is an inverted trapezoid, and the side surface is a slope;
  • the electrode 5 is located in the groove in the electrode region, and the shape of the electrode 5 is corresponding to the shape of the groove.
  • the electrode 5 is in contact with the active region 1 of the semiconductor device.
  • the electrode 5 is partially in the groove and partially in the groove. Above.
  • the method for fabricating the semiconductor device of the present embodiment includes: Providing an active region 1 of the semiconductor device, as shown in FIG. 3A;
  • the electrode shape control layer 2 is formed on the active region 1 of the semiconductor device, and the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from bottom to top, and the downward trend is linearly decreased, and the electrode shape is defined on the electrode shape control layer.
  • Figure 3B
  • the feature of the groove The size can be adjusted by an etching process, and the feature size of the groove can be slightly larger or smaller than the feature size of the photolithography as compared with the feature size of the photolithography, as shown in FIG. 3D1 and FIG. 3D2, respectively;
  • the electrode is deposited, the second mask layer 4 is removed, and the electrode 5 is formed, as shown in Fig. 3G.
  • the content of the aluminum element in the electrode shape control layer is gradually decreased from bottom to top, and when the downward trend is linearly decreased, the side surface of the groove is a slope, the shape of the etching section is trapezoidal, and after the electrode is deposited, the electrode section is also trapezoidal. This causes the electric field distribution at the edge of the electrode to change linearly, dispersing the distribution of the electric field peaks.
  • the electrode shape control layer 2 may be one of a semiconductor layer and a first dielectric layer or a combination of two.
  • the semiconductor device semiconductor layer is a combination of one or more of a group III nitride, silicon, germanium, silicon, mv compound, oxide; the first dielectric layer includes one of SiN, SiAlN, SiAlGaN, SiA10x, AlMgON, HfAlOx Combination of species or multiples.
  • the first dielectric layer may be grown by MOCVD, PECVD, LPCVD, MBE, CVD, or GCIB.
  • the electrode shape control layer 2 is a semiconductor layer and a first dielectric layer
  • the first dielectric layer is located above the semiconductor layer, and the content of the aluminum element in any one of the semiconductor layers is higher than the content of any aluminum element in the first dielectric layer.
  • the content of the aluminum element in the electrode shape control layer as a whole is gradually decreased linearly from the bottom to the top of the active region of the semiconductor device.
  • the active region of the semiconductor device in the embodiment includes: a high electron mobility transistor formed of an aluminum gallium nitride/gallium nitride heterostructure, a high electron mobility transistor formed of an aluminum gallium indium nitride/gallium nitride heterostructure, High mobility transistor made of aluminum nitride/gallium nitride heterostructure, gallium nitride MOSFET, device containing indium gallium nitride/gallium nitride multiple quantum well structure, light emitting diode composed of p-type nitride, UV-LED, photoelectric Detectors, hydrogen generators or solar cells can also be LDMOS, UMOSFET, diodes, Schottky diodes, avalanche breakdown diodes, etc.
  • the inner wall of the groove in the electrode shape control layer 2 and the surface of the electrode shape control layer 2 are entirely or partially deposited with a second dielectric layer, and the electrodes are wholly or partially located on the second dielectric layer.
  • the second dielectric layer may be a combination of one or more of A1203, A10N, SiN, SiON, SiO2, HfA10x, Hf02, and the deposition method is PECVD, LPCVD, CVD, ALD, MOCVD or PVD.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • 4H is a schematic structural view of the semiconductor device described in the second embodiment; the structure is substantially the same as that of the semiconductor device described in the first embodiment, except that the recess portion extends into the active region of the semiconductor device.
  • FIG. 4A-4H The manufacturing method corresponding to the embodiment is shown in FIG. 4A-4H, and the specific manufacturing steps are as follows: providing an active region 1 of the semiconductor device, as shown in FIG. 4A;
  • the electrode shape control layer 2 is formed on the active region 1 of the semiconductor device, and the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from bottom to top, and the downward trend is linearly decreased, and the electrode shape is defined on the electrode shape control layer.
  • Figure 4B
  • the shape of the groove varies with the content of the aluminum element in the electrode shape control layer 2, the characteristics of the groove
  • the size can be adjusted by an etching process.
  • the feature size of the groove can be slightly larger or smaller than the feature size of the photolithography, which is slightly larger than that shown in FIG. 4D;
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • Fig. 5 is a schematic view showing the semiconductor device described in the third embodiment.
  • the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from the bottom to the top, and the downward trend is an accelerated decrease.
  • the rest is the same as the first embodiment, and details are not described herein again.
  • the content of aluminum element in the electrode shape control layer is gradually decreased from bottom to top, and when the downward trend is accelerated, the side surface of the groove is an arc-shaped slope which is convex toward the middle, and after the electrode is deposited, the electrode section also has a groove interface. Similarly, the electric field distribution at the edge of the electrode changes accordingly, smoothing the electric field distribution.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • Fig. 6 is a schematic view showing the semiconductor device described in the fourth embodiment.
  • the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from the bottom to the top, and the downward trend is the deceleration.
  • the rest is the same as the first embodiment, and details are not described herein again.
  • the content of the aluminum element in the electrode shape control layer is gradually decreased from bottom to top, and the downward trend is decelerating, and the side surface of the groove is an arc-shaped slope which is recessed toward both sides, and the shape of the etching section is U-shaped, deposition
  • the cross section of the electrode is also U-shaped, and the electric field distribution at the edge of the electrode changes correspondingly, which smoothes the electric field distribution.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • Fig. 7 is a schematic view showing the semiconductor device described in the fifth embodiment.
  • the content of the aluminum element in the electrode shape control layer 2 in this embodiment is linearly decelerated from bottom to top and remains unchanged. The rest is the same as the first embodiment, and details are not described herein again.
  • the content of the aluminum element in the electrode shape control layer is linearly decelerated and then remains unchanged.
  • the groove is trapezoidal in the linear deceleration portion, and the portion which remains unchanged is a rectangle, and the shape of the etched section is rectangular above and trapezoidal at the bottom.
  • the electrode section is the same as the etched section.
  • Fig. 8 is a schematic view showing the semiconductor device described in the sixth embodiment.
  • the content of the aluminum element in the electrode shape control layer 2 is decelerated from the bottom to the top and then remains unchanged. The rest is the same as the first embodiment, and details are not described herein again.
  • the content of the aluminum element in the electrode shape control layer is first decelerated and then remains unchanged, the groove is u-shaped in the deceleration and descending portion, and the portion which remains unchanged is a rectangle, and the shape of the etched section is rectangular above, and the lower part is U-shaped, after the electrode is deposited, the electrode section is the same as the etched section.
  • Fig. 9 is a schematic view showing the semiconductor device described in the seventh embodiment.
  • the active region of the semiconductor device is a nitride high electron mobility transistor, the nucleation layer 12 grown on any of the substrates 11, the nitride buffer layer 13 grown on the nucleation layer 12, and the nitride buffer A nitride channel layer 14 grown on the layer 13, a nitride barrier layer 15 grown on the nitride channel layer 14, and a nitride layer 16 grown on the nitride barrier layer 15.
  • the electrode 51 is a gate electrode, and the electrode 52 and the electrode 53 are respectively a source and a drain of an ohmic contact. Among them, the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from the bottom to the top, and the downward trend is an accelerated decrease. Therefore, the electrode 51 is an arc-shaped structure which is convex toward the center in the electrode shape control layer 2.
  • Fig. 10 is a schematic view showing the semiconductor device described in the eighth embodiment.
  • the active region of the semiconductor device is an N-channel enhancement type MOSFET, two highly doped N+ regions 12 and 13 on the P-type substrate 11, and the electrode shape control layer 2 is a dielectric layer, wherein the aluminum element The content is gradually decreased from bottom to top, and the downward trend is linearly decreased; the electrode 51 is a gate, the electrode 52 is a source, and the electrode 53 is a drain.
  • Figure 11 is a schematic view showing the semiconductor device described in Embodiment 9.
  • the active region of the semiconductor device is a Schottky diode fabricated by a common CMOS process, an N-type layer 12 on the P-type substrate 11, an N+ cathode layer 13 in the N-type layer 12, and an electrode shape control layer 2 as a medium.
  • the content of the aluminum element is gradually decreased from bottom to top, and the downward trend is linearly decreased; the electrode 51 is an anode, and the electrode 52 is a cathode.
  • Fig. 12 is a view showing the semiconductor device of the tenth embodiment.
  • the active region of the semiconductor device is a vertical structure PIN diode, the semiconductor N+ layer 12 on the substrate 11, the semiconductor I layer 13 on the semiconductor N+ layer 12, and the semiconductor I layer 13
  • the electrode shape control layer 2 is a dielectric layer in which the content of the aluminum element is gradually decreased from bottom to top, and the downward trend is linearly decreased;
  • the electrode 51 is an anode, and the electrode 52 is a cathode.
  • the semiconductor device of the present invention and the method of fabricating the same use an electrode shape control layer on the active region of the semiconductor device, and the content of the aluminum element in the electrode shape control layer varies with thickness. Varying, by controlling the change in the content of the elements in the shape control layer of the electrode, the ratio of the lateral and longitudinal etching speeds during the etching process is controlled, thereby changing the shape of the etching section during the etching process to achieve the formation of the control electrode.
  • the shape of the electrode realizes the control of various electrode shapes from the process.
  • the etching speed is controlled by the material of the material, it is not necessary to change the process parameters in the etching process, so the controllability and repeatability are good, and the cylinder is easy to operate.
  • some special shapes can be realized, which is not possible with ordinary etching processes.

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Abstract

提供一种半导体器件及其制作方法。该半导体器件包括：半导体器件有源区（1）；位于半导体器件有源区（1）上的电极形状控制层（2），电极形状控制层（2）中含有铝元素，铝元素的含量从半导体器件有源区（1）由下至上逐渐减少；电极形状控制层（2）上设有电极区，电极区设有向半导体器件有源区（1）延伸并纵向贯穿所述电极形状控制层（2）的凹槽，凹槽的侧面全部或部分为斜坡、或向两侧凹陷的弧形坡、或向中间凸出的弧形坡；全部或部分位于电极区中凹槽内的电极（5），电极（5）形状与凹槽形状对应设置，电极（5）底部与半导体器件有源区（1）相接触。通过控制电极（5）的形状，改变电极（5）附近电场强度的分布，提高半导体器件的击穿电压和可靠性等性能。

Description

半导体器件及其制作方法
本申请要求于 2013 年 6 月 6 日提交中国专利局、 申请号为 201310223571.7、 发明名称为"半导体器件及其制作方法"的中国专利申请 的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体技术领域， 特别是涉及一种半导体器件及其制作方 法。
背景技术
在半导体器件中， 为了提高器件的击穿电压， 改善器件的可靠性， 电 场强度如何分布， 如何避免局部电场强度过大， 是半导体器件设计中必须 要考虑的问题之一。 电场的分布可以通过很多办法控制， 比如说对有源区 进行调制掺杂， 添加场板减小电场的最大值， 也可以通过控制电极的形状 对电场的分布进行约束。
例如： 氮化镓基高电子迁移率晶体管， 属于一种平面沟道场效应晶体 管， 其栅极形状的控制是非常重要的器件制造工艺之一。 高电子迁移率晶 体管的平面结构会引起电场强度的非均匀分布， 特别是在源极和漏极之间 的电压较高的情况下， 在靠近漏极的栅极的边缘会产生极高的电场强度。 图 1示出了氮化镓基高电子迁移率晶体管工作时源极和漏极之间的电场强 度分布， 在靠近漏极的栅极的边缘电场强度 4艮高， 一旦该峰值电场超过氮 化镓材料的临界电场， 器件就会被击穿。 由于器件的耐受电压是栅极和漏 极间电场的积分， 相对于均匀分布的电场， 栅极边缘的电场越高， 器件承 受的电压就越小。 此种现象会大大降低器件的工作性能， 如导致器件的击 穿电压降低和器件的可靠性下降等。
对于肖特基二极管来说， 在其电极边缘的电场也存在一个局部的极大 值， 需要构建一个场板或者在边缘处形成耗尽层， 改善电场的分布。
对于平面结构的 LDMOS, 以及具有垂直结构的 MOSFET,如 UMOS, 电极边缘也存在峰值电场， 也需要控制电极的形状或者添加边缘处场板等 方法来改善电场的分布。 对于具有垂直结构的 UMOS或者 VDMOS, 边缘 处的电场也同样需要加以控制。
为了改变电场强度的分布， 改善器件的工作性能， 电场的分布可以通 过很多办法控制， 比如说对有源区进行调制掺杂， 使用场板减小电场的最 大值， 也可以通过控制电极的形状对电场的分布进行约束。
场板是通过对平面器件有源区的垂直耗尽来扩展平面器件的水平耗尽 区， 从而引起平面器件电场强度分布的改变。 场板的位置可以在源极、 栅 极或漏极处，在器件中可以采用单个或多个场板， 以改变电场强度的分布， 降低靠近漏极的栅极边缘处的最大电场强度。
T型栅极 ( T-gate )通过把栅极形状制作成 T型， 利用 T型栅极本身 的形状特征来改变栅极处的电场分布。
在制作场板和 T型栅极的工艺过程中， 介质层是必不可少的， 最常用 的介质层是氮化硅。 受到制作工艺的限制， 复杂形状的场板在工艺上实现 起来比较困难， 要么制作工艺比较复杂， 要么就根本无法实现。 受到制作 工艺的限制， 栅极的形状也一直比较单一， 多种形状的栅极同样制作起来 比较困难， 要么制作工艺比较复杂， 要么也是根本无法实现。 因此， 迫切 需要开发新的制作工艺来实现复杂形状的场板和多种形状的栅极。
因此，针对上述技术问题，有必要提供一种半导体器件及其制作方法。 发明内容
有鉴于此，本发明的目的在于提供一种新的半导体器件及其制作方法， 采用了一种新的制作工艺使多种形状的电极的实现成为了可能。
本发明揭示了一种电极形状控制层，该电极形状控制层中含有铝元素， 该层中铝元素的含量是可以调节的， 电极形状控制层被刻蚀时， 横向和纵 向的刻蚀速度是随着铝元素的含量而变化的， 这样可以控制刻蚀截面的形 状， 设计制作出不同形状的刻蚀截面， 沉积电极后就制作出了相应形状的 电极， 从而达到了控制电极形状的目的。
调节电极形状控制层中铝元素的含量由下至上逐渐减少， 例如： 当下 降趋势呈线性下降时， 凹槽的侧面为斜坡， 刻蚀截面的形状为梯形， 沉积 电极后， 电极截面也为梯形， 分散了电场峰值的分布； 当下降趋势呈减速 下降时， 凹槽的侧面为向两侧凹陷的弧形坡， 刻蚀截面的形状为 U形， 沉 积电极后，电极截面也为 U形，电极边缘的电场分布就发生了相应的变化， 平緩了电场分布； 当下降趋势呈加速下降时， 凹槽的侧面为向中间凸出的 弧形坡， 沉积电极后， 电极截面也凹槽界面相同， 电极边缘的电场分布就 发生了相应的变化， 平緩了电场分布。
为了实现上述目的， 本发明实施例提供的技术方案如下：
一种半导体器件， 所述半导体器件包括：
半导体器件有源区；
位于所述半导体器件有源区上的电极形状控制层， 所述电极形状控制 层中含有铝元素， 所述全部或部分电极形状控制层中铝元素的含量从半导 体器件有源区由下至上逐渐减少， 所述电极形状控制层上设有电极区， 所 槽， 所述 槽的侧面全部或部分为斜坡、 或向两侧 陷的弧形坡、 或向 中间凸出的弧形坡；
全部或部分位于所述电极区中凹槽内的电极， 所述电极形状与凹槽形 状对应设置， 所述电极底部与半导体器件有源区相接触。
作为本发明的进一步改进， 所述电极形状控制层为半导体层、 第一介 质层中一种或两种的组合。
作为本发明的进一步改进， 所述半导体器件有源区和电极形状控制层 中的半导体层为三族氮化物、 硅、 锗、 错硅、 m-v族化合物、 氧化物中一 种或多种的组合。
作为本发明的进一步改进，所述第一介质层包括 SiN、 SiAIN、 SiAlGaN、 SiA10x、 AlMgON、 HfAlOx中一种或多种的组合。
作为本发明的进一步改进， 所述电极形状控制层为半导体层和第一介 质层时， 第一介质层位于半导体层的上方， 所述半导体层中任意一处铝元 素的含量高于第一介质层中任意一处铝元素的含量。
作为本发明的进一步改进， 所述全部或部分电极形状控制层中铝元素 的含量从半导体器件有源区由下至上呈线性下降、 或加速下降、 或减速下 降、 或先线性下降再保持不变、 或先减速下降再保持不变、 或先加速下降 再保持不变。
作为本发明的进一步改进， 所述电极形状控制层中的 槽部分延伸至 半导体器件有源区中。
作为本发明的进一步改进， 所述电极形状控制层中的 槽内壁及电极 形状控制层表面上全部或部分沉积有第二介质层， 所述电极全部或部分位 于所述第二介质层上。
作为本发明的进一步改进， 所述第二介质层包括 A1203、 A10N、 SiN、 SiON、 Si02、 HfA10x、 Hf02中一种或多种的组合。
作为本发明的进一步改进， 所述半导体器件包括二极管和三极管， 所 述电极包括二极管的阳极和阴极以及三极管的源极、 漏极和栅极。
作为本发明的进一步改进， 所述半导体器件有源区包括： 铝镓氮 /氮化 镓异质结构成的高电子迁移率晶体管、铝镓铟氮 /氮化镓异质结构成的高电 子迁移率晶体管、 氮化铝 /氮化镓异质结构成的高迁移率三极管、 氮化镓 MOSFET、 含有铟镓氮 /镓氮多量子阱结构的器件、 p型氮化物构成的发光 二极管、 UV-LED、 光电探测器、 氢气产生器、 太阳能电池、 LDMOS、 UMOSFET、 肖特基二极管或者雪崩击穿二极管。
相应地， 一种半导体器件制作方法， 所述方法包括：
Sl、 提供半导体器件有源区；
S2、 在所述半导体器件有源区上形成电极形状控制层， 所述电极形状 控制层中含有铝元素， 所述全部或部分电极形状控制层中铝元素的含量从 半导体器件有源区由下至上逐渐减少，所述电极形状控制层上设有电极区； 极形状控制层的 槽， 所述 槽的侧面全部或部分为斜坡、 或向两侧 陷 的弧形坡、 或向中间凸出的弧形坡；
S4、 在所述电极区中凹槽内的形成电极， 所述电极全部或部分位于电 极区中凹槽内， 所述电极形状与凹槽形状对应设置， 所述电极底部与半导 体器件有源区相接触。
作为本发明的进一步改进， 所述步骤 S3和 S4具体为： 531、在所述电极形状控制层上涂上第一掩膜层， 进行光刻， 露出电极 区；
532、 刻蚀所述电极区， 形成向半导体器件有源区延伸的凹槽；
533、 去除第一掩膜层；
S41、在所述电极形状控制层上涂上第二掩膜层， 进行光刻， 露出电极 区；
S42、 沉积电极， 去除第二掩膜层， 形成电极。
作为本发明的进一步改进，所述步骤 S2中的电极形状控制层为半导体 层、 第一介质层中一种或两种的组合， 第一介质层的生长方式包括 MOCVD、 PECVD、 LPCVD、 MBE、 CVD、 或 GCIB。
作为本发明的进一步改进， 所述步骤 S4前还包括：
在所述电极形状控制层中的 槽内壁及电极形状控制层表面上全部或 部分沉积第二介质层， 第二介质层包括 A1203、 A10N、 SiN、 SiON、 Si02、 HfA10x、 Hf02中一种或多种的组合。
本发明的有益效果是： 本发明半导体器件及其制作方法在半导体器件 中有源区上采用了一种电极形状控制层， 电极形状控制层中的铝元素的含 量是随着厚度的变化而变化的， 通过控制电极形状控制层中所述元素的含 量变化， 来控制刻蚀过程中横向和纵向刻蚀速度的比例， 从而改变刻蚀过 程中的刻蚀截面形状， 达到控制电极形成过程中电极的形状， 从工艺上实 现了对多种电极形状的控制。
由于刻蚀的速度是由材料的材质来控制， 无需改变刻蚀过程中的工艺 参数， 因此控制性、 重复性好， 筒单易行。 另外， 可以实现一些特殊的形 状， 这是普通刻蚀工艺无法实现的。 通过控制电极的形状， 改变电极附近 电场强度的分布， 提高半导体器件的击穿电压和可靠性等性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对 实施例或现有技术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图仅仅是本发明中记载的一些实施例， 对于本领域普通技 术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其 他的附图。
图 1为氮化镓基高电子迁移率晶体管工作时源极和漏极之间的电场强 度分布的示意图；
图 2为本发明实施例一中半导体器件的结构示意图；
图 3A至图 3G所示为本发明实施例一中半导体器件的制作方法的流程 示意图；
图 4A至图 4H所示为本发明实施例二中半导体器件的制作方法的流程 示意图；
图 5所示为本发明实施例三中半导体器件的示意图；
图 6所示为本发明实施例四中半导体器件的示意图；
图 7所示为本发明实施例五中半导体器件的示意图；
图 8所示为本发明实施例六中半导体器件的示意图；
图 9所示为本发明实施例七中半导体器件的示意图；
图 10所示为本发明实施例八中半导体器件的示意图；
图 11所示为本发明实施例九中半导体器件的示意图；
图 12所示为本发明实施例十中半导体器件的示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。 但这些 实施方式并不限制本发明， 本领域的普通技术人员根据这些实施方式所做 出的结构、 方法、 或功能上的变换均包含在本发明的保护范围内。
此外， 在不同的实施例中可能使用重复的标号或标示。 这些重复仅为 了筒单清楚地叙述本发明， 不代表所讨论的不同实施例及 /或结构之间具有 任何关联性。
本发明实施例公开了一种半导体器件， 包括：
半导体器件有源区；
位于半导体器件有源区上的电极形状控制层， 电极形状控制层中含有 铝元素， 全部或部分电极形状控制层中铝元素的含量从半导体器件有源区 由下至上逐渐减少， 电极形状控制层上设有电极区， 电极区设有向半导体 器件有源区延伸并纵向贯穿电极形状控制层的 槽， 槽的侧面全部或部 分为斜坡、 或向两侧凹陷的弧形坡、 或向中间凸出的弧形坡；
全部或部分位于电极区中凹槽内的电极， 电极形状与凹槽形状对应设 置， 所述电极底部与半导体器件有源区相接触。
相应地， 本发明还公开了一种半导体器件制作方法， 包括：
51、 提供半导体器件有源区；
52、 在半导体器件有源区上形成电极形状控制层， 电极形状控制层中 含有铝元素， 全部或部分电极形状控制层中铝元素的含量从半导体器件有 源区由下至上逐渐减少， 电极形状控制层上设有电极区； 状控制层的 槽， 槽的侧面全部或部分为斜坡、或向两侧 陷的弧形坡、 或向中间凸出的弧形坡；
S4、 在电极区中凹槽内的形成电极， 电极全部或部分位于电极区中凹 槽内， 电极形状与凹槽形状对应设置， 电极底部与半导体器件有源区相接 触。
以下结合各种不同的实施例对本发明作进一步说明。
实施例一：
本实施例中半导体器件结构参图 2所示， 该半导体器件包括： 半导体器件有源区 1 ;
在半导体器件有源区 1上的电极形状控制层 2, 电极形状控制层中含 有铝元素， 铝元素的含量从半导体器件有源区由下至上逐渐减少， 下降趋 势是线性下降， 电极形状控制层 2上定义有电极区， 电极区设有向半导体 器件有源区延伸并纵向贯穿电极形状控制层的 槽， 槽为倒置的梯形， 侧面为斜坡；
位于电极区中凹槽内的电极 5 , 电极 5形状与凹槽形状对应设置， 电 极 5与半导体器件有源区 1相接触， 本实施例中， 电极 5部分在凹槽内， 部分位于凹槽上方。
参图 3A-3G所示， 本实施方式中半导体器件的制作方法包括： 提供半导体器件有源区 1 , 参图 3A所示；
在半导体器件有源区 1上形成电极形状控制层 2, 电极形状控制层 2 中的铝元素的含量是由下至上逐渐减少， 下降趋势是线性下降， 电极形状 控制层上定义有电极区， 参图 3B所示；
在电极形状控制层 2上涂上第一掩膜层 3 , 经过光刻， 露出电极区， 参图 3C所示；
刻蚀电极区， 形成向半导体器件有源区延伸的 槽， 槽至少部分贯 穿电极形状控制层， 槽的形状随着电极形状控制层 2中的铝元素的含量 的变化而变化， 凹槽的特征尺寸可以通过刻蚀工艺进行调节， 与光刻的特 征尺寸相比， 槽的特征尺寸可以略大于或略小于光刻的特征尺寸， 分别 参照图 3D1和图 3D2所示；
去掉第一掩膜层 3, 参图 3E所示；
涂上第二掩膜层 4, 经过光刻， 露出电极区， 参图 3F所示；
沉积电极， 去掉第二掩膜层 4, 形成电极 5, 参图 3G所示。
本实施方式中电极形状控制层中铝元素的含量由下至上逐渐减少， 下 降趋势呈线性下降时， 凹槽的侧面为斜坡， 刻蚀截面的形状为梯形， 沉积 电极后， 电极截面也为梯形，这样就使得电极边缘的电场分布呈线性变化， 分散了电场峰值的分布。
本实施方式中电极形状控制层 2可为半导体层、 第一介质层中一种或 两种的组合。 半导体器件半导体层为三族氮化物、 硅、 锗、 错硅、 m-v族 化合物、 氧化物中一种或多种的组合； 第一介质层包括 SiN、 SiAlN、 SiAlGaN、 SiA10x、 AlMgON、 HfAlOx中一种或多种的组合。 第一介质层 的生长方式可以是 MOCVD、 PECVD、 LPCVD、 MBE、 CVD、 或 GCIB。
当电极形状控制层 2为半导体层和第一介质层时， 第一介质层位于半 导体层的上方， 半导体层中任意一处铝元素的含量高于第一介质层中任意 一处铝元素的含量， 整体上电极形状控制层中铝元素的含量从半导体器件 有源区由下至上逐渐线性减少。
本实施方式中半导体器件有源区包括： 铝镓氮 /氮化镓异质结构成的高 电子迁移率晶体管、 铝镓铟氮 /氮化镓异质结构成的高电子迁移率晶体管、 氮化铝 /氮化镓异质结构成的高迁移率三极管、 氮化镓 MOSFET、含有铟镓 氮 /镓氮多量子阱结构的器件、 p 型氮化物构成的发光二极管、 UV-LED、 光电探测器、 氢气产生器或太阳能电池， 还可以为 LDMOS、 UMOSFET、 二极管、 肖特基二极管、 雪崩击穿二极管等。
进一步地， 电极形状控制层 2中的凹槽内壁及电极形状控制层 2表面 上全部或部分沉积有第二介质层， 电极全部或部分位于第二介质层上。 第 二介质层可以为 A1203、 A10N、 SiN、 SiON、 Si02、 HfA10x、 Hf02中一 种或多种的组合， 沉积的方法为 PECVD、 LPCVD、 CVD、 ALD、 MOCVD 或 PVD。
实施例二：
图 4H为实施例二所描述的半导体器件的结构示意图； 其结构与实施 例一所描述的半导体器件基本相同， 区别之处在于： 凹槽部分延伸到了半 导体器件有源区中。
该实施例对应的制作方法， 参图 4A-4H所示， 具体制作步骤如下： 提供半导体器件有源区 1 , 参图 4A所示；
在半导体器件有源区 1上形成电极形状控制层 2, 电极形状控制层 2 中的铝元素的含量是由下至上逐渐减少， 下降趋势是线性下降， 电极形状 控制层上定义有电极区， 参图 4B所示；
在电极形状控制层 2上涂上第一掩膜层 3, 经过光刻， 露出电极区， 参图 4C所示；
刻蚀电极形状控制层 2上的电极区， 形成贯穿了电极形状控制层 2的 凹槽，凹槽的形状随着电极形状控制层 2中的铝元素的含量的变化而变化， 凹槽的特征尺寸可以通过刻蚀工艺进行调节， 与光刻的特征尺寸相比， 凹 槽的特征尺寸可以略大于或略小于光刻的特征尺寸， 参图 4D所示为略大 于的情形；
刻蚀 槽处的半导体器件有源区， 形成延伸至半导体器件有源区 1中 的凹槽， 参图 4E所示；
去掉第一掩膜层 3, 参图 4F所示；
涂上第二掩膜层 4, 经过光刻， 露出电极区， 参 4G所示； 沉积电极， 去掉第二掩膜层 4, 形成电极 5 , 参图 4H所示。
其余结构及制作方法均与实施例一相同， 在此不再赘述。
实施例三：
图 5所示为实施例三所描述半导体器件的示意图。
本实施方式中电极形状控制层 2中的铝元素的含量是由下至上逐渐减 少， 下降趋势是加速下降。 其余同实施例一， 在此不再赘述。
本实施例中电极形状控制层中铝元素的含量由下至上逐渐减少， 下降 趋势呈加速下降时， 凹槽的侧面为向中间凸出的弧形坡， 沉积电极后， 电 极截面也凹槽界面相同， 电极边缘的电场分布就发生了相应的变化， 平緩 了电场分布。
实施例四：
图 6所示为实施例四所描述半导体器件的示意图。
本实施方式中电极形状控制层 2中的铝元素的含量是由下至上逐渐减 少， 下降趋势是减速下降。 其余同实施例一， 在此不再赘述。
本实施例中电极形状控制层中铝元素的含量由下至上逐渐减少， 下降 趋势呈减速下降时， 凹槽的侧面为向两侧凹陷的弧形坡， 刻蚀截面的形状 为 U形， 沉积电极后， 电极截面也为 U形， 电极边缘的电场分布就发生了 相应的变化， 平緩了电场分布。
实施例五：
图 7所示为实施例五所描述半导体器件的示意图。
本实施例中电极形状控制层 2中的铝元素的含量是由下至上先线性减 速再保持不变。 其余同实施例一， 在此不再赘述。
本实施例中电极形状控制层中铝元素的含量先线性减速再保持不变， 槽在线性减速部分为梯形， 保持不变的部分为长方形， 刻蚀截面的形状 上方为长方形， 下方为梯形， 沉积电极后， 电极截面与刻蚀截面相同。
实施例六：
图 8所示为实施例六所描述半导体器件的示意图。
本实施例中电极形状控制层 2中的铝元素的含量是由下至上先减速下 降再保持不变。 其余同实施例一， 在此不再赘述。 本实施例中电极形状控制层中铝元素的含量先减速下降再保持不变， 凹槽在减速下降部分为 u形， 保持不变的部分为长方形， 刻蚀截面的形状 上方为长方形， 下方为 u形， 沉积电极后， 电极截面与刻蚀截面相同。
实施例七：
图 9所示为实施例七所描述半导体器件的示意图。
本实施方式中半导体器件有源区为氮化物高电子迁移率晶体管， 在任 意一种基板 11上生长的成核层 12,在成核层 12上生长的氮化物緩沖层 13 , 在氮化物緩沖层 13上生长的氮化物沟道层 14, 在氮化物沟道层 14上生长 的氮化物势垒层 15, 在氮化物势垒层 15上生长的氮化物冒层 16。
电极 51为栅电极， 电极 52和电极 53分别为欧姆接触的源极和漏极。 其中， 电极形状控制层 2中的铝元素的含量是由下至上逐渐减少， 下降趋 势是加速下降。 因此， 电极 51在电极形状控制层 2中为向中间凸出的弧形 结构。
实施例八：
图 10所示为实施例八所描述半导体器件的示意图。
本实施例中半导体器件有源区为 N沟道增强型 MOSFET, P型村底 11 上的两个高掺杂的 N+区 12和 13, 电极形状控制层 2为介质层， 其中的铝 元素的含量是由下至上逐渐减少， 下降趋势是线性下降； 电极 51为栅极， 电极 52为源极， 电极 53为漏极。
实施例九：
图 11所示为实施例九所描述半导体器件的示意图。
本实施例中半导体器件有源区为普通 CMOS 工艺制作的肖特基二极 管， P型村底 11上的 N型层 12, N型层 12中的 N+阴极层 13; 电极形状 控制层 2为介质层， 其中的铝元素的含量是由下至上逐渐减少， 下降趋势 是线性下降； 电极 51为阳极， 电极 52为阴极。
实施例十：
图 12所示为实施例十中半导体器件的示意图。
本实施例中半导体器件有源区为垂直结构的 PIN二极管，村底 11上的 半导体 N+层 12, 半导体 N+层 12上的半导体 I层 13, 半导体 I层 13上的 半导体 P+层 14; 电极形状控制层 2为介质层， 其中的铝元素的含量是由 下至上逐渐减少， 下降趋势是线性下降； 电极 51为阳极， 电极 52为阴极。
由以上实施方式可以看出， 本发明半导体器件及其制作方法在半导体 器件中有源区上采用了一种电极形状控制层， 电极形状控制层中的铝元素 的含量是随着厚度的变化而变化的， 通过控制电极形状控制层中所述元素 的含量变化， 来控制刻蚀过程中横向和纵向刻蚀速度的比例， 从而改变刻 蚀过程中的刻蚀截面形状， 达到控制电极形成过程中电极的形状， 从工艺 上实现了对多种电极形状的控制。
由于刻蚀的速度是由材料的材质来控制， 无需改变刻蚀过程中的工艺 参数， 因此控制性、 重复性好， 筒单易行。 另外， 可以实现一些特殊的形 状， 这是普通刻蚀工艺无法实现的。 通过控制电极的形状， 改变电极附近 电场强度的分布， 提高半导体器件的击穿电压和可靠性等性能。
对于本领域技术人员而言， 显然本发明不限于上述示范性实施例的细 节， 而且在不背离本发明的精神或基本特征的情况下， 能够以其他的具体 形式实现本发明。 因此， 无论从哪一点来看， 均应将实施例看作是示范性 的， 而且是非限制性的， 本发明的范围由所附权利要求而不是上述说明限 定， 因此旨在将落在权利要求的等同要件的含义和范围内的所有变化嚢括 在本发明内。 不应将权利要求中的任何附图标记视为限制所涉及的权利要 求。
此外， 应当理解， 虽然本说明书按照实施方式加以描述， 但并非每个 实施方式仅包含一个独立的技术方案， 说明书的这种叙述方式仅仅是为清 楚起见， 本领域技术人员应当将说明书作为一个整体， 各实施例中的技术 方案也可以经适当组合， 形成本领域技术人员可以理解的其他实施方式。

Claims

权 利 要 求
1、 一种半导体器件， 其特征在于， 所述半导体器件包括：
半导体器件有源区；
位于所述半导体器件有源区上的电极形状控制层， 所述电极形状控制 层中含有铝元素， 所述全部或部分电极形状控制层中铝元素的含量从半导 体器件有源区由下至上逐渐减少； 所述电极形状控制层上设有电极区， 所 槽， 所述 槽的侧面全部或部分为斜坡、 或向两侧 陷的弧形坡、 或向 中间凸出的弧形坡；
全部或部分位于所述电极区中凹槽内的电极， 所述电极形状与凹槽形 状对应设置， 所述电极底部与半导体器件有源区相接触。
2、根据权利要求 1所述的半导体器件， 其特征在于， 所述电极形状控 制层为半导体层、 第一介质层中一种或两种的组合。
3、根据权利要求 2所述的半导体器件， 其特征在于， 所述半导体器件 有源区和电极形状控制层中的半导体层为三族氮化物、硅、锗、错硅、 III-V 族化合物、 氧化物中一种或多种的组合。
4、根据权利要求 2所述的半导体器件， 其特征在于， 所述第一介质层 包括 SiN、 SiAlN、 SiAlGaN、 SiA10x、 AlMgON、 HfAlOx中一种或多种的 组合。
5、根据权利要求 2所述的半导体器件， 其特征在于， 所述电极形状控 制层为半导体层和第一介质层时， 第一介质层位于半导体层的上方， 所述 半导体层中任意一处铝元素的含量高于第一介质层中任意一处铝元素的含 量。
6、根据权利要求 1所述的半导体器件， 其特征在于， 所述全部或部分 电极形状控制层中铝元素的含量从半导体器件有源区由下至上呈线性下 降、 或加速下降、 或减速下降、 或先线性下降再保持不变、 或先减速下降 再保持不变、 或先加速下降再保持不变。
7、根据权利要求 1所述的半导体器件， 其特征在于， 所述电极形状控 制层中的 槽部分延伸至半导体器件有源区中。 8、根据权利要求 1所述的半导体器件， 其特征在于， 所述电极形状控 制层中的 槽内壁及电极形状控制层表面上全部或部分沉积有第二介质 层， 所述电极全部或部分位于所述第二介质层上。
9、根据权利要求 8所述的半导体器件， 其特征在于， 所述第二介质层 包括 A1203、 A10N、 SiN、 SiON、 Si02、 HfA10x、 Hf02中一种或多种的 组合。
10、 根据权利要求 1所述的半导体器件， 其特征在于， 所述半导体器 件包括二极管和三极管， 所述电极包括二极管的阳极和阴极以及三极管的 源极、 漏极和栅极。
11、 根据权利要求 10所述的半导体器件， 其特征在于， 所述半导体器 件有源区包括： 铝镓氮 /氮化镓异质结构成的高电子迁移率晶体管、 铝镓铟 氮 /氮化镓异质结构成的高电子迁移率晶体管、氮化铝 /氮化镓异质结构成的 高迁移率三极管、氮化镓 MOSFET、含有铟镓氮 /镓氮多量子阱结构的器件、 p型氮化物构成的发光二极管、 UV-LED、 光电探测器、 氢气产生器、 太阳 能电池、 LDMOS、 UMOSFET、 肖特基二极管或者雪崩击穿二极管。
12、 一种如权利要求 1所述的半导体器件制作方法， 其特征在于， 所 述方法包括：
51、 提供半导体器件有源区；
52、 在所述半导体器件有源区上形成电极形状控制层， 所述电极形状 控制层中含有铝元素， 所述全部或部分电极形状控制层中铝元素的含量从 半导体器件有源区由下至上逐渐减少，所述电极形状控制层上设有电极区； 极形状控制层的 槽， 所述 槽的侧面全部或部分为斜坡、 或向两侧 陷 的弧形坡、 或向中间凸出的弧形坡；
S4、 在所述电极区中凹槽内的形成电极， 所述电极全部或部分位于电 极区中凹槽内， 所述电极形状与凹槽形状对应设置， 所述电极底部与半导 体器件有源区相接触。
13、 根据权利要求 12所述的半导体器件制作方法， 其特征在于， 所述 步骤 S3和 S4具体为： 531、在所述电极形状控制层上涂上第一掩膜层， 进行光刻， 露出电极 区；
532、 刻蚀所述电极区， 形成向半导体器件有源区延伸的凹槽；
533、 去除第一掩膜层；
S41、在所述电极形状控制层上涂上第二掩膜层， 进行光刻， 露出电极 区；
S42、 沉积电极， 去除第二掩膜层， 形成电极。
14、根据权利要求 12所述的半导体器件制作方法， 其特征在于， 所述 步骤 S2 中的电极形状控制层为半导体层、 第一介质层中一种或两种的组 合，第一介质层的生长方式包括 MOCVD、 PECVD、 LPCVD、 MBE、 CVD、 或 GCIB。
15、 根据权利要求 12所述的半导体器件制作方法， 其特征在于， 所述 步骤 S4前还包括：
在所述电极形状控制层中的 槽内壁及电极形状控制层表面上全部或 部分沉积第二介质层， 第二介质层包括 A1203、 A10N、 SiN、 SiON、 Si02、 HfA10x、 Hf02中一种或多种的组合。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180151484A1 (en) * 2014-06-12 2018-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Pad Design for Reliability Enhancement in Packages
US10833031B2 (en) 2014-06-12 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311284B (zh) * 2013-06-06 2015-11-25 苏州晶湛半导体有限公司 半导体器件及其制作方法
US9812562B1 (en) * 2016-06-03 2017-11-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure, HEMT structure and method of forming the same
JP2018157141A (ja) * 2017-03-21 2018-10-04 株式会社東芝 半導体装置及び半導体装置の製造方法
CN109935630B (zh) * 2017-12-15 2021-04-23 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN112349773A (zh) * 2019-08-07 2021-02-09 苏州能讯高能半导体有限公司 一种半导体器件及其制备方法
US11424356B2 (en) * 2020-03-16 2022-08-23 Raytheon Company Transistor having resistive field plate
CN111952360B (zh) * 2020-08-19 2023-02-21 深圳方正微电子有限公司 场效应管及其制备方法
CN114551340B (zh) * 2022-01-14 2025-06-13 深圳镓芯半导体科技有限公司 第三代半导体接触窗结构及其制造方法
CN114725194B (zh) * 2022-02-17 2025-07-11 西安电子科技大学 一种基于栅下场调制的低压终端器件及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162695A (zh) * 2006-10-09 2008-04-16 西安能讯微电子有限公司 氮化镓hemt器件表面钝化及提高器件击穿电压的工艺
CN101312207A (zh) * 2007-05-21 2008-11-26 张乃千 一种增强型氮化镓hemt器件结构
CN101320750A (zh) * 2007-06-06 2008-12-10 西安能讯微电子有限公司 Hemt器件及其制造方法
CN101604704A (zh) * 2008-06-13 2009-12-16 张乃千 Hemt器件及其制造方法
CN102130158A (zh) * 2011-01-05 2011-07-20 西安电子科技大学 阶梯型凹槽栅高电子迁移率晶体管
US20120223320A1 (en) * 2011-03-04 2012-09-06 Transphorm Inc. Electrode configurations for semiconductor devices
CN103311284A (zh) * 2013-06-06 2013-09-18 苏州晶湛半导体有限公司 半导体器件及其制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235639B1 (en) 1998-11-25 2001-05-22 Micron Technology, Inc. Method of making straight wall containers and the resultant containers
KR100403454B1 (ko) * 2000-06-20 2003-11-01 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성 방법
KR20020002700A (ko) * 2000-06-30 2002-01-10 박종섭 금속 배선 형성 방법
US7238560B2 (en) * 2004-07-23 2007-07-03 Cree, Inc. Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
US7456443B2 (en) 2004-11-23 2008-11-25 Cree, Inc. Transistors having buried n-type and p-type regions beneath the source region
US7749911B2 (en) * 2004-11-30 2010-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an improved T-shaped gate structure
US7141486B1 (en) 2005-06-15 2006-11-28 Agere Systems Inc. Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures
JP2007165446A (ja) * 2005-12-12 2007-06-28 Oki Electric Ind Co Ltd 半導体素子のオーミックコンタクト構造
JP2008306083A (ja) * 2007-06-11 2008-12-18 Nec Corp Ｉｉｉ−ｖ族窒化物半導体電界効果型トランジスタおよびその製造方法
US7859021B2 (en) * 2007-08-29 2010-12-28 Sanken Electric Co., Ltd. Field-effect semiconductor device
JP2010067690A (ja) * 2008-09-09 2010-03-25 Toshiba Corp 化合物半導体装置およびその製造方法
JP5496635B2 (ja) * 2008-12-19 2014-05-21 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162695A (zh) * 2006-10-09 2008-04-16 西安能讯微电子有限公司 氮化镓hemt器件表面钝化及提高器件击穿电压的工艺
CN101312207A (zh) * 2007-05-21 2008-11-26 张乃千 一种增强型氮化镓hemt器件结构
CN101320750A (zh) * 2007-06-06 2008-12-10 西安能讯微电子有限公司 Hemt器件及其制造方法
CN101604704A (zh) * 2008-06-13 2009-12-16 张乃千 Hemt器件及其制造方法
CN102130158A (zh) * 2011-01-05 2011-07-20 西安电子科技大学 阶梯型凹槽栅高电子迁移率晶体管
US20120223320A1 (en) * 2011-03-04 2012-09-06 Transphorm Inc. Electrode configurations for semiconductor devices
CN103311284A (zh) * 2013-06-06 2013-09-18 苏州晶湛半导体有限公司 半导体器件及其制作方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180151484A1 (en) * 2014-06-12 2018-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Pad Design for Reliability Enhancement in Packages
US10756007B2 (en) * 2014-06-12 2020-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US10833031B2 (en) 2014-06-12 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US11177200B2 (en) 2014-06-12 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US11600587B2 (en) 2014-06-12 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US12581985B2 (en) 2014-06-12 2026-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages

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