WO2015016541A1 - Procédé de fabrication d'un élément à nanofils - Google Patents

Procédé de fabrication d'un élément à nanofils Download PDF

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Publication number
WO2015016541A1
WO2015016541A1 PCT/KR2014/006833 KR2014006833W WO2015016541A1 WO 2015016541 A1 WO2015016541 A1 WO 2015016541A1 KR 2014006833 W KR2014006833 W KR 2014006833W WO 2015016541 A1 WO2015016541 A1 WO 2015016541A1
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Prior art keywords
substrate
nanowire
nanowires
coating
manufacturing
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English (en)
Korean (ko)
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최경진
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UNIST Academy Industry Research Corp
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UNIST Academy Industry Research Corp
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems ; Auxiliary parts of microstructural devices or systems
    • B81B7/04—Networks or arrays of similar microstructural devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/122—Nanowire, nanosheet or nanotube semiconductor bodies oriented at angles to substrates, e.g. perpendicular to substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/123—Nanowire, nanosheet or nanotube semiconductor bodies comprising junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3418—Phosphides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3421—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3462—Nanowires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials

Definitions

  • the present invention relates to a nanowire device manufacturing method, and more particularly to a nanowire device manufacturing method for generating nanowires uniformly over the entire semiconductor wafer surface.
  • Nanowires are linear materials that are in the nanometer range in diameter and have units of hundreds of nanometers, micrometers, or larger millimeters, which are much larger in length than the diameter. The physical properties of these nanowires depend on their diameter and length.
  • the nanowires can be applied to a variety of micro devices due to their small size, and there is an advantage in that they can use optical properties indicating movement characteristics or polarization phenomena of electrons according to a specific direction. It can be used as an in-transistor, and can be applied to various chemical sensors and biosensors.
  • Nanowires are currently being widely studied in the field of nanotechnology, and are currently being applied to various fields such as optical devices such as lasers, transistors, and memory devices.
  • Current materials used in nanowires include group III-V cadmium sulfide-based group II-VI semiconductor materials such as silicon, zinc oxide and gallium nitride, which are light emitting semiconductors.
  • Current nanowire manufacturing process technology has been developed to the level that can control the length and width of nanowires, but the technology to arrange and device in a desired position on the substrate is not yet mature.
  • Conventional core / shell-type nanowire manufacturing methods include, for example, chemical vapor deposition (CVD), laser ablation, and templates.
  • CVD chemical vapor deposition
  • laser ablation laser ablation
  • templates templates
  • a nanowire made of core / shell is formed and separated from a substrate to contact one side of the shell with an electrode and remove a portion of the opposite shell.
  • a method of forming an electrode again on the exposed core portion is disclosed.
  • p-GaN and n-GaN are formed into nanowires made of cores and shells, and then formed into aligned nanowire thin films to contact electrodes on one side and etch the opposite shell to expose the p-GaN cores.
  • An electrode is formed in the film and used as a light emitting element.
  • Patent Publication No. 2004-0090524 relates to a ZnO-based nanowire having a multi-wall structure and a method of manufacturing the same, and discloses a nanowire including a core part of a ZnO nanowire and a shell part of a nitride semiconductor, a dielectric, and the like.
  • Korean Patent Laid-Open Publication No. 2009-0003840 discloses a method of manufacturing a core / shell-type nanowire in which density and position control are possible by blocking contact between a core portion and a shell portion nanowire with an insulating film having a pattern formed in advance.
  • the present invention has been made to overcome the disadvantages of the prior art as described above, it is an object of the present invention to provide a method for manufacturing a nanowire device to improve the productivity by uniformly generating nanowires for the entire surface of a single substrate.
  • the substrate preparation step of preparing a substrate for nanowire generation in the nanowire device manufacturing method for generating a nanowire over the entire substrate area, the substrate preparation step of preparing a substrate for nanowire generation; A substrate surface treatment step of immersing the prepared substrate in a polylysine solution for a predetermined time; A substrate coating step of uniformly coating As atoms on the entire surface of the substrate; And a nanowire generation step of generating an InAsP nanowire array on the coated substrate.
  • the substrate is characterized in that any one selected from silicon, a substrate coated with silicon on glass, indium stone oxide, graphite, molybdenum sulfide, copper, zinc and aluminum.
  • the substrate is immersed in the polylysine solution for 1 minute to 10 minutes.
  • the As coating in the substrate coating step is characterized in that the AsH 3 precursor is flown to the substrate by an organometallic chemical vapor deposition method.
  • the nanowires are produced by simultaneously flowing In, As, and P atom precursors by organometallic chemical vapor deposition.
  • the In, As and P atom precursors are supplied by different ratios to adjust the composition ratio of In, As and P of the nanowires.
  • the passivation layer of the InP component is formed on the surface of the nanowire so that the photo-excited electron-electron is non-luminescent due to the high concentration of surface defects present on the surface of the InAsP nanowire. And further comprising a passivation layer generating step of inhibiting the recombination mechanism.
  • the passivation layer generating step further comprises a TCO layer generation step of further forming a TCO layer for electrical connection to the nanowire ends.
  • the substrate is a p-type silicon material and the nanowires are characterized in that the n-type InAs 0.75 P 0.25 material.
  • the nanowire device manufacturing method according to the present invention is characterized in that the nanowires are produced at a uniform density in the entire area of the upper surface of the substrate of a standard size, thereby exhibiting high productivity during mass production of the device, and also having excellent physical properties. It can be used with various devices.
  • FIG. 1 is a flowchart of a method for manufacturing a nanowire device according to the present invention
  • FIG. 3 is an electron micrograph of the nanowires generated in FIG.
  • FIG. 5 is an electron micrograph of the nanowires generated in FIG.
  • FIG. 9 is a graph illustrating nanowire density distribution of each location of FIG. 6.
  • FIG. 10 is a graph of diameter distribution of nanowires according to positions of FIG. 6.
  • 15 is an electron micrograph of the nanowire manufactured by the method of the embodiment implemented as a solar cell
  • FIG. 16 is a graph illustrating current-voltage characteristics of FIG. 15;
  • FIG. 17 is a graph of the abnormality coefficient and the rectification rate value of FIG. 15.
  • FIG. 17 is a graph of the abnormality coefficient and the rectification rate value of FIG. 15.
  • Nanowire device manufacturing method including a substrate preparation step (S1), substrate surface treatment step (S2), substrate coating step (S3) and nanowire generation step (S4) It is composed.
  • the substrate preparation step S1 is a step of preparing a substrate for generating nanowires.
  • the substrate is not particularly limited, but may be any conductive material such as silicon, a substrate coated with silicon on glass, indium stone oxide, graphite, molybdenum sulfide, copper, zinc, aluminum, etc., in order to be used as an electrode on one side. Silicon doped with n-type or p-type is suitable.
  • the process proceeds in the same manner as usual pre-substrate treatment, such as a cleaning operation for removing impurities on the surface.
  • the substrate surface treatment step S2 the surface of the substrate prepared through the substrate preparation step S1 is separately processed.
  • the substrate is immersed in a poly-L-lysine (PLL) solution for a predetermined time.
  • PLL poly-L-lysine
  • a thin polyelectrolyte is formed on the surface of the substrate by the immersion liquid so that the surface of the substrate has a '+' charge.
  • the immersion time is suitably 1 to 10 minutes. If the immersion time is less than 1 minute, the '+' charge generation of the substrate surface is not complete, if more than 10 minutes, productivity is deteriorated.
  • the substrate surface treated by the substrate surface treatment step S2 is subjected to a substrate coating step S3.
  • the substrate coating step (S3) is a metal organic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Deposition) PLL-treated substrate after loading the polylysine treated substrate into the MOCVD chamber, the hydrogen gas inside the chamber 15 L / By flowing at a flow rate of min, the internal pressure is maintained at 10 mbar to 100 mbar, while the substrate temperature is maintained at 570 ° C to 630 ° C while flowing a '-' charged AsH 3 precursor over the substrate for 1 minute.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • step S3 As atoms are uniformly coated on the entire surface of the substrate due to the electrostatic reaction between the substrate surface of the '+' charge and the AsH 3 of the '-' charge.
  • the substrate surface is coated with As atoms in the substrate coating step (S3), when In and P atom precursors are simultaneously flown onto the substrate surface using the same organometallic chemical vapor deposition method, a uniform InAsP nanowire array is formed on the entire surface of the substrate. do.
  • InAs y P 1-y nanowires with the modulated composition of As and P atoms In, As, and P precursors, trimethylindium (TMIn), arsine (AsH 3 ), and phosphine (PH 3 ), respectively, were 2x.
  • Flow was 10 ⁇ 5 , 2.2 ⁇ 10 ⁇ 4 , 4.5 ⁇ 10 ⁇ 3 to 8.4 ⁇ 10 ⁇ 2 mol / min, and the chamber pressure and temperature were kept the same as in step S3.
  • the prepared 2 inch diameter silicon substrate was immersed in the PLL solution for 3 minutes and immediately loaded into the MOCVD chamber, and then the internal pressure was maintained at 10 mbar to 100 mbar and the substrate temperature was maintained at 570 ° C. to 630 ° C.
  • P precursors were added under the same process conditions, and growth time was maintained for 5 to 60 minutes to generate InAs y P 1-y nanowires.
  • FIG. 2 is an external shape of a substrate manufactured by the method of Comparative Example, and SEM pictures of points A and B are shown in FIG. 3.
  • the nanowires produced in the comparative example show a difference in density between the points A and B.
  • both the points A and B have high nanowire densities as shown in FIG. 5. It can also be confirmed that the same density was generated at both points.
  • the uniformity of the nanowires produced on the other silicon substrates prepared by the examples was analyzed.
  • FIG. 6 is an external optical photograph of a silicon substrate manufactured according to an embodiment
  • FIG. 7 is an SEM photograph of nanowires taken in a 45 degree direction. As shown in FIG. 7, the nanowires were grown perpendicular to the substrate.
  • FIG. 9 is a graph showing the density of points A, B, and C of FIG. 6 to confirm that the density of the nanowires is uniform regardless of the position. As shown in FIG. 10, the diameter of the nanowires is also irrelevant to the position. Uniformity was confirmed.
  • an InP passivation layer was formed on the surface of the nanowire to perform photoluminescence (PL) analysis. As shown in FIG. 11, the photoluminescence spectral intensity increased by 50 times. There are numerous surface states on the surface of nanowires without a passivation layer, so that photo-excited electron-electrons do not luminescently recombine, but are surface-bonded. If passivation is spatially separated from the surface defects by InP, there is a reason that non-luminescent recombination is reduced.
  • FIG. 13 is a graph analyzing the longitudinal composition of nanowires using energy-dispersive X-ray spectroscopy (EDX).
  • EDX energy-dispersive X-ray spectroscopy
  • FIG. 14 is a graph showing nanowire XRD spectra modulated with As and P atom compositions. As the P composition was increased in pure InP, it was confirmed that the peak peak value of InAs y P 1-y nanowires having a zinc brand (Zincblende) structure gradually increased from 25.3 degrees to 25.6 degrees.
  • a heterojunction solar cell was prepared by forming a TCO layer on the p-type silicon substrate and n-type InAs 0.75 P 0.25 nanowires prepared by the method of Example.
  • FIG. 15 is an SEM image of a manufactured solar cell
  • FIG. 16 is a graph of current-voltage characteristics of the solar cell measured at room temperature
  • FIG. 17 is an ideality factor and rectification rate (obtained from a current-voltage characteristic graph). rectifying ratio chart.
  • the p-type silicon substrate / n-type n-type InAs 0.75 P 0.25 nanowire heterojunction structure implemented in this example shows superior characteristics compared to the heterojunction structure fabricated by homojunction nanowires or bonding processes. .

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Silicon Compounds (AREA)

Abstract

La présente invention a pour objet un procédé de fabrication d'un élément à nanofils. Ledit procédé améliore la productivité en formant des nanofils de manière homogène sur toute une surface d'un substrat unique. A cette fin, la présente invention concerne le procédé de fabrication de l'élément à nanofils. Ledit procédé permet de former des nanofils sur toute la surface de l'ensemble d'un substrat et comprend : une étape de préparation du substrat consistant à préparer le substrat pour former les nanofils ; une étape de traitement de surface du substrat consistant à tremper le substrat préparé dans une solution de polylysine pendant une durée spécifique ; une étape de revêtement du substrat consistant à déposer de manière homogène des atomes As sur toute la surface du substrat ; et une étape de formation des nanofils consistant à former un alignement de nanofils InAsP sur le substrat qui a été recouvert.
PCT/KR2014/006833 2013-07-31 2014-07-25 Procédé de fabrication d'un élément à nanofils Ceased WO2015016541A1 (fr)

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KR1020130091107A KR101431818B1 (ko) 2013-07-31 2013-07-31 나노와이어 소자 제조 방법
KR10-2013-0091107 2013-07-31

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111755600A (zh) * 2020-06-17 2020-10-09 北京航空航天大学 一种基于复合纳米线网络结构的忆阻器

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
DAN DALACU ET AL.: "Selective-area vapor-liquid-solid growth of tunable InAsP quantum dots in nanowires", APPL. PHYS. LETT., vol. 98, 2011, pages 251101, XP012141117, DOI: doi:10.1063/1.3600777 *
JOSEF A. CZABAN ET AL.: "GaAs Core-Shell Nanowires for Photovoltaic Applications", NANO LETT., vol. 9, no. 1, 2009, pages 148 - 154, XP055152467, DOI: doi:10.1021/nl802700u *
MAARTEN H. M. VAN WEERT ET AL.: "Selective Excitation and Detection of Spin States in a Single Nanowire Quantum Dot", NANO LETT., vol. 9, no. 5, 2009, pages 1989 - 1993 *
MARIA TCHEMYCHEVA ET AL.: "Growth and Characterization of InP Nanowires with InAsP Insertions", NANO LETT., vol. 7, no. 6, 2007, pages 1500 - 1504 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111755600A (zh) * 2020-06-17 2020-10-09 北京航空航天大学 一种基于复合纳米线网络结构的忆阻器

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