WO2015074621A1 - Procédé de gravure pour réguler un effet de micro-chargement de profondeur de tranchées peu profondes - Google Patents

Procédé de gravure pour réguler un effet de micro-chargement de profondeur de tranchées peu profondes Download PDF

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Publication number
WO2015074621A1
WO2015074621A1 PCT/CN2014/092156 CN2014092156W WO2015074621A1 WO 2015074621 A1 WO2015074621 A1 WO 2015074621A1 CN 2014092156 W CN2014092156 W CN 2014092156W WO 2015074621 A1 WO2015074621 A1 WO 2015074621A1
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wafer
etching
polymer
film layer
gas
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PCT/CN2014/092156
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English (en)
Chinese (zh)
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符雅丽
李国荣
杨盟
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Beijing NMC Co Ltd
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Beijing NMC Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • the present invention relates to the field of semiconductor device manufacturing, and more particularly to an etching method for controlling the shallow micro-load effect of shallow trenches.
  • the micro load effect is as shown in FIG. 1 , wherein in the wafer 100, the photoresist 101, the mask layer 102, and the silicon oxide layer are sequentially in order from top to bottom. 103, the base silicon 104, and the wafer 100 further includes a small opening area 110 and a large opening area 120.
  • An etching method for controlling shallow trench depth micro-loading effect includes the following steps: mask etching a wafer entering a process chamber until an opening on the wafer contacts Substrate silicon to the wafer; depositing a deposition gas into the process chamber to perform a deposition reaction, depositing a polymer-like film layer on the wafer that blocks the subsequent etching; The inert gas is introduced into the process chamber, and the polymer film layer is processed under plasma excitation conditions; the wafer is subjected to a shallow trench etching process to a predetermined depth.
  • the polymer-like film layer which blocks the subsequent etching is a polymer-like film layer having carbon and hydrogen components.
  • the polymer-like film layer which blocks the subsequent etching is a SiO 2 -based film layer.
  • the polymer is from 10 angstroms to 300 angstroms.
  • the method further comprises the step of: removing the photoresist remaining in the wafer by ashing.
  • the deposition gas is CH 4 or a combination of SiH 4 and O 2 .
  • the inert gas is Ar and/or He.
  • the thickness of the polymer-like film layer is controlled by the deposition time.
  • the inert gas is introduced into the process chamber, and the polymer film layer is treated under plasma excitation conditions, including the steps of: introducing an inert gas into the process chamber; Treating the polymer film layer under excitation conditions;
  • the point detection method captures the moment when the small-sized open area of the wafer exposes the base silicon, ends the current step, and completes the step of processing the polymer-like film layer.
  • the process condition of performing a mask etching process on the wafer entering the process chamber until the opening on the wafer contacts the base silicon of the wafer is: source power It is 400-700W, the bias power is 100-300W, the air pressure is 3mt ⁇ 10mt, the etching time is 10 ⁇ 40s per step, the main gas is CF 4 and CH 2 F 2 , the flow rate is 50-350sccm, and the auxiliary gas is O. 2 , Ar, He, the auxiliary gas flow rate other than oxygen is 50 ⁇ 150sccm, oxygen flow rate is 5 ⁇ 30scc;
  • the process condition of the process step of depositing a deposition gas into the process chamber to perform a deposition reaction and depositing a polymer-like film layer for blocking the subsequent etching on the wafer is: source power 100 to 1000W, bias power is 0W ⁇ 50W, deposition gas flow is 10 ⁇ 500sccm, process pressure is 1 ⁇ 100mT, process time is 10 ⁇ 60s;
  • the process conditions for introducing the inert gas into the process chamber and treating the polymer film layer under plasma excitation conditions are: source power is 100-1000 W, bias power is 50 W ⁇ 300W, Ar flow rate is 10 ⁇ 500sccm, He flow is 10 ⁇ 500sccm, process pressure is 1 ⁇ 100mT, process time is 10-60s;
  • the process conditions for performing the shallow trench etching process on the wafer to a predetermined depth are: source power is 700-1200 W, bias power is 100-200 W, air pressure is 10 mt ⁇ 25 mt, etching time It is 70 to 100 s, the main gas is HBr, the flow rate is 300-500 sccm, and the auxiliary gas is at least one of Cl 2 , NF 3 , SF 6 , N 2 , O 2 , and HeO 2 , and the flow rate is 5-50 sccm.
  • the process conditions of the process step of depositing a deposition gas into the process chamber, performing a deposition reaction, and depositing a polymer-like film layer for blocking the subsequent etching on the wafer are:
  • the source power is 300-700W
  • the bias power is 0W
  • the deposition gas flow rate is 100-200sccm
  • the process gas pressure is 10-30mT
  • the process time is 10-30s;
  • the process condition of the process step of injecting an inert gas into the process chamber to treat the polymer-like film layer under plasma excitation conditions is: source power is 300 to 700 W, bias power is 100 W to 200 W, Ar flow rate is 100 to 200 sccm, He flow rate is 100 to 200 sccm, process gas pressure is 5 to 20 mT, and process time is 10-20 s.
  • the process conditions of the process step of removing the photoresist from the wafer by the ashing process are: source power is 700-1200 W, bias power is 0 W, air pressure is 10 mt to 30 mt, and etching time is 80 ⁇ . At 120 s, the gas is O 2 and the flow rate is 200 to 500 sccm.
  • the invention provides an etching method for controlling the micro-load effect of shallow trench depth, which can be used to form a trench by adding a deposition step of a polymer-like film layer and a modification step of the deposited polymer-like film layer. Etching the opposite effect of the microloading effect effectively reduces or eliminates the etch depth microloading effect in the trench etch.
  • the etching method for controlling the micro-load effect of shallow trench depth provided by the invention does not need to add an additional process, is simple in operation, and has a short time; and can be adjusted and controlled by process parameters such as time for specific equipment processing, and has high flexibility. . At the same time, this method can help balance the difference in critical dimensions of different opening areas of the wafer to a certain extent.
  • FIG. 1 is a schematic view of a wafer after conventional trench etching
  • FIG. 2 is a flow chart of a specific embodiment of an etching method for controlling a micro-load effect of a shallow trench depth according to the present invention
  • step S100 is performed by the method shown in FIG. 2;
  • step S200 is performed by the method shown in FIG. 2;
  • FIG. 5 is a schematic structural view of a wafer when step S300 is performed by using the method shown in FIG. 2;
  • step S400 is performed by the method shown in FIG. 2;
  • FIG. 7 is a flow chart of another embodiment of an etching method for controlling shallow trench depth microloading effects of the present invention.
  • the etching method for controlling the shallow trench depth micro-load effect provided by the embodiment of the present invention, as described in FIG. 2, includes the following steps:
  • the mask layer 102 of the wafer 100 entering the process chamber is etched, and the opening on the wafer 100 is etched to contact the base silicon to complete the etching of the mask layer 100.
  • the wafer 100 from top to bottom, there are a photoresist layer 101, a mask layer 102, a silicon oxide layer 103, and a base silicon 104, wherein the mask layer 102 is a SIN type hard mask layer. .
  • the wafer 100 further includes a small opening area 110 and a large opening area 120.
  • a deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer that blocks the subsequent etching is deposited on the wafer.
  • a deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer that blocks the subsequent etching is deposited on the wafer.
  • a deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer that blocks the subsequent etching is deposited on the wafer.
  • a deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer that blocks the subsequent etching is deposited on the wafer.
  • the total contact area of the small opening area 110 ie, all the small opening areas in the small opening area 110 and the large opening area 120 of the same opening area during the deposition of the polymer-like film layer 105 (ie, all small opening areas)
  • the sum of the areas of the bottom of the layer 110 and the sidewalls of the polymer-depositable polymer film layer 105 is greater than the total contact area of the large opening region 120 (i.e., the bottom of the large opening region 120 and the sidewalls of the depositable polymer)
  • the sum of the areas of the film layers 105 causes
  • the thickness of the polymer-like film layer 105 deposited in the large opening region 120 is greater than the thickness of the polymer-like film layer 105 deposited by the small opening region 110.
  • the deposition does not occur only at the bottom of the opening.
  • the sidewalls of the opening are also deposited with a polymer film layer 105 of different thickness.
  • the larger the opening area the side wall thereof The thicker the deposited polymer-like film layer 105 will be. This difference also balances the loading effect of the opening size of the trench etching process to some extent.
  • an inert gas is introduced into the process chamber, and the polymer-like film layer is treated under plasma excitation conditions.
  • the polymer-like film layer 105 at all positions of the wafer 100 is thinned or disappears.
  • the treatment is to modify the polymer-like film layer 105 to make the film layer thin or disappear. It is primarily a physical bombardment where the rate of consumption of the deposited polymer-like film layer 105 is approximately the same at different openings.
  • the thickness of the polymer-like film layer 105 deposited in the large opening region 120 is still greater than the thickness of the polymer-like film layer 105 deposited in the small opening region 110. And after the treatment of this step, the thickness of the deposited deposit is proportional to the size of the opening.
  • a small amount of other auxiliary gas may be added in the step for processing, such as O 2 , N 2 , H 2 and the like.
  • the preset depth is an etch depth set according to actual needs of the semiconductor device. It should be noted here that due to the blocking of the polymer-like film layer 105, the etching speed of the large opening region 120 may be slowed relative to the original state, so that the small opening region 110 and the large opening region 120 may be etched. The depth is the same or similar, as shown in Figure 6.
  • the etching method for controlling the micro-load effect of the shallow trench depth provided by the embodiment of the present invention can be performed by adding a deposition step of the polymer-like film layer and a step of modifying the deposited layer.
  • the etching method for controlling the shallow micro-load effect of the shallow trench provided by the embodiment of the invention does not need to add an additional process, is simple in operation, has a short time, and can be adjusted and controlled by time and other process parameters for specific equipment processing, and flexibility. Big. At the same time, this method can help balance the difference in key dimensions of different opening areas of the wafer to a certain extent.
  • the polymer-like film layer that blocks the subsequent etching is a polymer-like film layer having carbon and hydrogen components.
  • the polymer-like film layer 105 whose main component is carbon and hydrogen is equivalent to a photoresist, which acts as a barrier to subsequent etching, thereby equivalent to a slowing of the etching rate, and a polymer film deposited due to the large opening region 120.
  • the thickness of the layer is large, so the effect of slowing down the etching speed of the large opening region 120 is more pronounced.
  • the polymer-like film layer which has a certain blocking effect on the subsequent etching is a SiO 2 -based film layer.
  • the SiO 2 -type film layer can also play a role in relatively slowing the etching speed of the large opening region 120.
  • the polymer-like film layer 105 has a thickness of 10 angstroms to 300 angstroms.
  • the etching method for controlling the shallow trench depth micro-loading effect further includes the following steps: S500, removing the photoresist remaining in the wafer by ashing.
  • the deposition gas is CH 4 or a combination of SiH 4 and O 2 .
  • the gas CH 4 is used for deposition, a polymer-like film layer mainly composed of carbon and hydrogen can be formed.
  • a combination of SiH 4 and O 2 gas is used as a deposition gas, a SiO 2 -type film layer can be formed, which can be relatively reduced. The effect of the etch rate in the slow open area.
  • other gas combinations which can produce a similar deposited film layer are also applicable in other embodiments of the invention, such as other carbon and hydrogen containing gases.
  • the inert gas is Ar and/or He.
  • the thickness of the polymer-like film layer is controlled by deposition time.
  • the deposition time of the polymer-like polymer can be obtained through preliminary experiments.
  • the TEM slice analysis can be performed after the trench etching is completed by presetting a short deposition time to verify the difference in depth at different opening sizes. If the difference is still large, the deposition time needs to be increased. This is repeated until the depth difference is reduced to an acceptable range. This is a simple process test that can be directly performed by a person skilled in the art according to the description, and will not be described in detail herein.
  • the thickness of the polymer-like film layer can also be adjusted and controlled by other parameters of the processing process or a combination of parameters, such as source power, gas pressure, and gas flow rate.
  • the treatment of the polymer-like polymer can also be controlled by other parameters or combinations of parameters of the processing process, such as process time, source power, gas pressure, and gas flow rate.
  • step S300 includes the following steps:
  • the embodiment of the invention can accurately grasp the time of the polymer-like treatment, make the process processing more accurate, and at the same time reduce the cost and improve the production efficiency.
  • the etching process for mask etching of a wafer entering a process chamber until the opening on the wafer contacts the base silicon of the wafer
  • the process conditions of the step are: source power is 400-700 W, bias power is 100-300 W, air pressure is 3 mt to 10 mt, etching time is 10-40 s, and main gas is CF 4 and CH. 2 F 2 , the flow rate is 50-350 sccm, the auxiliary gas is O 2 , Ar, He, the auxiliary gas flow rate other than oxygen is 50-150 sccm, and the oxygen flow rate is 5-30 sccm.
  • Performing a process step of depositing a deposition gas into the process chamber to perform a deposition reaction, depositing a polymer-like film layer blocking the subsequent etching on the wafer ie, step S200
  • the process conditions are: the source power is 100-1000W, and the bias power is 0W-50W.
  • the deposition gas flow rate is 10 to 500 sccm, the process gas pressure is 1 to 100 mT, and the process time is 10 to 60 s.
  • step S300 The process step of introducing an inert gas into the process chamber to process the polymer-like film layer under plasma excitation conditions (ie, step S300) is: source power is 100-1000W
  • the bias power is 50W to 300W
  • the Ar flow rate is 10 to 500 sccm
  • the He flow rate is 10 to 500 sccm
  • the process gas pressure is 1 to 100 mT
  • the process time is 10-60 s.
  • step S400 The process conditions for performing the shallow trench etching process on the wafer to a predetermined depth (ie, step S400) are: source power is 700-1200 W, bias power is 100-200 W, and air pressure is 10 mt. ⁇ 25mt, etching time is 70-100s, main gas is HBr, flow rate is 300-500sccm, auxiliary gas is at least one of Cl 2 , NF 3 , SF 6 , N 2 , O 2 , HeO 2 , flow rate is 5-50 sccm.
  • the deposition gas is introduced into the process chamber to perform a deposition reaction, and a polymer-like film layer for blocking subsequent etching is deposited on the wafer.
  • the process conditions of the process step are: source power is 300-700 W, bias power is 0 W, deposition gas flow is 100-200 sccm, process gas pressure is 10-30 mT, and process time is 10-30 s.
  • the process condition that the inert gas is introduced into the process chamber to process the polymer-like film layer under plasma excitation conditions is: source power is 300-700W
  • the bias power is 100 W to 200 W
  • the Ar flow rate is 100 to 200 sccm
  • the He flow rate is 100 to 200 sccm
  • the process gas pressure is 5 to 20 mT
  • the process time is 10-20 s.
  • the process condition of removing the photoresist ashing removal of the wafer is as follows: the source power is 700-1200 W, and the bias power is 0W, the gas pressure is 10 mt to 30 mt, the etching time is 80 to 120 s, the gas is oxygen, and the flow rate is 200 to 500 sccm.

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Abstract

L'invention porte sur un procédé de gravure qui permet de réguler l'effet de micro-chargement de la profondeur de tranchées peu profondes et qui comprend les étapes suivantes : la gravure des couches de masque sur la tranche de semi-conducteur entrant dans une chambre de traitement, jusqu'à ce que les ouvertures sur la tranche de semi-conducteur soient en contact avec le substrat Si de la tranche de semi-conducteur ; l'alimentation en gaz de dépôt dans la chambre de traitement pour effectuer une réaction de dépôt, afin de déposer une couche de film de type polymère empêchant une gravure d'épaisseur ; l'alimentation en gaz inertes dans la chambre de traitement et le traitement du film de type polymère dans la condition d'excitation de plasma ; l'exécution d'un processus de gravure de tranchée peu profonde sur la tranche de semi-conducteur jusqu'à la profondeur prédéterminée. Ceci peut efficacement réduire ou éliminer l'effet de micro-chargement de profondeur de gravure pendant la gravure des tranchées, ne nécessite aucun processus supplémentaire avec un fonctionnement simple et un laps de temps écoulé relativement court, et peut en outre être ajusté avec une grande flexibilité par régulation du paramètre de traitement, tel que la durée, pour un traitement d'équipement spécial.
PCT/CN2014/092156 2013-11-25 2014-11-25 Procédé de gravure pour réguler un effet de micro-chargement de profondeur de tranchées peu profondes Ceased WO2015074621A1 (fr)

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CN201310606952.3A CN104658882B (zh) 2013-11-25 2013-11-25 控制浅沟槽深度微负载效应的刻蚀方法
CN201310606952.3 2013-11-25

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CN102810470A (zh) * 2011-05-29 2012-12-05 南亚科技股份有限公司 降低微负载效应的方法

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CN110911344A (zh) * 2018-09-14 2020-03-24 长鑫存储技术有限公司 半导体衬底浅沟槽制作方法及半导体衬底浅沟槽结构
CN110911344B (zh) * 2018-09-14 2023-09-05 长鑫存储技术有限公司 半导体衬底浅沟槽制作方法及半导体衬底浅沟槽结构
US11430795B2 (en) 2020-07-24 2022-08-30 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
CN113451126A (zh) * 2021-07-07 2021-09-28 北京北方华创微电子装备有限公司 晶圆刻蚀方法
CN113451126B (zh) * 2021-07-07 2024-02-27 北京北方华创微电子装备有限公司 晶圆刻蚀方法
CN114914156A (zh) * 2022-06-30 2022-08-16 北京北方华创微电子装备有限公司 刻蚀方法
CN119596461A (zh) * 2024-12-02 2025-03-11 浙江大学绍兴研究院 一种高垂直度bto波导的制备方法

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