WO2015149653A1 - Circuit de réglage de coefficient d'utilisation d'horloge et générateur de signal d'horloge multiphasé - Google Patents

Circuit de réglage de coefficient d'utilisation d'horloge et générateur de signal d'horloge multiphasé Download PDF

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Publication number
WO2015149653A1
WO2015149653A1 PCT/CN2015/075206 CN2015075206W WO2015149653A1 WO 2015149653 A1 WO2015149653 A1 WO 2015149653A1 CN 2015075206 W CN2015075206 W CN 2015075206W WO 2015149653 A1 WO2015149653 A1 WO 2015149653A1
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Prior art keywords
clock
clock signal
delay
duty ratio
output
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English (en)
Chinese (zh)
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陈中盟
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ZTE Corp
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ZTE Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses

Definitions

  • the present invention relates to clock adjustment techniques, and more particularly to a clock duty cycle adjustment circuit and a multi-phase clock generator.
  • DDR Double Rate Synchronous Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • the first type uses a negative feedback pulse adjustment circuit to adjust the duty cycle of the output clock, and converts the duty cycle information of the output clock into a current or voltage to adjust the slew rate of the clock in the loop ( The slew rate), which in turn adjusts the duty cycle of the clock signal.
  • the slew rate the circuit block diagram is shown in FIG. 1.
  • the patent duty cycle adjustment process is: converting the duty ratio of DRIVER OUT (output clock after duty cycle adjustment) into voltage DET OUT by using an RC filter circuit (filter)
  • the output voltage that is, the voltage at which the filter converts the output clock
  • DET OUT is not equal to the operating voltage VDD/2
  • the voltage error between the two is converted by the error amplifier 30 into Control voltage CTL
  • CTL is configured to adjust the gate voltage of PMOS12 and NMOS18, change the slew rate of DRIVER IN (clock after input clock CLK_IN is adjusted by slew rate), change slew rate
  • the slope of the rising and falling edges is changed to adjust the duty cycle of the signal.
  • a clock signal and an inverted clock signal having the same phase but different phase changes are mixed by a phase mixer to cancel the phase change, thereby Generate a roughly corrected clock signal, because the linearity of the mixer is low; the duty cycle accuracy of the output clock of the mixer is poor.
  • the output clock of the first-stage DCC to the mixer is further increased. Adjustment. Specifically, as shown in FIG. 2, the duty cycle adjustment process of the patent is: obtaining clocks clk1 and clk2 with opposite phases through two delay locked loops (DLLs), and then obtaining a rough sketch through the phase mixer.
  • DLLs delay locked loops
  • Adjust the duty cycle signal clk_hpg then add a DCC LOOP to further adjust the duty cycle of clk_hpg; DCC LOOP adjusts the output clock voltage of the differential amplifier in DCC by converting the duty cycle of clk_out into a control voltage.
  • the slew rate which adjusts the duty cycle.
  • the first method converting the duty ratio information into current or voltage to adjust the slew rate of the clock in the loop and adjusting the clock duty ratio, which may cause dynamics due to slew rate Increased power consumption;
  • the second method uses a phase mixer to adjust the duty cycle.
  • the linearity of the mixer also has a large effect on the clock duty cycle, which causes a duty cycle error, resulting in a clock duty cycle. Adjustment is not accurate.
  • the main technical problem to be solved by the embodiments of the present invention is to provide a clock duty ratio adjustment circuit and a multi-phase clock generator, which can adjust the duty ratio of the clock signal, and can save dynamic power consumption and improve the clock duty ratio. Adjustment accuracy.
  • an embodiment of the present invention provides a clock duty cycle adjustment circuit, including: a clock delay processing module and a clock adjustment module;
  • the clock delay processing module is configured to delay the input clock signal of the clock duty ratio adjusting circuit to obtain a delayed clock signal, and obtain an output clock signal of the clock duty ratio adjusting circuit, according to the The duty cycle of the output clock signal adjusts the input clock signal with a delay between the delayed clock signals;
  • the clock adjustment module is configured to adjust the duty ratio of the input clock signal according to the delayed clock signal to obtain the output clock signal.
  • the clock adjustment module is further configured to detect a rising edge of the input clock signal and the delayed clock signal, and output a rising edge when detecting a rising edge of the input clock signal, when detecting The falling edge of the falling edge of the delayed clock signal is output.
  • the clock delay processing module is further configured to reduce a delay between the input clock signal and the delayed clock signal when a duty ratio of the output clock signal is greater than a first threshold. A delay between the input clock signal and the delayed clock signal is increased when a duty cycle of the output clock signal is less than the first threshold.
  • the clock delay processing module includes: a clock delay sub-module and a clock feedback sub-module;
  • the clock feedback submodule is configured to acquire the output clock signal, and convert a duty ratio of the output clock signal into a control voltage
  • the clock delay sub-module is configured to delay the input clock signal to obtain the delayed clock signal, and adjust a delay between the input clock signal and the delayed clock signal according to the control voltage Time.
  • the clock feedback submodule is further configured to convert a duty ratio of the output clock signal into a changed control voltage
  • the clock delay sub-module is further configured to adjust a delay between the input clock signal and the delayed clock signal according to the change of the control voltage.
  • the clock feedback submodule is further configured to convert the duty of the output clock signal to a control voltage in a reduced state when the duty ratio of the output clock signal is greater than a first threshold; When the space ratio is less than the first threshold, it is converted into a control voltage in an increased state;
  • the clock delay sub-module is further configured to reduce a delay between the input clock signal and the delayed clock signal when the control voltage is in a reduced state; when the control voltage is in an increased state The delay between the input clock signal and the delayed clock signal is increased.
  • the clock feedback sub-module is a charge pump, and the charge pump is composed of a current rudder phase detector and a low-pass filter in series;
  • the current rudder phase detector is configured to convert a duty ratio of the output clock signal into a control voltage, and charge and discharge the low-pass filter by the control voltage to obtain a control voltage in an increasing or decreasing state.
  • the clock delay sub-module is a voltage-controlled delay device, and the clock adjustment module is a rising edge detector.
  • an embodiment of the present invention further provides a multi-phase clock generator, including a DLL (Delay Locked Loop) circuit and at least two clock duty adjustment circuits described above;
  • DLL Delay Locked Loop
  • the DLL circuit is configured to generate at least two clock signals of different phases
  • the at least two clock duty ratio adjusting circuits are configured to respectively perform duty ratio adjustment on at least two clock signals of different phases; the number of the clock duty ratio adjusting circuits and the clock signal generated by the DLL circuit The phase type corresponds.
  • the multi-phase clock generator further includes a control circuit, and the control circuit is configured to control whether the clock duty ratio adjustment circuit operates.
  • the clock duty ratio adjusting circuit and the multi-phase clock generator configured a clock delay processing module to delay the input clock signal of the clock duty ratio adjusting circuit to obtain a delayed clock. And a module for obtaining an output clock signal of the clock duty cycle adjustment circuit, adjusting a delay between the input clock signal and the delayed clock signal according to a duty ratio of the output clock signal;
  • the clock adjustment module is configured to adjust a duty cycle of the input clock signal according to the delayed clock signal to obtain the output clock
  • the module of the signal is such that the embodiment of the present invention can adjust the input clock signal by using the delayed clock signal of the input clock signal, and dynamically adjust the delayed clock signal by using the duty ratio of the output clock signal to finally obtain the required duty
  • the adjustment circuit described in the embodiment of the present invention does not need to convert the clock duty ratio information into a slew rate to adjust the output clock duty ratio, thereby avoiding the slew rate.
  • the problem of increased dynamic power consumption is achieved, thereby achieving a time-saving
  • FIG. 1 is a schematic structural diagram of a clock duty ratio adjustment circuit in the prior art
  • FIG. 2 is a schematic structural diagram of another clock duty ratio adjustment circuit in the prior art
  • FIG. 3 is a schematic structural diagram of a first clock duty ratio adjustment circuit according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic structural diagram of a second clock duty ratio adjusting circuit according to Embodiment 1 of the present invention.
  • FIG. 5 is a timing diagram of a rising edge detector according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural diagram of a third clock duty ratio adjusting circuit according to Embodiment 1 of the present invention.
  • FIG. 7 is a schematic structural diagram of a clock duty ratio adjustment circuit according to Embodiment 2 of the present invention.
  • FIG. 8 is a schematic structural diagram of a charge pump according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic structural diagram of a first multi-phase clock generator according to Embodiment 3 of the present invention.
  • FIG. 10 is a schematic structural diagram of a second multi-phase clock generator according to Embodiment 3 of the present invention.
  • FIG. 11 is a schematic structural diagram of a third multi-phase clock generator according to Embodiment 3 of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the embodiment provides a clock duty ratio adjustment circuit, including: a clock delay processing module and a clock adjustment module;
  • the clock delay processing module is configured to delay the input clock signal CLK_IN of the clock duty ratio adjusting circuit to obtain a delayed clock signal CLK_IN_DELAY, and obtain an output clock signal of the clock duty ratio adjusting circuit, according to The duty ratio of the output clock signal CLK_OUT adjusts a delay Tdealy between the input clock signal and the delayed clock signal;
  • the clock adjustment module is configured to adjust the duty ratio of the input clock signal CLK_IN according to the delayed clock signal CLK_IN_DELAY to obtain the output clock signal CLK_OUT.
  • the main idea of the clock duty ratio adjusting circuit in this embodiment is to adjust the duty ratio of the input clock signal by inputting the delayed clock signal of the clock signal, and dynamically adjust the input clock signal and the delay by using the duty ratio of the outputted output clock signal.
  • the delay between the clock signals finally forms an output clock signal with a preset duty cycle that forms a dynamic balance of the entire adjustment circuit.
  • an output clock signal with a duty ratio of 50% can be obtained.
  • the duty ratio of the output clock signal of the adjustment circuit is 50%.
  • the delay between the input clock signal and the delayed clock signal is not adjusted, and the delay is adjusted if the other duty ratio is not equal to 50%.
  • the clock duty cycle circuit can generate output clock signals of different duty ratios according to different settings.
  • the clock duty ratio adjustment circuit of this embodiment does not need to convert the clock duty ratio information into a slew rate to adjust the output clock duty ratio, thereby achieving a direct connection between reducing the power supply high level and the current.
  • the time effect saves dynamic power and avoids the duty cycle error due to the uncertainty of the accuracy of the mixer.
  • the manner in which the clock adjustment module adjusts the duty ratio of the clock signal in the clock duty adjustment circuit is to adjust the duty ratio of the clock signal by adjusting the duration of the high level of the clock signal.
  • the modulation module may be configured to detect a rising edge of the input clock signal and the delayed clock signal, and output a rising edge when a rising edge of the input clock signal is detected, when the delayed clock signal is detected
  • the clock adjustment module in this embodiment may be a rising edge detector. As shown in Figure 5, when the rising edge detector detects CLK_IN, the rising edge detector output signal CLK_OUT also outputs a rising edge. When the rising edge of CLK_IN_DELAY is detected, CLK_OUT changes from high level to low level.
  • the duty ratio of the output clock signal CLK_OUT of this embodiment depends on the delay Tdealy between CLK_IN_DELAY and CLK_IN of CLK_OUT.
  • the clock delay processing module in the adjusting circuit of the embodiment is configured to reduce the duty ratio when the duty ratio of the output clock signal CLK_OUT is greater than 0.5, based on the adjusted duty ratio mode shown in FIG. a delay Tdealy between the input clock signal CLK_IN and the delayed clock signal CLK_IN_DELAY, increasing the input clock signal CLK_IN and the delayed clock signal CLK_IN_DELAY when the duty ratio of the output clock signal CLK_OUT is less than 0.5
  • the delay between the two is Tdealy.
  • the adjustment circuit of the embodiment can adjust the input clock signal of any duty ratio to an output clock signal with a duty ratio of 0.5, for example, the duty ratio of CLK_OUT is 0.6>0.5, and the clock delay processing module will Decrease Tdealy to reduce the duty cycle until the duty cycle of CLK_OUT is 0.5; or if the duty cycle of CLK_OUT is 0.4 ⁇ 0.5, the clock delay processing module will increase Tdealy, thereby increasing the duty cycle until The duty cycle of CLK_OUT is 0.5.
  • the clock delay processing module in the embodiment includes: a clock delay sub-module and a clock feedback sub-module; and the clock feedback sub-module is configured to acquire the output clock signal, and the The duty cycle of the output clock signal is converted to a control voltage Vctrl; the clock delay sub-module is configured to delay the input clock signal to obtain the delayed clock signal, And adjusting a delay between the input clock signal and the delayed clock signal according to the control voltage Vctrl.
  • the adjusting circuit of this embodiment can convert the output clock duty information into a control voltage, and control the clock delay sub-module to adjust the delay between the input clock signal CLK_IN and the delayed clock signal CLK_IN_DELAY by the control voltage Tdealy .
  • the clock delay sub-module in this embodiment may be a voltage-controlled delay device.
  • the clock feedback sub-module of the embodiment is further configured to convert the duty ratio of the output clock signal into a changed control voltage Vctrl; the clock delay sub-module is further configured to adjust the according to the change of the control voltage Vctrl The delay between the input clock signal and the delayed clock signal.
  • the clock feedback sub-module is further configured to convert the output clock signal to a control voltage in a reduced state when the duty ratio of the output clock signal is greater than 0.5; when the duty ratio of the output clock signal is less than 0.5 When it is converted into a control voltage in an increased state;
  • the clock delay sub-module is further configured to reduce a delay between the input clock signal and the delayed clock signal when the control voltage is in a reduced state, when the control voltage is increasing The state increases the delay between the input clock signal and the delayed clock signal.
  • the priority clock feedback module is a charge pump, and the duty cycle of the output clock signal is converted into a changed control voltage by the charge pump.
  • the charge pump of this embodiment is composed of a current rudder phase detector and a low pass filter connected in series; the current rudder phase detector is configured to convert the duty ratio of the output clock signal into a control voltage, and use the control voltage to The low pass filter is charged and discharged to obtain a control voltage in an increased or decreased state.
  • the clock delay processing module may also be configured. Decreasing a delay between the input clock signal and the delayed clock signal when a duty ratio of the output clock signal is greater than a first threshold; when a duty cycle of the output clock signal is less than the a threshold value increases a delay between the input clock signal and the delayed clock signal; correspondingly, the clock feedback sub-module may be further configured to: when the duty ratio of the output clock signal is greater than the first At the threshold, converting it to a control voltage in a reduced state; when the duty ratio of the output clock signal is less than the first threshold, converting it to a control voltage in an increasing state; the clock delay The submodule may be further configured to reduce a delay between the input clock signal and the delayed clock signal when the control voltage is in a reduced state; and increase the threshold when the control voltage is in an increased state a delay between the input
  • the clock duty ratio adjusting circuit and the multi-phase clock generator provided by the embodiment of the present invention configure a clock delay processing module to delay the input clock signal of the clock duty ratio adjusting circuit to obtain a delayed clock. And a module for obtaining an output clock signal of the clock duty cycle adjustment circuit, adjusting a delay between the input clock signal and the delayed clock signal according to a duty ratio of the output clock signal;
  • the clock adjustment module is configured to adjust a duty ratio of the input clock signal according to the delayed clock signal to obtain a module for outputting the clock signal, so that the embodiment of the present invention can utilize the delay of the input clock signal
  • the clock signal adjusts the input clock signal, and dynamically adjusts the delayed clock signal by using the duty ratio of the output clock signal to finally obtain an output clock signal of a desired duty ratio.
  • the adjustment circuit described in the embodiment of the present invention does not need to adjust the clock.
  • the duty cycle information is converted to a slew rate to adjust the output clock duty cycle, thereby avoiding the slew r.
  • the problem of increased dynamic power consumption caused by ate (swing rate) achieves the effect of reducing the time between the high level of the power supply and the current, saving the dynamic power consumption.
  • the adjustment circuit according to the embodiment of the present invention does not need to be adjusted by using a phase mixer, the duty error caused by the uncertainty of the accuracy of the mixer is avoided; therefore, compared with the adjustment circuit of the prior art,
  • the clock duty cycle adjustment circuit described in the embodiment of the invention can save power consumption, Improve the accuracy of the duty cycle adjustment.
  • the clock duty ratio adjustment circuit of the embodiment of the present invention converts clock duty information into a control voltage by using a charge pump, and does not use an error control amplifier to convert clock duty information into a control voltage, therefore, The problem of increased power consumption and reduced duty cycle adjustment accuracy caused by the decrease of the gain of the error control amplifier at the high frequency is avoided; and the embodiment of the present invention increases the loop gain and improves the comparison with the prior art. Accuracy and response speed for duty cycle adjustment.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the embodiment provides a clock duty ratio adjusting circuit, which is composed of a voltage controlled delay device, a rising edge detector, and a charge pump, and the charge pump is further composed of a current steering phase detector and a low pass filter. composition.
  • the rising edge detector constitutes a clock adjusting module of the embodiment of the invention
  • the voltage controlled delay device and the charge pump constitute a clock delay processing module of the embodiment of the invention, wherein the charge pump functions as a clock feedback module.
  • the function of the voltage controlled delay is to adjust the delay between the output signal CLK_IN_DELAY and the input signal CLK_IN as the control voltage Vctrl changes.
  • the rising edge detector is configured to detect the rising edges of the two signals CLK_IN and CLK_IN_DELAY, when detected On the rising edge of CLK_IN, the rising edge detector output signal CLK_OUT also outputs a rising edge.
  • CLK_OUT changes from high level to low level.
  • the timing diagram of the rising edge detector is shown in Figure 5. Shown. Therefore, adjusting the rising edge of CLK_IN_DELAY, that is, adjusting the control voltage Vctrl of the voltage-controlled delay device, changing the delay Tdealy of the voltage-controlled delay device, the high-level duration Thigh of the output clock signal CLK_OUT can be adjusted, thereby adjusting CLK_OUT Duty cycle.
  • a feedback circuit ie, a charge pump
  • the current rudder phase detector converts the duty cycle of the output clock signal CLK_OUT into a control voltage Vctrl
  • the low pass filter is configured to smooth Vctrl and increase the circuit gain of the feedback loop, and the current rudder phase detector and the low pass filter are formed.
  • a charge pump as shown in Figure 8, When the level of CLK_OUT is low, the charging current Iup of the current rudder phase detector charges the low-pass filter, so that Vctrl increases.
  • the voltage-controlled delay device and the charge pump realize a control voltage that changes in a state when the duty ratio of the output clock signal is not 50%, and then the voltage-controlled delay device controls the delay by controlling the voltage change to make the output The duty cycle of the clock signal is eventually 50%.
  • the clock ratio null adjustment circuit can adjust the clock signal of any duty cycle to a clock signal with 50% duty, which does not need to convert the output clock duty ratio information into a slew rate to adjust the output.
  • the clock duty cycle does not need to be adjusted by using a mixer, but adjusts the duty cycle of the output clock by converting the output clock duty cycle information into the rising edge delay information of the input clock; compared with the prior art, It saves power and increases duty cycle adjustment accuracy.
  • this embodiment uses a charge pump to convert the output clock duty information into a control voltage, which increases the loop gain, improves the accuracy and response speed of the duty cycle adjustment, and avoids the error control amplifier at high frequencies.
  • the power consumption due to the decrease in gain is increased, and the accuracy of duty cycle adjustment is lowered.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the embodiment provides a multi-phase clock generator, including a DLL (Delay Locked Loop) circuit and at least two clock duty ratio adjustment circuits (adjustment circuit). 1-n); the DLL circuit is configured to generate at least two different phase clock signals (CLK-1, CLK-2, ... CLK-n); the at least two clock duty cycle adjustment circuits are configured to respectively Duty cycle adjustment of at least two clock signals of different phases; the clock The number of duty cycle adjustment circuits corresponds to the phase type at which the DLL circuit generates a clock signal.
  • DLL Delay Locked Loop
  • CLK-n Phase Locked Loop
  • the at least two clock duty cycle adjustment circuits are configured to respectively Duty cycle adjustment of at least two clock signals of different phases
  • the clock The number of duty cycle adjustment circuits corresponds to the phase type at which the DLL circuit generates a clock signal.
  • the DLL circuit requires several clock duty cycle adjustment circuits to generate clock signals of several phases. For example, generating eight different phase clock signals requires eight clock duty cycle adjustment circuits to adjust the clock signals for each phase.
  • a control circuit may also be added, the control circuit being configured to control whether the clock duty cycle adjustment circuit operates.
  • the control circuit in this embodiment may be a decoder.
  • clock duty cycle adjustment circuit of the embodiment of the present invention is not limited to adjusting the clock signal in the DLL circuit, and can also adjust the clock signal generated by other circuits.
  • the multi-phase clock generator of the present embodiment will be specifically described below with a multi-phase clock generator that generates clock signals of eight different phases.
  • the multi-phase clock generator includes: a conventional DLL circuit, a 3x8 decoder, and eight clock duty ratio adjustment circuits as described above; the circuit in the dotted line frame is a conventional DLL structure, wherein the delay unit There are eight, each delay unit has the same delay, so the phase shift of each delay unit is 45 degrees, which can generate signals of different phases of CLK_45, CLK_90, CLK_135, CLK_180, CLK_225, CLK_270, CLK_315, CLK_3608.
  • the eight clock duty ratio adjustment circuits respectively adjust the duty ratio of the signals of eight different phases, and output signals of eight different phases with a duty ratio of 50%; the 3x8 decoder is used as a switch to control the duty ratio adjustment circuit. Work or not.
  • the embodiment of the present invention can adjust the input clock signal by using the delayed clock signal of the input clock signal, and dynamically adjust the delayed clock signal by using the duty ratio of the output clock signal to finally obtain the output clock signal of the required duty ratio, thus
  • the adjustment circuit described in the embodiment of the present invention does not need to convert the clock duty ratio information into a slew rate to adjust the output clock duty ratio, thereby avoiding an increase in dynamic power consumption due to a slew rate.
  • the problem is achieved by reducing the time-to-time effect of the power supply high level and current, saving the purpose of dynamic power consumption.

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Abstract

La présente invention concerne un circuit de réglage de coefficient d'utilisation d'horloge, comprenant : un module de traitement de temporisation d'horloge et un module de réglage d'horloge, ledit module de traitement de temporisation d'horloge étant conçu pour appliquer un retard sur un signal d'entrée d'horloge du circuit de réglage de coefficient d'utilisation d'horloge pour obtenir un signal d'horloge temporisé, et acquérir un signal d'horloge de sortie du circuit de réglage de coefficient d'utilisation d'horloge pour ajuster le retard entre le signal d'entrée d'horloge et le signal d'horloge temporisé en fonction du coefficient d'utilisation du signal de sortie d'horloge. Ledit module de réglage d'horloge est configuré pour ajuster le coefficient d'utilisation du signal d'entrée d'horloge en fonction du signal d'horloge temporisé pour obtenir le signal de sortie d'horloge. L'invention concerne en outre un générateur de signal d'horloge multiphasé.
PCT/CN2015/075206 2014-04-01 2015-03-27 Circuit de réglage de coefficient d'utilisation d'horloge et générateur de signal d'horloge multiphasé Ceased WO2015149653A1 (fr)

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CN201410129747.7A CN104980126A (zh) 2014-04-01 2014-04-01 一种时钟占空比调整电路及多相位时钟产生器
CN201410129747.7 2014-04-01

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CN110459161B (zh) * 2019-08-23 2023-04-07 北京集创北方科技股份有限公司 接收装置、驱动芯片、显示装置及电子设备
CN113162586B (zh) * 2021-04-16 2024-02-13 南京大学 一种时钟占空比修调方法及系统
CN113852362B (zh) * 2021-12-01 2022-02-08 广东芯炽集成电路技术有限公司 一种用于高速模数转换器的占空比可调电路
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