WO2015151797A1 - Substrat de montage et dispositif électronique - Google Patents

Substrat de montage et dispositif électronique Download PDF

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Publication number
WO2015151797A1
WO2015151797A1 PCT/JP2015/057848 JP2015057848W WO2015151797A1 WO 2015151797 A1 WO2015151797 A1 WO 2015151797A1 JP 2015057848 W JP2015057848 W JP 2015057848W WO 2015151797 A1 WO2015151797 A1 WO 2015151797A1
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WO
WIPO (PCT)
Prior art keywords
wiring
layer
light emitting
emitting element
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2015/057848
Other languages
English (en)
Japanese (ja)
Inventor
青柳　哲理
菊地　健
友田　勝寛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to CN201580015838.0A priority Critical patent/CN106133815B/zh
Priority to US15/128,227 priority patent/US10971412B2/en
Priority to EP15774421.0A priority patent/EP3128505B1/fr
Publication of WO2015151797A1 publication Critical patent/WO2015151797A1/fr
Anticipated expiration legal-status Critical
Priority to US17/202,275 priority patent/US12027429B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/232—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising connection or disconnection of parts of a device in response to a measurement
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V19/00—Fastening of light sources or lamp holders
    • F21V19/001—Fastening of light sources or lamp holders the light sources being semiconductors devices, e.g. LEDs
    • F21V19/003—Fastening of light source holders, e.g. of circuit boards or substrates holding light sources
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/852—Encapsulations
    • H10H20/853—Encapsulations characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/855—Optical field-shaping means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2115/00—Light-generating elements of semiconductor light sources
    • F21Y2115/10—Light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes

Definitions

  • This technology relates to a mounting board on which fine pixels are mounted on a wiring board, and an electronic apparatus including the mounting board.
  • Patent Document 1 discloses a display device that drives each LED (Light Emitting Diode) provided at an intersection of a signal line and a scanning line by turning on and off signal lines and scanning lines arranged in a grid pattern. ing.
  • this driving method since video display is performed by sequential scanning of scanning lines, it is not easy to increase display luminance.
  • Patent Document 2 it is conceivable to provide an LED and a driving IC for each pixel and to actively drive each LED.
  • these may be embedded with resin for the purpose of protecting the LED and the driving IC.
  • the resin for embedding the LED and the drive IC is thick, the wiring board is likely to warp due to the thick resin.
  • the wiring board is warped by the resin, there may be a problem that the LED or the driving IC is peeled off from the wiring board due to the warping of the wiring board.
  • the defective product is covered with resin, and thus there is a problem that it is not easy to repair the defective product.
  • a mounting board includes a wiring board, a plurality of light emitting elements arranged in a matrix on the wiring board, and a plurality of drives arranged in a matrix on the wiring board to control light emission of the light emitting elements.
  • IC The light emitting element and the driving IC are mounted on the same surface.
  • the wiring board has a plurality of first wirings that electrically connect the light emitting element and the driving IC to each other on the mounting surface of the light emitting element and the driving IC.
  • An electronic apparatus includes one or more mounting boards and a control circuit that controls the one or more mounting boards.
  • the light emitting element and the driving IC are mounted on the same surface, and the plurality of first wirings that electrically connect the light emitting element and the driving IC to each other emit light. It is formed on the mounting surface of the element and the driving IC.
  • the light emitting element, the driving IC, and the first wiring are formed on a common surface, a defect is found in the light emitting element, the driving IC, or the first wiring in the process of manufacturing the mounting substrate.
  • the light emitting element, the driving IC, and the first wiring can be easily repaired.
  • the light emitting element, the driving IC, and the first wiring are formed on a common surface, the light emitting element and the driving IC are formed in different layers, or the first wiring is a mounting surface of the light emitting element and the driving IC. Compared with the case where it is formed in an upper layer, the thickness of the resin for embedding the light emitting element, the driving IC and the first wiring can be reduced.
  • the light emitting element, the driving IC, and the first wiring are formed on a common surface. Can be easily repaired, and defects when the light emitting element, the driving IC, and the first wiring are covered with resin can be reduced.
  • FIG. 3 is a diagram illustrating an example of a perspective configuration of a unit substrate in FIG. 2. It is a figure showing an example of the circuit structure in the cell of FIG. It is a figure showing an example of the plane structure of the light emitting element of FIG.
  • FIG. 5 is a diagram illustrating an example of a planar configuration of the drive IC in FIG. 4. It is a figure showing an example of the cross-sectional structure of the cell of FIG. It is a figure showing an example of the manufacturing method of the cell of FIG. FIG.
  • FIG. 9 is a diagram illustrating an example of a process following FIG.
  • FIG. 10 is a diagram illustrating an example of a process following FIG. 9.
  • FIG. 11 is a diagram illustrating an example of a process following FIG. 10.
  • FIG. 12 is a diagram illustrating an example of a process following FIG. 11. It is a figure showing an example of the perspective composition of the illuminating device concerning a 2nd embodiment of this art. It is a figure showing the modification of the circuit structure in the cell of FIG.
  • FIG. 10 is a diagram illustrating a modification of the perspective configuration of the display device in FIG. 1. It is a figure showing one modification of the isometric view structure of the illuminating device of FIG.
  • FIG. 1 illustrates an example of a perspective configuration of the display device 1 according to the first embodiment of the present technology.
  • the display device 1 is a so-called LED display, and uses LEDs as display pixels.
  • the display device 1 includes a display panel 10 and a control circuit 20 that controls the display panel 10 (specifically, a cell 10E described later).
  • the display panel 10 is obtained by stacking a mounting substrate 10A and a counter substrate 10B on each other.
  • the surface of the counter substrate 10B is a video display surface, which has a display area at the center and a frame area which is a non-display area around the display area.
  • the counter substrate 10B is disposed, for example, at a position facing the mounting substrate 10A via a predetermined gap. Note that the counter substrate 10B may be in contact with the upper surface of the mounting substrate 10A.
  • the counter substrate 10B includes, for example, a light transmissive substrate that transmits visible light, and includes, for example, a glass substrate, a transparent resin substrate, or a transparent resin film.
  • FIG. 2 illustrates an example of a perspective configuration of the mounting substrate 10A.
  • the mounting substrate 10 ⁇ / b> A includes a plurality of unit substrates 10 ⁇ / b> C arranged in a tile shape.
  • FIG. 3 illustrates an example of a perspective configuration of the unit substrate 10C.
  • the unit substrate 10C includes, for example, a plurality of cells 10E arranged in a tile shape and a support substrate 10D that supports each cell 10E.
  • Each unit substrate 12C further has a control substrate (not shown).
  • the control board is electrically connected to each cell 10E via each electrode pad 34 described later.
  • the support substrate 10D is configured by, for example, a metal frame or a wiring substrate.
  • the support substrate 10D When the support substrate 10D is composed of a wiring substrate, it can also serve as a control substrate. At this time, at least one of the support substrate 10D and the control substrate is electrically connected to each cell 10E (or a wiring substrate 30 described later) via each electrode pad 34.
  • the support substrate 10D corresponds to a specific example of “support substrate” of the present technology.
  • the electrode pad 34 corresponds to a specific example of “electrode pad” of the present technology.
  • FIG. 4 illustrates an example of a circuit configuration in the cell 10E.
  • the cell 10E includes a plurality of data lines Sig extending in the column direction and a plurality of gate lines Gate extending in the row direction in a region facing the display region.
  • the data line Sig and the gate line Gate are made of, for example, copper.
  • the data line Sig corresponds to a specific example of “signal line” of the present technology.
  • the gate line Gate corresponds to a specific example of “selection line” of the present technology.
  • the cell 10E further includes a plurality of pixels 11 arranged in a matrix in a region facing the display region described above.
  • Each pixel 11 includes a light emitting element 12 and a drive IC 13 that drives the light emitting element 12.
  • the pixel 11 corresponds to a specific example of “pixel” in the present technology.
  • the light emitting element 12 corresponds to a specific example of “light emitting element” of the present technology.
  • the drive IC 13 corresponds to a specific example of “drive IC” of the present technology.
  • the cell 10E further includes, for example, a plurality of saw voltage lines Saw, a plurality of power supply lines VDD1 and VDD2, a plurality of reference voltage lines Ref1 and Ref2, and a plurality of ground lines GND in an area facing the display area. And have.
  • Each saw voltage line Saw extends, for example, in the row direction.
  • Each power supply line VDD1, each power supply line VDD2, each reference voltage line Ref1, each reference voltage line Ref2, and each ground line GND for example, extends in the column direction.
  • At least one of the saw voltage line Saw, the power supply lines VDD1 and VDD2, the reference voltage lines Ref1 and Ref2, and the ground line GND may be omitted depending on the driving method.
  • the saw voltage line Saw, the power supply lines VDD1 and VDD2, the reference voltage lines Ref1 and Ref2, and the ground line GND are made of, for example, copper.
  • column wiring is used as a general term for the data line Sig, the power supply line VDD1, the power supply line VDD2, the reference voltage line Ref1, the reference voltage line Ref2, and the ground line GND.
  • row wiring is used as a general term for the gate line Gate and the saw voltage line Saw.
  • Each data line Sig is a wiring through which a signal corresponding to the video signal is input by the control circuit 20.
  • the signal corresponding to the video signal is, for example, a signal that controls the light emission luminance of the light emitting element 12.
  • the plurality of data lines Sig are made of, for example, a type of wiring corresponding to the number of emission colors of the light emitting element 12.
  • the plurality of data lines Sig include, for example, a plurality of data lines SigR, a plurality of data lines SigG, and a plurality of data lines SigB.
  • Each data line SigR is a wiring through which a signal corresponding to a red video signal is input by the control circuit 20.
  • Each data line SigG is a wiring through which a signal corresponding to a green video signal is input by the control circuit 20.
  • Each data line SigB is a wiring through which a signal corresponding to a blue video signal is input by the control circuit 20.
  • the emission color of the light emitting element 12 is not limited to three colors, and may be four or more colors.
  • the plurality of data lines Sig includes a plurality of data lines SigR, a plurality of data lines SigG, and a plurality of data lines SigB, one data line SigR, one data line SigG, and one data line SigR
  • a set of data lines Sig consisting of is assigned to each pixel column, for example.
  • the set of data lines Sig is assigned to each of the plurality of pixel columns. Further, depending on the driving method, the set of data lines Sig can be replaced with a single data line Sig.
  • Each gate line Gate is a wiring through which a signal for selecting the light emitting element 12 is input by the control circuit 20.
  • the signal for selecting the light emitting element 12 is, for example, a signal for starting sampling of the signal input to the data line Sig and causing the sampled signal to be input to the light emitting element 12 to start light emission of the light emitting element 12.
  • One gate line Gate is allocated, for example, for each pixel row.
  • Each saw voltage line Saw is, for example, a wiring to which a signal having a sawtooth waveform is input by the control circuit 20.
  • a signal having a sawtooth waveform is compared with a sampled signal, for example, sampled only for a period when the peak value of the signal having a sawtooth waveform is higher than the peak value of the sampled signal.
  • a signal is input to the light emitting element 12.
  • One saw voltage line Saw is allocated, for example, every two pixel rows.
  • Each power supply line VDD ⁇ b> 2 is a wiring through which a drive current supplied to the light emitting element 12 is input by the control circuit 20.
  • One power supply line VDD2 is assigned, for example, every two pixel columns.
  • Each power supply line VDD1, each reference voltage line Ref1, each reference voltage line Ref2, and each ground line GND is a wiring to which a fixed voltage is input by the control circuit 20.
  • a ground potential is input to each ground line GND.
  • One power supply line VDD1 is allocated for every two pixel columns, for example.
  • One reference voltage line Ref1 is assigned, for example, every two pixel columns.
  • One reference voltage line Ref2 is assigned for every two pixel columns, for example.
  • One ground line GND is allocated for every two pixel columns, for example.
  • FIG. 5 illustrates an example of a planar configuration of the light emitting element 12.
  • a symbol surrounded by a square indicates that a terminal adjacent to the symbol is electrically connected to a terminal adjacent to the same symbol described later in FIG.
  • the light emitting element 12 is a chip-like component that emits light of a plurality of colors.
  • the light emitting element 12 includes, for example, a light emitting element 12R that emits red light, a light emitting element 12G that emits green light, and a light emitting element 12B that emits blue light.
  • the light emitting elements 12R, 12G, and 12B are covered with a protective body 12i made of, for example, a resin.
  • the light emitting elements 12R, 12G, and 12B are, for example, LED chips.
  • the LED chip has a micrometer order chip size, for example, several tens of ⁇ m square.
  • the LED chip has, for example, a semiconductor layer including a stacked structure in which an active layer is sandwiched between semiconductor layers having different conductivity types, and two electrodes disposed on a common surface (same surface) of the semiconductor layer. Yes.
  • the light emitting elements 12R, 12G, and 12B may be separate chips, or may be a single chip that is common to each other.
  • the light emitting element 12 has, for example, six electrode pads 12a to 12f.
  • one electrode is electrically connected to the electrode pad 13m of the driving IC 13 via the electrode pad 12a and the wiring 16 (see FIG. 4), and the other electrode is the electrode pad 12b and the wiring 16. Is electrically connected to the ground line GND.
  • one electrode is electrically connected to the electrode pad 13o of the driving IC 13 through the electrode pad 12c and the wiring 16, and the other electrode is connected to the ground line through the electrode pad 12d and the wiring 16. It is electrically connected to GND.
  • one electrode is electrically connected to the electrode pad 13p of the driving IC 13 through the electrode pad 12e and the wiring 16, and the other electrode is connected to the ground line through the electrode pad 12f and the wiring 16. It is electrically connected to GND.
  • the wiring 16 electrically connects the pixel 11 to the data line Sig, the gate line Gate, the power supply line VDD1, the power supply line VDD2, the reference voltage line Ref1, the reference voltage line Ref2, the saw voltage line Saw, or the ground line GND.
  • the wiring 16 is also a wiring for electrically connecting the light emitting element 12 and the driving IC 13 to each other in the pixel 11.
  • the wiring 16 is formed by sputtering or plating, for example.
  • the wiring 16 corresponds to a specific example of “first wiring”, “third wiring”, and “third wiring” of the present technology.
  • Each wiring 16 is formed in the same layer (or in the same plane). Some of the plurality of wirings 16 directly connect the pixels 11 to the various row wirings and the various column wirings.
  • the other wirings 16 among the plurality of wirings 16 are composed of a plurality of partial wirings formed intermittently.
  • each wiring 16 composed of a plurality of partial wirings each partial electrode has one or a plurality of wirings (for example, one or a plurality of relay wirings 15 described later) formed in a layer below each wiring 16 (for example, a wiring layer 32E described later). ).
  • the relay wiring 15 is made of, for example, copper.
  • FIG. 6 shows an example of a planar configuration of the drive IC 13.
  • a wiring name surrounded by a square indicates a name of a wiring that is electrically connected to a terminal adjacent to the wiring name.
  • the drive IC 13 controls the light emission of the light emitting element 12.
  • the drive IC 13 has, for example, 14 electrode pads 13a, 13b, 13c, 13d, 13e, 13f, 13g, 13h, 13i, 13k, 13m, 13n, 13o, and 13p.
  • the electrode pads 13a, 13b, and 13c are electrically connected to the data lines SigG, SigR, and SigB through the wiring 16.
  • the electrode pads 13d and 13e are electrically connected to the power supply lines VDD1 and VDD2 through the wiring 16.
  • the electrode pads 13f and 13g are electrically connected to the reference potential lines Ref1 and Ref2 through the wiring 16.
  • the electrode pad 13h is electrically connected to the ground line GND through the wiring 16.
  • the electrode pad 13 i is electrically connected to the gate line Gate through the wiring 16.
  • the electrode pad 13k is electrically connected to the saw voltage line Saw via the wiring 16.
  • the electrode pads 13m, 13o, and 13n are electrically connected to the electrode pads 12a, 12c, and 12e of the light emitting element 12 through the wiring 16.
  • the electrode pad 13 p is not connected to the wiring 16.
  • FIG. 7 illustrates an example of a cross-sectional configuration of the cell 10E.
  • FIG. 7 shows an example of a cross-sectional configuration of a location where the light emitting element 12, the driving IC 13, the data line SigB1, and the gate line Gate2 are formed in the cell 10E.
  • the cell 10E includes a wiring substrate 30, a fine L / S layer 40 formed in contact with the upper surface of the wiring substrate 30, and a plurality of pixels 11 arranged in a matrix on the upper surface of the fine L / S layer 40. is doing.
  • the wiring board 30 has a role as an intermediate board in relation to the wiring board 10D.
  • the wiring board 30 corresponds to a specific example of “wiring board” of the present technology.
  • the fine L / S layer 40 corresponds to a specific example of “fine L / S layer” of the present technology.
  • the cell 10E further includes, for example, a buried layer 44 covering the surface including each pixel 11, a light shielding layer 45 formed in contact with the buried layer 44, and an insulating layer 50 formed in contact with the back surface of the wiring substrate 30. And have.
  • the embedded layer 44 is made of a light-transmitting material that transmits visible light, and is formed of, for example, a light-transmitting resin layer that transmits visible light.
  • the light shielding layer 45 includes a material that absorbs visible light.
  • the insulating layer 50 is made of, for example, an ultraviolet curable resin or a thermosetting resin.
  • the light shielding layer 45 has an opening 45 ⁇ / b> A at a location facing each light emitting element 12.
  • the light emitted from each light emitting element 12 is emitted to the outside through each opening 45A.
  • the insulating layer 50 has an opening 50A at a location facing each electrode pad 34 as an external connection terminal of the cell 10E. Accordingly, each electrode pad 34 is exposed on the back surface of the cell 10E (wiring substrate 30) through the opening 50A.
  • the electrode pad 34 and the wiring board 10D are electrically connected to each other through a metal bump or a solder bump provided in the opening 50A.
  • the wiring board 30 is, for example, a laminated board in which electrical connection between layers is made with vias.
  • the wiring board 30 has a plurality of electrode pads 34 as external connection terminals on the back surface of the wiring board 30.
  • the plurality of electrode pads 34 are, for example, for each of the data line SigR1, the data line SigG1, the data line SigB1, the gate line Gate1, the gate line Gate2, the power supply line VDD1, the reference voltage line Ref1, the reference voltage line Ref2, and the saw voltage line Saw.
  • One or more are provided.
  • the wiring board 30 electrically connects the plurality of wirings 16 routed in the fine L / S layer 40 and the plurality of electrode pads 34.
  • the wiring substrate 30 has a plurality of through wirings 17 that electrically connect the plurality of wirings 16 and the plurality of electrode pads 34.
  • Each through wiring 17 is a wiring that penetrates the wiring board 30 in the thickness direction.
  • a certain through wiring 17 includes a data line Sig extending in a column direction within a certain layer, and a plurality of vias penetrating a part of the layers in the wiring substrate 30.
  • a certain through wiring 17 includes a gate line Gate extending in a row direction in a certain layer and a plurality of vias penetrating a part of the layers in the wiring substrate 30.
  • a certain through wiring 17 includes a power supply line VDD1 extending in the column direction in a certain layer and a plurality of vias penetrating a part of the layers in the wiring substrate 30.
  • a certain through wiring 17 includes a reference voltage line Ref 1 extending in the column direction within a certain layer, and a plurality of vias penetrating a part of the layers in the wiring substrate 30.
  • a certain through wiring 17 includes a reference voltage line Ref ⁇ b> 2 extending in the column direction within a certain layer, and a plurality of vias penetrating a part of the layers in the wiring substrate 30.
  • a certain through wiring 17 includes a saw voltage line Saw extending in the column direction in a certain layer and a plurality of vias penetrating a part of the layers in the wiring substrate 30.
  • the plurality of pixels 11 are arranged at equal intervals in the row direction and the column direction, for example, as shown in FIG.
  • the pitch of the pixels 11 is equal not only in each cell 10E but also between two adjacent cells 10E.
  • a plurality of electrode pads 34 as external connection terminals of each cell 10E are provided on the back surface of the cell 10E. Therefore, it is possible to omit or minimize a frame region that cannot be used for the pixel 11 arrangement, such as when an external connection terminal is provided on the outer edge of the upper surface of the mounting surface. Therefore, if such a frame region is omitted from each cell 10E, or if such a frame region in each cell 10E is minimized, it is also between two adjacent cells 10E.
  • the pitch of the pixels 11 can be made equal.
  • the wiring substrate 30 is, for example, a build-up substrate, and includes a core substrate 31, a build-up layer 32 formed in contact with the upper surface of the core substrate 31, and a build-up layer 33 formed in contact with the back surface of the core substrate 31. And have.
  • the wiring board 30 corresponds to a specific example of “build-up board” of the present technology.
  • the buildup layers 32 and 33 correspond to a specific example of “buildup layer” of the present technology.
  • the core substrate 31 ensures the rigidity of the cell 10E, and is, for example, a glass epoxy substrate.
  • the buildup layer 32 has one or more wiring layers.
  • the buildup layer 32 includes a wiring layer 32 ⁇ / b> A, an insulating layer 32 ⁇ / b> B, a wiring layer 32 ⁇ / b> C, an insulating layer 32 ⁇ / b> D, and a wiring layer 32 ⁇ / b> E in this order from the upper surface side of the core substrate 31.
  • the buildup layer 33 has one or more wiring layers. For example, as shown in FIG.
  • the buildup layer 33 includes a wiring layer 33A, an insulating layer 33B, a wiring layer 33C, an insulating layer 33D, and a wiring layer 33E in this order from the back surface side of the core substrate 31.
  • the wiring layers 32A, 32C, 32E, 33A, 33C, 33E are made of, for example, copper.
  • the insulating layers 32B, 32D, 33B, 33D are made of, for example, an ultraviolet curable resin or a thermosetting resin.
  • Each data line Sig is formed in the buildup layer 32, for example.
  • FIG. 7 illustrates a state in which the data line SigB1 is formed in the wiring layer 32C.
  • Each gate line Gate is formed in a layer different from the data line Sig.
  • the gate line Gate is formed in a layer different from the data line Sig in the buildup layer 32.
  • FIG. 7 illustrates a state in which the gate line Gate2 is formed in the wiring layer 32A.
  • Each power supply line VDD2 and each ground line GND are formed in, for example, the wiring layer 32E.
  • Each electrode pad 34 is formed in the build-up layer 33, for example, in the same layer as the wiring layer 33E.
  • a later-described relay wiring 15 is formed in a wiring layer 32 ⁇ / b> E that is a wiring layer on the upper surface of the wiring substrate 30.
  • the fine L / S layer 40 includes a wiring layer 42 and an insulating layer 41 provided between the wiring layer 42 and the upper surface of the wiring substrate 30.
  • the insulating layer 41 is in contact with the wiring layer 42 and the upper surface of the wiring substrate 30.
  • the wiring layer 42 is a layer including each wiring 16. Therefore, the wiring layer 42 is formed in the fine L / S layer 40.
  • the insulating layer 41 is provided between each wiring 16 and the upper surface of the wiring substrate 30, and is in contact with each wiring 16 and the upper surface of the wiring substrate 30.
  • the insulating layer 41 has, for example, an opening 41A at a position facing the gate line Gate and the data line Sig.
  • the insulating layer 41 further has an opening 41A, for example, at a position facing the relay wiring 15 electrically connected to the partial electrode.
  • the gate line Gate, the data line Sig, and a part of the relay wiring 15 are exposed on the bottom surface of the opening 41A.
  • the insulating layer 41 is made of, for example, VPA.
  • VPA is generally used as a resist.
  • VPA manufactured by Nippon Steel Chemical Co., Ltd. is marketed.
  • the opening 41 can be formed in the VPA by selectively exposing and developing the VPA.
  • the wiring layer 42 (each wiring 16) includes, for example, a seed layer 42A in contact with the upper surface of the wiring substrate 30 including the bottom surface and side surface of the opening 41A, and a plating layer 42B in contact with the upper surface of the seed layer 42A.
  • the seed layer 42A becomes a plating growth surface when the plating layer 42B is formed by plating in the manufacturing process.
  • the seed layer 42A is in contact with the bottom surface of the opening 41A, and is electrically connected to, for example, the gate line Gate, the data line Sig, and the relay wiring 15.
  • the seed layer 42A is made of copper, for example.
  • the plating layer 42B is formed by a plating process using the seed layer 42A as a plating growth surface in the manufacturing process.
  • the wiring layer 42 (each wiring 16) may be a layer formed by sputtering, for example.
  • the wiring layer 42 (each wiring 16) is formed in contact with the upper surface of the insulating layer 41.
  • the electrode of each pixel 11 is formed in contact with the upper surface of the seed layer 42A. Therefore, although the light emitting element 12 and the driving IC 13 are formed on the same surface (the upper surface of the seed layer 42A), strictly speaking, the formation surface of the wiring layer 42 (each wiring 16) (the upper surface of the insulating layer 41). ) Is formed on a different surface.
  • the surface including the upper surface of the insulating layer 41 and the upper surface of the seed layer 42A is the mounting surface 41S. Accordingly, the wiring layer 42 (each wiring 16) is formed on the mounting surface 41 ⁇ / b> S of each pixel 11, and is formed on a surface substantially common to each pixel 11.
  • the wiring layer 42 (each wiring 16) is plated and bonded to, for example, the gate line Gate, the data line Sig, and the relay wiring 15 electrically connected to the partial electrodes.
  • the bonding between the wiring layer 42 (each wiring 16), the gate line Gate, and the data line Sig is a process of forming the wiring layer 42 (each wiring 16). It may be performed in a batch.
  • the wiring layer 42 (each wiring 16) is, for example, plated and bonded to the pixel 11 (the light emitting element 12 and the driving IC 13).
  • the bonding between the wiring layer 42 (each wiring 16) and the pixel 11 is collectively performed in the process of forming the wiring layer 42 (each wiring 16). It may be done.
  • the L / S (line and space) of the fine L / S layer 40 is smaller than the L / S of the wiring board 30.
  • L / S indicates the narrowest wiring pitch in the plane.
  • the L / S of the fine L / S layer 40 includes a plurality of signal lines Sig, a plurality of gate lines Gate, a plurality of voltage lines VDD1, a plurality of reference voltage lines Ref1, a plurality of reference voltage lines Ref2, and a saw voltage line Saw. It is smaller than L / S.
  • the L / S of the fine L / S layer 40 is, for example, about 25 ⁇ m.
  • L / S of the wiring board 30 is about 75 ⁇ m, for example.
  • FIGS. 8 to 12 show an example of the manufacturing process of the mounting substrate 10A in the order of steps.
  • the wiring board 30 is prepared.
  • an opening 41A is formed in the insulating layer 41 at a position facing the upper surfaces of the gate line Gate and the data line Sig by a predetermined method (FIG. 8).
  • the opening 41A is also formed at a position facing the upper surface of the relay wiring 15 electrically connected to the partial wiring by a predetermined method.
  • a seed layer 42A is formed on the upper surface of the wiring board 30 including the bottom and side surfaces of the opening 41A (FIG. 9).
  • a fixing layer 43A for temporarily fixing the light emitting element 12 and the driving IC 13 is formed by applying an insulating adhesive over the entire surface (see FIG. 10).
  • a pressure-sensitive adhesive layer represented by silicone or acrylic may be formed as the fixed layer 43A.
  • the light emitting element 12 and the driving IC 13 are temporarily fixed by the fixing layer 43A (FIG. 10).
  • the electrode pads 12a to 12e of the light emitting element 12 and the electrode pads 13a to 13p of the driving IC 13 are arranged so as to be connectable to a metal body (plating layer 42B) grown in a plating process described later.
  • the fixing layer 43A other than the part temporarily fixing the light emitting element 12 and the driving IC 13 (the part of the fixing layer 43A existing on the bottom surface of the light emitting element 12 and the driving IC 13) is removed.
  • the fixed layer 43A remains only on the bottom surfaces of the light emitting element 12 and the driving IC 13 (FIG. 11).
  • the remaining fixed layer 43 ⁇ / b> A is described as the fixed layer 43.
  • dry etching or organic solvent immersion can be performed.
  • an insulating adhesive may be applied in advance only to a place where the light emitting element 12 and the driving IC 13 are temporarily fixed.
  • plating is performed using the seed layer 42A as a plating growth surface, and a plating layer 42B is formed on the upper surface of the seed layer 42A (FIG. 12).
  • the wiring layer 42 (each wiring 16) is formed.
  • the wiring layer 42 (each wiring 16), the gate line Gate, and the data line Sig are joined together in the formation process of the wiring layer 42 (each wiring 16).
  • the wiring layer 42 (each wiring 16) and the pixel 11 are joined together in the formation process of the wiring layer 42 (each wiring 16).
  • the light shielding layer 45 is formed (see FIG. 7). In this way, the mounting substrate 10A is manufactured.
  • the light emitting element 12 and the driving IC 13 are formed on the same surface, and a plurality of wirings 16 that electrically connect the light emitting element 12 and the driving IC 13 to each other in each pixel 11 are also formed on the mounting surface 41S.
  • a plurality of wirings 16 that electrically connect the light emitting element 12 and the driving IC 13 to each other in each pixel 11 are also formed on the mounting surface 41S.
  • the driving IC 13, and the wiring 16 are formed on the common mounting surface 41S, in the process of manufacturing the mounting substrate 10A, for example, at the stage shown in FIG. Even when a defect is found in the IC 13 or the wiring 16, the light emitting element 12, the driving IC 13 and the wiring 16 can be easily repaired.
  • the light emitting element 12, the driving IC 13, and the wiring 16 are formed on the common mounting surface 41S, the light emitting element 12 and the driving IC 13 are formed in different layers, or the wiring 16 is formed in the light emitting element 12 and the driving IC 13.
  • the thickness of the resin (embedding layer 44) for embedding the light emitting element 12, the driving IC 13 and the wiring 16 can be reduced. Therefore, it is possible to easily repair the pixel 11 after mounting, and it is possible to reduce problems when the pixel 11 is covered with resin.
  • FIG. 13 illustrates an example of a perspective configuration of the illumination device 2 according to the second embodiment of the present technology.
  • the illumination device 2 does not change the signal input to the data line Sig every moment like the video signal. This corresponds to a fixed value corresponding to the brightness.
  • the lighting device 2 includes a lighting panel 60 and a control circuit 70 that controls the lighting panel 60.
  • the illumination panel 60 is obtained by superimposing a mounting substrate 60A and a counter substrate 60B on each other.
  • the surface of the counter substrate 60B is a light emitting surface.
  • the counter substrate 60B is disposed, for example, at a position facing the mounting substrate 60A via a predetermined gap. Note that the counter substrate 60B may be in contact with the upper surface of the mounting substrate 60A.
  • the counter substrate 60B includes, for example, a light transmissive substrate that transmits visible light, and includes, for example, a glass substrate, a transparent resin substrate, or a transparent resin film.
  • the mounting substrate 60A is composed of a plurality of unit substrates arranged in a tile shape, for example, as in FIG.
  • the unit substrate has, for example, a plurality of cells arranged in a tile shape and a support substrate that supports each cell.
  • Each unit substrate further includes a control substrate (not shown), and is electrically connected to each cell via each electrode pad 34.
  • the support substrate is composed of, for example, a metal frame or a wiring substrate. In the case where the support substrate is composed of a wiring substrate, it can also serve as a control substrate.
  • each cell for example, in FIGS. 4 and 7, when the signal input to the data line Sig has a fixed value corresponding to the brightness of the illumination light, wiring unnecessary for driving the pixel 11 is provided. This is omitted as appropriate.
  • the light emitting element 12, the driving IC 13, and the wiring 16 are formed on a common mounting surface 41S, similarly to the display device 1 according to the first embodiment and the modification thereof. Thereby, even if a defect is found in the light emitting element 12 or the driving IC 13 in the process of manufacturing the mounting substrate 1, the light emitting element 12 and the driving IC 13 can be easily repaired. Further, the light emitting element 12 and the driving IC 13 are formed in different layers, and the light emission is performed as compared with the case where the wiring 16 is formed in a layer above the mounting surface 41S of the light emitting element 12 and the driving IC 13.
  • the thickness of the resin (embedding layer 44) for embedding the element 12, the driving IC 13 and the wiring 16 can be reduced. Therefore, it is possible to easily repair the pixel 11 after mounting, and it is possible to reduce problems when the pixel 11 is covered with resin.
  • the light shielding layer 45 may be disposed on the back surfaces of the counter substrates 10B and 60B (surfaces on the mounting substrates 10A and 60A side).
  • one drive IC 13 is provided for each light emitting element 12.
  • one drive IC 13 may be provided for each of the plurality of light emitting elements 12.
  • one drive IC 13 may be provided for each of the four light emitting elements 12 in the 2 ⁇ 2 matrix.
  • the counter substrates 10B and 60B may be omitted.
  • the counter substrates 10B and 60B may be provided for each unit substrate 10C or for each cell 10E.
  • the light emitting element 12 may have a single emission color.
  • the cell 10E may have, for example, a plurality of color filters in the opening 45A.
  • the light shielding layer 45 may be omitted.
  • each pixel 11 (light emitting element 12 and driving IC 13) is plated and bonded to the wiring layer 42 (each wiring 16). Good. For example, after solder bumps are provided on the electrode pads of the light emitting element 12 and the driving IC 13, the light emitting element 12 and the driving IC 13 are arranged on each wiring 16, and then reflow is performed. Thereby, the light emitting element 12 and the driving IC 13 can be soldered to the wirings 16.
  • this technique can take the following composition.
  • a wiring board A plurality of pixels arranged in a matrix on the wiring board; Each of the pixels includes a light emitting element and a driving IC that controls light emission of the light emitting element, The light emitting element and the driving IC are mounted on the same surface,
  • the wiring board includes a plurality of first wirings that electrically connect the light emitting element and the driving IC to each other in each pixel, on a mounting surface of the light emitting element and the driving IC.
  • the wiring board is A plurality of selection lines formed in a lower layer than each of the first wirings and extending in a row direction; A plurality of signal lines formed in a lower layer than each first wiring and extending in a column direction; A second wiring formed in the same layer as each of the first wirings or in a layer lower than each of the first wirings and electrically connected to each of the selection lines; A third wiring formed in the same layer as each first wiring or in a layer lower than each first wiring, and electrically connected to each signal line;
  • the wiring board is A build-up substrate having a core substrate and one or more build-up layers formed on both surfaces of the core substrate, and electrical connection between the layers made by vias; A fine L / S (line and space) layer formed in contact with the upper surface of the build-up substrate, L / S of the fine L / S layer is smaller than L / S of the build-up substrate, Each selection line and each signal line are formed in the build-up layer, Each said 1st wiring, each said 2nd wiring, and each said 3rd wiring are the mounting boards as described in (2) formed in the said fine L / S layer.
  • the wiring board includes a resin layer that covers a surface including each light emitting element and each driving IC.
  • the mounting substrate is A wiring board; A plurality of pixels arranged in a matrix on the wiring board;
  • Each of the pixels includes a light emitting element and a driving IC that controls light emission of the light emitting element, The light emitting element and the driving IC are mounted on the same surface,
  • the electronic device wherein the wiring board includes a plurality of first wirings that electrically connect the light emitting element and the driving IC to each other in each pixel, on a mounting surface of the light emitting element and the driving IC.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Led Device Packages (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

Conformément à un mode de réalisation, la présente invention concerne un substrat de montage qui comporte un substrat de câblage (30), une pluralité d'éléments électroluminescents (12) agencés en une matrice sur le substrat de câblage, et une pluralité de circuits intégrés (IC) d'attaque (13) qui sont agencés en une matrice sur le substrat de câblage et commandent une émission de lumière à partir des éléments électroluminescents. Les éléments électroluminescents et le circuit intégré (IC) d'attaque sont montés sur la même surface. Le substrat de câblage a, sur la surface de montage pour les éléments électroluminescents et le circuit intégré (IC) d'attaque, une pluralité de premiers fils (16) qui connectent électriquement les éléments électroluminescents et le circuit intégré (IC) d'attaque les uns aux autres.
PCT/JP2015/057848 2014-03-31 2015-03-17 Substrat de montage et dispositif électronique Ceased WO2015151797A1 (fr)

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CN201580015838.0A CN106133815B (zh) 2014-03-31 2015-03-17 安装基板以及电子装置
US15/128,227 US10971412B2 (en) 2014-03-31 2015-03-17 Mounting substrate and electronic apparatus
EP15774421.0A EP3128505B1 (fr) 2014-03-31 2015-03-17 Substrat de montage et dispositif électronique
US17/202,275 US12027429B2 (en) 2014-03-31 2021-03-15 Mounting substrate and electronic apparatus

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JP2014-074843 2014-03-31
JP2014074843A JP2015197544A (ja) 2014-03-31 2014-03-31 実装基板および電子機器

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US17/202,275 Continuation US12027429B2 (en) 2014-03-31 2021-03-15 Mounting substrate and electronic apparatus

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US12027429B2 (en) 2024-07-02
US20170103926A1 (en) 2017-04-13
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CN106133815A (zh) 2016-11-16
EP3128505B1 (fr) 2020-10-21
JP2015197544A (ja) 2015-11-09
CN106133815B (zh) 2019-02-01
US10971412B2 (en) 2021-04-06
EP3128505A1 (fr) 2017-02-08

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