WO2016072024A1 - Procédé de fabrication de transistor à couches minces, transistor à couches minces et écran d'affichage - Google Patents

Procédé de fabrication de transistor à couches minces, transistor à couches minces et écran d'affichage Download PDF

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Publication number
WO2016072024A1
WO2016072024A1 PCT/JP2014/079619 JP2014079619W WO2016072024A1 WO 2016072024 A1 WO2016072024 A1 WO 2016072024A1 JP 2014079619 W JP2014079619 W JP 2014079619W WO 2016072024 A1 WO2016072024 A1 WO 2016072024A1
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Prior art keywords
silicon layer
amorphous silicon
layer
film transistor
substrate
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Japanese (ja)
Inventor
伸武 野寺
石田　茂
良平 高倉
吉明 松島
隆夫 松本
小林　和樹
大亥 桶谷
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Sakai Display Products Corp
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Sakai Display Products Corp
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Priority to PCT/JP2014/079619 priority Critical patent/WO2016072024A1/fr
Priority to US15/327,615 priority patent/US10038098B2/en
Publication of WO2016072024A1 publication Critical patent/WO2016072024A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to a method for manufacturing a thin film transistor, a thin film transistor, and a display panel including the thin film transistor.
  • a TFT (Thin Film Transistor) type liquid crystal display is obtained by bonding a TFT substrate and a color filter substrate having R (red), G (green), and B (blue) colors with a necessary gap therebetween.
  • An image can be displayed by injecting liquid crystal between the substrate and the color filter substrate and controlling the light transmittance of the liquid crystal molecules for each pixel.
  • data lines and scanning lines are arranged in a grid pattern in the vertical and horizontal directions, and pixels composed of TFTs are formed at locations where the data lines and the scanning lines intersect.
  • a drive circuit configured by TFTs and driving data lines and scanning lines is formed around a display region including a plurality of pixels.
  • a-Si TFTs amorphous silicon TFTs
  • amorphous p-Si (polysilicon) TFTs depending on the crystalline state of the semiconductor (silicon).
  • the a-Si TFT has a high resistance and a small leakage current (leakage current).
  • the p-Si TFT has a significantly higher electron mobility than the a-Si TFT. For this reason, an a-Si TFT having a small leakage current is used for each pixel constituting the display region, and a p-Si TFT having a high electron mobility is used for the drive circuit.
  • the a-Si TFT has a bottom gate structure in which the gate electrode is arranged in the lowest layer, and the p-Si TFT has a gate electrode on the upper side of the semiconductor film.
  • the top gate structure to be arranged is used.
  • TFTs having different structures are formed on a single substrate, the manufacturing process becomes complicated.
  • an a-Si layer is formed in advance on the entire substrate, and the entire substrate is irradiated with a laser to convert the a-Si layer into a polycrystalline p-Si layer. It is changing. After crystallization, a p-Si layer is formed at a required position through exposure, development, and etching processes. Further, the a-Si layer covering the p-Si layer also forms an a-Si layer at a required position through exposure, development, and etching processes. For this reason, two steps of exposure, development, and etching are required.
  • the present invention has been made in view of such circumstances, and an object thereof is to provide a method of manufacturing a thin film transistor, a thin film transistor, and a display panel including the thin film transistor, which can shorten the manufacturing process.
  • the method of manufacturing a thin film transistor according to the present invention includes a step of forming a gate electrode on a surface of a substrate, a step of forming an insulating film on the surface of the substrate on which the gate electrode is formed, A step of forming a first amorphous silicon layer on the surface of the formed substrate; and annealing for irradiating an energy beam to a plurality of required locations separated from the first amorphous silicon layer to change the required locations to a polysilicon layer. Forming a second amorphous silicon layer covering the polysilicon layer, forming an n + silicon layer on the surface of the second amorphous silicon layer, and forming a required pattern on the n + silicon layer.
  • Etching, and forming a source electrode and a drain electrode on the n + silicon layer after the etching, and the annealing step includes at least one of the source electrode and the drain electrode on the surface of the substrate.
  • An energy beam is irradiated at the projected position so as not to overlap the plurality of required portions.
  • a gate electrode is formed on the surface of the substrate, and an insulating film is formed on the surface of the substrate on which the gate electrode is formed.
  • a first amorphous silicon layer (a-Si film) is formed on the surface of the substrate on which the insulating film is formed.
  • an energy beam is irradiated to a plurality of required portions separated from each other in the first amorphous silicon layer to change the required portions into a polysilicon layer (poly-Si film). Each required portion is above the gate electrode and is a channel region between the source and the drain.
  • the energy beam for example, an ultraviolet excimer laser having a large absorption of an amorphous silicon layer (a-Si film) can be used.
  • the laser light When laser light from a laser light source is incident on, for example, a multi-lens array, the laser light is partially irradiated to each required portion via a different optical path for each lens. As a result, only the region (a plurality of spaced apart required portions) that becomes the channel region in the first amorphous silicon layer is selectively changed to the polysilicon layer (poly-Si film).
  • a second amorphous silicon layer is formed so as to cover the polysilicon layer that has become polycrystalline due to the annealing process, and an n + silicon layer is formed on the surface of the second amorphous silicon layer.
  • the n + silicon layer (n + Si film) is a contact layer with the source electrode and the drain electrode, and is a semiconductor layer having a high impurity concentration such as phosphorus or arsenic.
  • a required pattern is formed on the n + silicon layer.
  • the required pattern can be appropriately determined according to the arrangement or structure of the source electrode, the drain electrode, and the semiconductor layer.
  • the first amorphous silicon layer, the second amorphous silicon layer, and the n + silicon layer are etched, and a source electrode and a drain electrode are formed on the etched n + silicon layer.
  • the amorphous silicon layer formed on the entire surface of the substrate is irradiated with an energy beam (for example, a laser) over the entire surface of the substrate to change the polysilicon layer, and then the polysilicon layer is exposed, developed and etched.
  • an energy beam for example, a laser
  • the channel region of the first amorphous silicon layer is not irradiated with the energy beam (for example, laser) over the entire surface of the substrate. Since the energy beam is partially irradiated only on the region to be formed, the channel region can be formed only by the annealing process. For this reason, the steps of exposure, development and etching for forming the channel region are not necessary, and the manufacturing process can be shortened.
  • an energy beam is irradiated so that at least one of the source electrode and the drain electrode does not overlap the plurality of required portions at a position projected onto the surface of the substrate.
  • a second amorphous silicon layer is formed so as to cover the polysilicon layer which is a channel region, and a source electrode and a drain electrode are formed on the second amorphous silicon layer via an n + silicon layer. That is, the second amorphous silicon layer is for preventing the source and drain electrodes and the channel region from being in direct contact with each other, and has a characteristic that leakage current (leakage current) is small. By preventing at least one of the source electrode and the drain electrode and the position where the required portion is projected onto the surface of the substrate from overlapping, the leakage current can be further reduced.
  • the thin film transistor according to the present invention includes a gate electrode formed on a surface of a substrate, a polysilicon layer formed on the gate electrode, an amorphous silicon layer formed on the polysilicon layer, and n + A silicon layer, and a source electrode and a drain electrode formed on the n + silicon layer, wherein at least one of the source electrode and the drain electrode and the position where the polysilicon layer is projected onto the surface of the substrate do not overlap It is characterized by the above.
  • the thin film transistor includes a gate electrode formed on the surface of the substrate, a polysilicon layer (poly-Si film) formed on the upper side of the gate electrode, and an amorphous formed on the upper side of the polysilicon layer.
  • a silicon layer (a-Si film) and an n + silicon layer (n + Si film), and a source electrode and a drain electrode formed on the n + silicon layer are provided.
  • the polysilicon layer is a channel region.
  • the n + silicon layer is a contact layer with the source electrode and the drain electrode, and is a semiconductor layer having a high impurity concentration such as phosphorus or arsenic. The positions where at least one of the source electrode and the drain electrode and the polysilicon layer are projected onto the surface of the substrate do not overlap.
  • the amorphous silicon layer is intended to prevent direct contact between the source and drain electrodes and the channel region, and has a characteristic of low leakage current (leakage current). By preventing at least one of the source electrode and the drain electrode and the position where the polysilicon layer is projected onto the surface of the substrate from overlapping, the leakage current can be further reduced.
  • the amorphous silicon layer is formed around the polysilicon layer and has a first amorphous silicon layer having a thickness comparable to the thickness of the polysilicon layer, the polysilicon layer, and the first layer. And a second amorphous silicon layer formed on the surface of the amorphous silicon layer.
  • the amorphous silicon layer includes the first amorphous silicon layer formed around the polysilicon layer and having a thickness approximately equal to the thickness of the polysilicon layer, the polysilicon layer, and the first amorphous silicon layer. And a second amorphous silicon layer formed on the surface. That is, the polysilicon layer is obtained by changing only the region corresponding to the channel region of the first amorphous silicon layer formed on the upper side of the gate electrode into a polysilicon layer in a polycrystalline state. It can be seen that the exposure, development, and etching processes are not performed to form the film.
  • the second amorphous silicon layer is for preventing direct contact between the source and drain electrodes and the channel region, and has a characteristic that leakage current (leakage current) is small.
  • the thin film transistor according to the present invention is characterized in that a boundary surface between the polysilicon layer and the first amorphous silicon layer is substantially perpendicular to the surface of the substrate.
  • the boundary surface between the polysilicon layer and the first amorphous silicon layer is substantially perpendicular to the surface of the substrate. That is, since the line width on the gate electrode side of the polysilicon layer does not become wider than the line width on the source electrode and drain electrode side, at least one of the source electrode and the drain electrode is projected to the surface of the substrate. Thus, it is easy to avoid overlapping the polysilicon layer. In addition, since the gate insulating film in the channel region is not exposed to etching, deterioration of TFT characteristics can be suppressed.
  • the display panel according to the present invention includes the thin film transistor according to the above-described invention.
  • a display panel capable of shortening the manufacturing process can be provided.
  • the exposure, development, and etching processes can be deleted by one process, and the manufacturing process can be shortened.
  • FIG. 11 is an explanatory diagram illustrating an example of Vg-Id characteristics of the thin film transistor of this embodiment.
  • FIG. 1 is a schematic cross-sectional view of an essential part showing a first example of the structure of the thin film transistor of the present embodiment.
  • a thin film transistor TFT: Thin Film Transistor, also referred to as a TFT substrate
  • a gate electrode 2 formed on the surface of a glass substrate 1 (also referred to as a substrate) and covers the gate electrode 2 to provide gate insulation.
  • a film 3 (for example, a SiO 2 film, a SiO 2 / SiN film stack, a SiN film, etc.) is formed.
  • a polysilicon layer (poly-Si film) 5 is formed on the surface of the gate insulating film 3 and above the gate electrode 2.
  • a first amorphous silicon layer (a-Si film) 4 having the same thickness as the polysilicon layer 5 is formed.
  • a second amorphous silicon layer (a-Si film) 6 is formed on the surfaces of the polysilicon layer 5 and the first amorphous silicon layer 4.
  • the first amorphous silicon layer 4 and the second amorphous silicon layer 6 are collectively referred to simply as an amorphous silicon layer.
  • n + silicon layer (n + Si film) 7 is formed at a required position on the surface of the second amorphous silicon layer 6.
  • the n + silicon layer 7 is a contact layer with the source electrode 8 and the drain electrode 9 and is a semiconductor layer having a high impurity concentration such as phosphorus or arsenic.
  • a source electrode 8 and a drain electrode 9 having a required pattern are formed on the surface of the n + silicon layer 7, the side surfaces of the second amorphous silicon layer 6 and the first amorphous silicon layer 4, and the surface of the gate insulating film 3. is there.
  • the polysilicon layer 5 corresponds to a channel region. Further, the first amorphous silicon layer 4, the second amorphous silicon layer 6, and the polysilicon layer 5 are collectively referred to as a semiconductor layer.
  • a TFT including a gate electrode 2, a semiconductor layer, a source electrode 8, a drain electrode 9, and the like shown in FIG. 1 is a TFT for a driving circuit for driving a pixel. Since the TFT for the driving circuit is required to operate at high speed, the polysilicon layer 5 having a high electron mobility is used in the channel region.
  • a passivation film 10 made of SiN is formed on the entire TFT substrate so as to cover the source electrode 8 and the drain electrode 9, and an organic film 11 is formed on the surface of the passivation film 10 to flatten the surface. ing.
  • a through hole is formed at a required position of the passivation film 10 and the organic film 11, and the pixel electrode 12 and the drain electrode 9 (and the source electrode 8) are electrically connected through the through hole.
  • the pixel electrode 12 is made of ITO, which is a transparent conductive film.
  • the polysilicon layer 5 has a thickness approximately equal to the thickness of the surrounding first amorphous silicon layer 4, so the first amorphous silicon layer 4 formed on the upper side of the gate electrode 2.
  • the region corresponding to the channel region (a plurality of required separated points) is changed to the polysilicon layer 5 in a polycrystalline state by annealing using an energy beam (for example, a laser), It can be seen that the exposure, development and etching processes are not performed to form the polysilicon layer 5 as the channel region.
  • the boundary surface between the polysilicon layer 5 and the first amorphous silicon layer 4 is substantially perpendicular to the surface of the substrate 1. That is, if the polysilicon layer is formed by photo-etching, the side surface of the polysilicon layer does not become substantially perpendicular to the surface of the substrate 1 but has a tapered shape that becomes wider toward the gate electrode side. .
  • the polysilicon layer 5 is formed by laser annealing as in this embodiment, the line width on the gate electrode 2 side of the polysilicon layer 5 is wider than the line width on the source electrode 8 and drain electrode 9 sides.
  • the line width on the gate electrode 2 side and the line width on the source electrode 8 and drain electrode 9 side are approximately the same, so that at least one of the source electrode 8 and the drain electrode 9 is attached to the surface of the substrate 1. It is easy to avoid overlapping with the polysilicon layer 5 at the position projected onto. Further, since the gate insulating film 3 in the channel region is not exposed to etching, deterioration of TFT characteristics can be suppressed.
  • the second amorphous silicon layer 6 is for preventing the source electrode 8 and the drain electrode 9 from directly contacting the channel region, and uses a characteristic of a small leakage current (leakage current).
  • a leakage current leakage current
  • FIG. 2 is a schematic plan view of an essential part showing a first example of the structure of the thin film transistor of the present embodiment.
  • FIG. 2 for the sake of simplicity, the positional relationship of the first amorphous silicon layer 4, the polysilicon layer 5, the source electrode 8, and the drain electrode 9 in a plan view is shown.
  • a first amorphous silicon layer 4 is formed around the polysilicon layer 5.
  • a second amorphous silicon layer having substantially the same dimensions as the dimensions (vertical and horizontal dimensions) of the first amorphous silicon layer 4 is formed on the surfaces of the polysilicon layer 5 and the first amorphous silicon layer 4. 6 is formed.
  • the positions where the source electrode 8, the drain electrode 9 and the polysilicon layer 5 are projected onto the surface of the glass substrate 1 are not overlapped. Thereby, the leakage current between the source electrode 8 and the drain electrode 9 and the polysilicon layer 5 can be further reduced.
  • FIG. 3 is a manufacturing process diagram showing an example of a manufacturing method of the thin film transistor of the present embodiment.
  • the gate electrode 2 is formed on the glass substrate 1 (S11), and the gate insulating film 3 is formed on the surface of the glass substrate 1 so as to cover the gate electrode 2 (S12).
  • An a-Si film 4 as a first amorphous silicon layer is formed on the surface of the glass substrate 1 on which the gate insulating film 3 is formed (S13).
  • a dehydrogenation annealing process is performed (S14), and laser pre-cleaning is performed (S15).
  • the a-Si film 4 is crystallized by a partial irradiation type laser (S16).
  • the crystallization process is an annealing process (also referred to as a laser annealing process).
  • a required portion of the a-Si film 4 is irradiated with an energy beam through a multi-lens array, and the required portion is formed on a polysilicon layer (poly). -Si film) 5.
  • the required portion is on the upper side of the gate electrode 2 and is a channel region between the source and the drain.
  • the energy beam for example, an ultraviolet excimer laser having a large absorption of an amorphous silicon layer (a-Si film) can be used.
  • FIG. 4 is a schematic diagram showing an example of the configuration of a partial irradiation type laser.
  • the glass substrate 1 on which the a-Si film 4 is formed is placed on a mounting table (not shown) and is translated in the direction of the arrow in FIG. 4 at a required speed. is there.
  • a multi-lens array is arranged in which individual lenses are arranged at an appropriate distance along a direction intersecting the moving direction of the glass substrate 1.
  • the laser beam is partially irradiated to a plurality of required locations separated via different optical paths for each lens. That is, partial laser annealing can be performed.
  • the region serving as the channel region in the a-Si film 4 is selectively changed to the polysilicon layer (poly-Si film) 5.
  • n + Si film (n + silicon layer) 7 is formed on the surface of the a-Si film 6 (S19).
  • the n + Si film 7 is a contact layer with the source electrode 8 and the drain electrode 9 and is a semiconductor layer having a high impurity concentration such as phosphorus or arsenic.
  • the required pattern can be appropriately determined according to the arrangement or structure of the source electrode 8, the drain electrode 9, and the semiconductor layer.
  • the a-Si films 4 and 6 and the n + Si film 7 are etched (S21), and the source electrode 8 and the drain electrode 9 are formed on the n + Si film 7 after the etching (S21). S22).
  • the energy beam (for example, laser) is not irradiated on the entire surface of the substrate, but the energy beam is partially applied only to the region that becomes the channel region in the first amorphous silicon layer 4. Since the irradiation is performed, the channel region can be formed only by the annealing process. For this reason, since the channel region is formed, the exposure process, the development process, and the etching process are not required for the polysilicon layer crystallized over the entire substrate surface, and the manufacturing process can be shortened.
  • the energy beam for example, laser
  • an energy beam is irradiated to a required portion so that the positions where at least one of the source electrode 8 and the drain electrode 9 and the channel region are projected onto the surface of the glass substrate 1 do not overlap.
  • a second amorphous silicon layer 6 is formed so as to cover the polysilicon layer 5 which is a channel region, and a source electrode 8 and a drain electrode 9 are formed above the second amorphous silicon layer 6 via an n + silicon layer 7. is there. That is, the second amorphous silicon layer 6 is for preventing the source electrode 8 and the drain electrode 9 from directly contacting the channel region, and has a characteristic of a small leakage current (leakage current). By preventing the position where at least one of the source electrode 8 and the drain electrode 9 and the polysilicon layer 5 are projected onto the surface of the glass substrate 1 from overlapping, the leakage current can be further reduced.
  • FIG. 5 is a schematic cross-sectional view of the relevant part showing a second example of the structure of the thin film transistor of the present embodiment
  • FIG. 6 is a schematic plan view of the relevant part showing a second example of the structure of the thin film transistor of the present embodiment.
  • the polysilicon layer 5 as the channel region is located closer to the source electrode 8 side than in the first embodiment. That is, as shown in FIG. 6, the positions where the drain electrode 9 and the polysilicon layer 5 are projected onto the surface of the glass substrate 1 are not overlapped. Thereby, the leakage current between the drain electrode 9 and the polysilicon layer 5 can be further reduced.
  • FIG. 7 is a schematic cross-sectional view of an essential part showing a third example of the structure of the thin film transistor of the present embodiment
  • FIG. 8 is a schematic plan view of an essential part of the third example of the structure of the thin film transistor of the present embodiment. is there.
  • the polysilicon layer 5 as the channel region is located closer to the drain electrode 9 than in the first embodiment. That is, as shown in FIG. 8, the positions where the source electrode 8 and the polysilicon layer 5 are projected onto the surface of the glass substrate 1 are prevented from overlapping. Thereby, the leakage current between the source electrode 8 and the polysilicon layer 5 can be further reduced.
  • the leakage current can be further reduced by preventing the position where at least one of the source electrode 8 and the drain electrode 9 and the polysilicon layer 5 are projected onto the surface of the glass substrate 1 from overlapping. .
  • FIG. 9 is an explanatory diagram showing an example of the Vg-Id characteristics of the thin film transistor of this embodiment.
  • the horizontal axis indicates Vg (gate voltage), and the vertical axis indicates Id (drain current).
  • 9 is a conventional TFT as shown in FIGS. 10 and 11 to be described later, in which the channel region is a polysilicon layer, and the source electrode, the drain electrode, and the polysilicon layer are glass substrates. When projected onto the surface, the characteristics are exhibited when a part of each of the source and drain electrodes and a part of the polysilicon layer overlap.
  • the curve indicated by the symbol B in FIG. 9 shows the characteristics of a conventional TFT in which the channel region is composed of an amorphous silicon layer.
  • the polarity indicated by symbol C in the figure indicates the characteristic in the case of the second example of the present embodiment.
  • a TFT having a structure in which a part of each of the source electrode and the drain electrode and a part of the polysilicon layer overlap is a TFT having a channel region formed by an amorphous silicon layer (reference symbol B).
  • reference symbol A a TFT having a channel region formed by an amorphous silicon layer
  • reference symbol B a TFT having a channel region formed by an amorphous silicon layer
  • the drain current in the on state can be made larger than that of a TFT (curve B) having a channel region formed of an amorphous silicon layer.
  • the leakage current in the off state can be reduced to the same extent as in the case of a TFT (curve B) having a channel region formed of an amorphous silicon layer.
  • FIG. 10 is a schematic cross-sectional view of a main part showing the structure of a conventional thin film transistor
  • FIG. 11 is a schematic plan view of the main part showing the structure of a conventional thin film transistor.
  • a gate electrode 102 is formed on the surface of a glass substrate 101, and a gate insulating film 103 is formed so as to cover the gate electrode 102.
  • a polysilicon layer (poly-Si film) 104 is formed on the surface of the gate insulating film 103 and above the gate electrode 102.
  • An amorphous silicon layer (a-Si film) 105 is formed so as to cover the polysilicon layer 104.
  • An n + silicon layer (n + Si film) 106 is formed at a required position on the surface of the amorphous silicon layer 105.
  • a source electrode 107 and a drain electrode 108 having a required pattern are formed on the surface of the n + silicon layer 106, the side surface of the amorphous silicon layer 105, and the surface of the gate insulating film 103.
  • FIG. 12 is a manufacturing process diagram showing a conventional method for manufacturing a thin film transistor. As shown in FIG. 12, a gate electrode 102 is formed on a glass substrate 101 (S101), and a gate insulating film 103 is formed on the surface of the glass substrate 101 so as to cover the gate electrode 102 (S102).
  • An a-Si film is formed on the surface of the glass substrate 101 on which the gate insulating film 103 is formed (S103).
  • a dehydrogenation annealing process is performed (S104), and laser pre-cleaning is performed (S105).
  • the a-Si film is crystallized by the whole surface irradiation type laser (S106).
  • FIG. 13 is a schematic diagram showing an example of the configuration of the whole surface irradiation type laser.
  • the glass substrate 101 on which the a-Si film is formed is placed on a mounting table (not shown) and is moved in parallel in the direction of the arrow in FIG. 13 at a required speed.
  • a mirror having a length substantially the same as the width direction of the glass substrate 101 (direction intersecting the direction of parallel movement) is disposed.
  • the laser light is irradiated on the entire surface of the glass substrate 101.
  • the a-Si film is entirely changed to a polysilicon layer (poly-Si film).
  • n + Si film (n + silicon layer) 106 is formed on the surface of the a-Si film 105 (S111).
  • an exposure process and a development process are performed (S112), and the a-Si film 105 and the n + Si film 106 are etched (S113) to make the semiconductor layer have a required structure, and the source is formed on the n + Si film 106 after the etching.
  • the electrode 107 and the drain electrode 108 are formed (S114).
  • the amorphous silicon layer formed on the entire surface of the substrate is irradiated with an energy beam (for example, a laser) over the entire surface of the substrate to be changed into a polysilicon layer, and then the polysilicon layer is changed.
  • an energy beam for example, a laser
  • the entire surface of the substrate is not irradiated with an energy beam (for example, a laser).
  • the energy beam is partially irradiated to only the region to be the channel region in the first amorphous silicon layer, the channel region can be formed only by the annealing process. Therefore, the steps of exposure, development, and etching for forming the channel region (steps S107 and S108 shown in FIG. 12) are not required, and the manufacturing process can be shortened.
  • the thin film transistor of this embodiment can be used for a display panel. That is, the thin film transistor (TFT substrate) of this embodiment and the color filter substrate having the colors of R (red), G (green), and B (blue) are bonded to each other with a necessary gap, and the TFT substrate and the color are bonded. By injecting liquid crystal between the filter substrate, a TFT liquid crystal display panel (liquid crystal display) can be manufactured. Thereby, the display panel which can shorten a manufacturing process can be provided.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un procédé de fabrication de transistor à couches minces au moyen duquel il est possible de raccourcir le processus de fabrication, un transistor à couches minces et un écran d'affichage pourvu d'un transistor à couches minces. Le procédé de fabrication de transistor à couches minces comprend les étapes suivantes : la formation d'une électrode de grille sur la surface d'un substrat ; la formation d'un film isolant sur la surface du substrat sur laquelle l'électrode de grille a été formée ; la formation d'une première couche de silicium amorphe sur la surface du substrat sur laquelle le film isolant a été formé ; le recuit consistant à exposer à un faisceau d'énergie une pluralité d'emplacements requis et séparés sur la première couche de silicium amorphe et à provoquer la conversion des emplacements requis en une couche de polysilicium ; le revêtement de la couche de polysilicium et la formation d'une seconde couche de silicium amorphe ; la formation d'une couche de silicium n+ sur la surface de la seconde couche de silicium amorphe ; la gravure de la première couche de silicium amorphe, de la seconde couche de silicium amorphe et de la couche de silicium n+.
PCT/JP2014/079619 2014-11-07 2014-11-07 Procédé de fabrication de transistor à couches minces, transistor à couches minces et écran d'affichage Ceased WO2016072024A1 (fr)

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US15/327,615 US10038098B2 (en) 2014-11-07 2014-11-07 Method for manufacturing thin film transistor, thin film transistor and display panel

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US10770483B2 (en) 2018-06-28 2020-09-08 Sakai Display Products Corporation Thin film transistor, display device and method for manufacturing thin film transistor
US11133333B2 (en) 2018-06-28 2021-09-28 Sakai Display Products Corporation Producing method for thin film transistor with different crystallinities

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KR102365963B1 (ko) * 2015-06-23 2022-02-23 삼성디스플레이 주식회사 박막 트랜지스터, 이의 제조 방법 및 이를 갖는 액정 표시 장치
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US10672797B2 (en) * 2018-09-30 2020-06-02 Chongqing Hkc Optoelectronics Technology Co., Ltd. Array substrate, method for fabricating array substrate and display
CN113748521B (zh) * 2020-03-27 2024-09-13 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置
CN111628004A (zh) * 2020-05-18 2020-09-04 深圳市华星光电半导体显示技术有限公司 低延时薄膜晶体管、阵列基板及显示面板

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