WO2016095585A1 - 横向绝缘栅双极型晶体管及其制造方法 - Google Patents

横向绝缘栅双极型晶体管及其制造方法 Download PDF

Info

Publication number
WO2016095585A1
WO2016095585A1 PCT/CN2015/090914 CN2015090914W WO2016095585A1 WO 2016095585 A1 WO2016095585 A1 WO 2016095585A1 CN 2015090914 W CN2015090914 W CN 2015090914W WO 2016095585 A1 WO2016095585 A1 WO 2016095585A1
Authority
WO
WIPO (PCT)
Prior art keywords
type
region
oxide layer
bipolar transistor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/090914
Other languages
English (en)
French (fr)
Inventor
祁树坤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab1 Co Ltd, CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab1 Co Ltd
Priority to JP2017533196A priority Critical patent/JP6437657B2/ja
Priority to US15/537,753 priority patent/US10084073B2/en
Priority to EP15869096.6A priority patent/EP3240042B1/en
Publication of WO2016095585A1 publication Critical patent/WO2016095585A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • H10P32/1406—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/421—Insulated-gate bipolar transistors [IGBT] on insulating layers or insulating substrates, e.g. thin-film IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/417—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/418—Insulated-gate bipolar transistors [IGBT] having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region

Definitions

  • the present invention relates to a semiconductor process, and more particularly to a lateral insulated gate bipolar transistor, and to a method of fabricating a lateral insulated gate bipolar transistor.
  • Lateral Insulated-Gate Bipolar Transistor (Lateral Insulated-Gate Bipolar Transistor, LIGBT) is commonly used in the output stage of high voltage power drive integrated circuits.
  • LIGBT Lateral Insulated-Gate Bipolar Transistor
  • the conductance modulation effect brings about a low on-state voltage drop, it is accompanied by a problem that the off-time is long due to residual minority carriers in the drift region, so how to balance the on-state voltage drop and turn-off time , become the direction of continuous improvement of LIGBT devices.
  • a lateral insulated gate bipolar transistor comprising a substrate, an anode end and a cathode end on the substrate, and a drift region and a gate between the anode end and the cathode end, the anode end including a P on the substrate a buried layer, an N-type buffer on the P-type buried layer, and a P+ collector region on the surface of the N-type buffer;
  • the laterally insulated gate bipolar transistor further includes a trench gate, the trench gate from the N A type of buffer region and a P+ collector region extend through the P-type buried layer, the trench gate including an oxide layer on the inner surface of the trench and polysilicon filled in the oxide layer.
  • a method of fabricating a laterally insulated gate bipolar transistor comprising the steps of: providing a substrate formed with a drift region; forming a P-type buried layer in the drift region by high energy ion implantation of P-type ions; above the P-type buried layer Injecting N-type ions to form an N-type buffer; thermally pushing the well to diffuse the implanted P-type ions and N-type ions; injecting P-type ions and thermally annealing to form a P-type body region; photolithography and etching are formed from the N-type a buffer surface penetrating the trench of the P-type buried layer; forming an oxide layer on an inner surface of the trench; filling the oxide layer with polysilicon; ion implantation to form a P+ collector region on the surface of the N-type buffer region, And a P+ region and an N+ region of the surface of the P-type body region, the P+ collector region being in contact with the oxide layer.
  • the P+ region of the collector is reversely biased with the trench gate, the parasitic PMOS is turned on and is in an amplified state, and the remaining minority carriers in the drift region are started to be extracted ( Hole), by adjusting the thickness of the gate oxide, can control the withstand voltage of the device, and ensure a faster switching speed for fast shutdown.
  • FIG. 1 is a schematic cross-sectional view of a laterally insulated gate bipolar transistor in an embodiment
  • FIG. 2 is a flow chart showing a method of fabricating a laterally insulated gate bipolar transistor in an embodiment.
  • FIG. 1 is a schematic cross-sectional view of a laterally insulated gate bipolar transistor including a substrate 10, an anode terminal and a cathode terminal on a substrate 10 between an anode end and a cathode end, in an embodiment.
  • the anode terminal includes a P-type buried layer 52 on the substrate, an N-type buffer region 54 on the P-type buried layer 52, and a P+ collector region 56 on the surface of the N-type buffer region 54.
  • the cathode end includes a P-type body region 42 on the substrate 10, a P+ region 44 and an N+ region 46 on the surface of the P-type body region 42, and a cathode metal 41 as an electrode of the emitter.
  • the gate 61 includes a gate oxide layer and a polysilicon gate.
  • the trench gate penetrates from the surface of the N-type buffer 54 and the P+ collector region 56 to the P-type buried layer 52.
  • the trench gate includes an oxide layer 51 on the inner surface of the trench and polysilicon 53 filled in the oxide layer 51.
  • the lateral insulated gate bipolar transistor forms a vertical P-channel MOSFET through the P+ collector region 56, the N-type buffer layer 54, the P-type buried layer 52, and the oxide layer 51 and the polysilicon 53 (wherein the oxide layer 51 functions as gate oxide, Polysilicon 53 is used as a polysilicon gate).
  • the gate 61 of the laterally insulated gate bipolar transistor is positively biased, the electron current passes through the channel of the P-type body region 42 from the N+ region 46 of the emitter to the drift region 30 and the N-type buffer region 54.
  • the laterally insulated gate bipolar transistor enters an operational state.
  • the parasitic vertical PMOSFET is in an off state because the trench gate is connected to the anode terminal.
  • the lateral IGBT When the lateral IGBT is turned off, the P+ region 56 of the collector is reverse biased with the trench gate, the vertical P-channel MOSFET is turned on and in an amplified state, and the remaining minority carrier current in the drift region 30 is started to be extracted. Sub (hole).
  • the thickness of the gate oxide oxide layer 51
  • the device withstand voltage can be controlled, and a faster switching speed can be ensured to achieve a fast turn-off.
  • the gate oxide thickness is too thin, the trench gate has a strong inversion capability to the channel formed by the N-type buffer 54/drift region 30, and the parasitic vertical PMOS has a faster switching speed, but is affected by the electric field of the oxide layer 51.
  • the device withstand voltage is low; conversely, if the gate oxide thickness is too thick, the device withstand voltage is high, but the switching speed is reduced, which is not conducive to the life control of minority carriers in the LIGBT device.
  • the thickness of the oxide layer 51 is 800 angstroms to 2000 angstroms.
  • the device has a forward blocking voltage of 600V and a reverse blocking voltage of minus 40V.
  • the depth of the N-type buffer region 54 is insufficient to reach the P-type buried layer 52, so that the P-type buried layer 52 and the N-type buffer layer 54 are separated by the drift region 30.
  • Silicon-on-insulator (SOI) technology is gaining increasing importance in HVIC and SPIC applications, while IGBT devices are low on-resistance due to high input impedance and conductance modulation effects in power device applications. Increasingly important. Compared with bulk silicon isolation devices, SOI's LIGBT devices have low leakage, low on-resistance, high input impedance, high package density, fast switching, significant noise reduction and feasible under high temperature operation due to slot isolation. Sexuality, a wider range of applications in automotive electronics, home electronics and communications and industrial applications. The LIGBT shown in FIG.
  • SOI-LIGBT silicon-on-insulator type lateral insulated gate bipolar transistor
  • a method for fabricating a laterally insulated gate bipolar transistor in an embodiment for preparing the lateral insulated gate bipolar transistor includes the following steps:
  • a silicon wafer is formed on a drift region formed on a substrate, a buried oxide layer on the substrate, and a buried oxide layer.
  • high energy ions are implanted into the P-type ions to form a P-type buried layer in the drift region.
  • Injection at the anode end requires high energy ion implantation because of the high requirements for implant depth. Boron ions are implanted in this embodiment.
  • the hot push well diffuses the implanted P-type ions and N-type ions.
  • a longitudinal N-type buffer and a P-type buried layer are formed, and a P-type buried layer is formed on the buried oxide layer.
  • a P-type body region is formed at the cathode end to serve as a base region of the LIGBT.
  • etching is performed using a reactive ion etching (RIE) process.
  • RIE reactive ion etching
  • an oxide layer is formed as a gate oxide of the PMOSFET on both the sidewall and the bottom surface of the trench by thermal oxidation.
  • the polysilicon gate in the trench is formed as a gate of the PMOS by a deposition process, and the polysilicon gate between the cathode terminal and the anode terminal is formed as a gate of the LIGBT.
  • S290, ion implantation forms a P+ collector region on the surface of the N-type buffer region, and a P+ region and an N+ region on the surface of the P-type body region.
  • the emitter, the collector, and the drain of the P-channel MOSFET are formed, wherein the P+ collector region is in contact with the oxide layer in the trench and serves as the drain of the P-channel MOSFET.

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)

Abstract

提供了一种横向绝缘栅双极型晶体管(LIGBT)，包括衬底(10)、衬底(10)上的阳极端和阴极端，以及位于阳极端与阴极端之间的漂移区(30)和栅极(61)，阳极端包括衬底(10)上的P型埋层(52)、P型埋层(52)上的N型缓冲区(54)以及N型缓冲区(54)表面的P+集电区(56)；横向绝缘栅双极型晶体管还包括与阳极端邻接的沟槽栅极，沟槽栅极从N型缓冲区(54)和P+集电区(56)表面贯穿至P型埋层(52)，沟槽栅极包括沟槽内表面的氧化层(51)和填充于氧化层内的多晶硅(53)。还提供了一种横向绝缘栅双极型晶体管的制造方法。当LIGBT关断时，集电极的P+区与沟槽栅极为反向偏置，寄生PMOS开启并处于放大状态，开始抽取漂移区中残余的少子空穴，通过栅氧的厚度可控制器件耐压，并保证较快的开关速度，达到快速关断的目的。

Description

横向绝缘栅双极型晶体管及其制造方法
【技术领域】
本发明涉及半导体工艺，特别是涉及一种横向绝缘栅双极型晶体管，还涉及一种横向绝缘栅双极型晶体管的制造方法。
【背景技术】
横向绝缘栅双极型晶体管（Lateral Insulated-Gate Bipolar Transistor, LIGBT）常用于高压功率驱动集成电路的输出级。在电导调制效应带来低导通压降的同时，会伴随漂移区中由于残留少数载流子导致的关断时间偏长的问题，因此如何在开态压降和关断时间之间取得平衡，成为LIGBT器件持续改进的方向。
【发明内容】
基于此，有必要提供一种能够快速关断的横向绝缘栅双极型晶体管及其制造方法。
一种横向绝缘栅双极型晶体管，包括衬底、衬底上的阳极端和阴极端，以及位于阳极端与阴极端之间的漂移区和栅极，所述阳极端包括衬底上的P型埋层、P型埋层上的N型缓冲区以及N型缓冲区表面的P+集电区；所述横向绝缘栅双极型晶体管还包括沟槽栅极，所述沟槽栅极从N型缓冲区和P+集电区表面贯穿至所述P型埋层，所述沟槽栅极包括沟槽内表面的氧化层和填充于所述氧化层内的多晶硅。
一种横向绝缘栅双极型晶体管的制造方法，包括下列步骤：提供形成有漂移区的衬底；高能离子注入P型离子在漂移区内形成P型埋层；在所述P型埋层上方注入N型离子，形成N型缓冲区；热推阱使注入的P型离子和N型离子扩散；注入P型离子并热退火形成P型体区；光刻并刻蚀形成自所述N型缓冲区表面贯穿至所述P型埋层的沟槽；在所述沟槽的内表面形成氧化层；在所述氧化层内填充多晶硅；离子注入形成N型缓冲区表面的P+集电区，以及所述P型体区表面的P+区和N+区，所述P+集电区与所述氧化层接触。
上述横向绝缘栅双极型晶体管，当LIGBT关断时，集电极的P+区与沟槽栅极为反向偏置，寄生PMOS开启并处于放大状态，开始抽取漂移区中残余的少数载流子（空穴），通过调整栅氧的厚度可控制器件耐压，并保证较快的开关速度，达到快速关断的目的。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中横向绝缘栅双极型晶体管的截面示意图；
图2是一实施例中横向绝缘栅双极型晶体管的制造方法的流程图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
图1是一实施例中横向绝缘栅双极型晶体管的截面示意图，横向绝缘栅双极型晶体管包括衬底10、衬底10上的阳极端和阴极端，位于阳极端与阴极端之间的漂移区30和栅极61，以及沟槽栅极。阳极端包括衬底上的P型埋层52、P型埋层52上的N型缓冲区54以及N型缓冲区54表面的P+集电区56。阴极端包括衬底10上的P型体区42，P型体区42表面的P+区44和N+区46，以及作为发射极的电极的阴极金属41。栅极61包括栅氧化层和多晶硅栅。沟槽栅极从N型缓冲区54和P+集电区56表面贯穿至P型埋层52，沟槽栅极包括沟槽内表面的氧化层51和填充于氧化层51内的多晶硅53。
上述横向绝缘栅双极型晶体管，通过P+集电区56、N型缓冲区54、P型埋层52以及氧化层51和多晶硅53形成纵向的P沟道MOSFET（其中氧化层51作为栅氧、多晶硅53作为多晶硅栅）。当横向绝缘栅双极型晶体管的栅极61正偏时，电子电流由发射极的N+区46穿过P型体区42的沟道先后进入漂移区30、N型缓冲区54。随着阳极端P+区56正偏，空穴由集电极注入漂移区30，并由于电子的吸引进入P型体区42，横向绝缘栅双极型晶体管进入工作状态。此时寄生的纵向PMOSFET由于沟槽栅极与阳极端相连，故处于关断状态。
当横向绝缘栅双极型晶体管关断时，集电极的P+区56与沟槽栅极为反向偏置，纵向P沟道MOSFET开启并处于放大状态，开始抽取漂移区30中残余的少数载流子（空穴）。通过调整栅氧（氧化层51）的厚度可控制器件耐压，并保证较快的开关速度，达到快速关断的目的。栅氧厚度过薄，沟槽栅极对N型缓冲区54/漂移区30形成的沟道的反型能力较强，寄生的纵向PMOS有较快的开关速度，但受氧化层51的电场影响，器件耐压偏低；反之，栅氧厚度过厚，则器件耐压较高，但开关速度下降，不利于LIGBT器件中少数载流子的寿命控制。综合理论分析及实践应用，在其中一个实施例中，氧化层51的厚度为800埃~2000埃。具体地，在一个氧化层51的厚度为1000埃的实施例中，器件具有600V正向阻断电压和负40V的反向阻断电压。
在图1所示实施例中，N型缓冲区54的深度不足以到达P型埋层52，故P型埋层52和N型缓冲区54之间被漂移区30分隔开。
绝缘体上硅（SOI）技术正在HVIC及SPIC应用领域体现出愈来愈大的重要性，而IGBT器件则由于高输入阻抗及电导调制效应带来的低导通电阻特性，在功率器件应用领域中日益占据重要地位。相比于体硅结隔离型器件，SOI的LIGBT器件由于槽式隔离带来的低漏电、低开态电阻、高输入阻抗、高封装密度、快速开关、降噪效果显著及高温工作下的可行性，在汽车电子、家用电子及通信和工业应用上取得较为广泛的应用。图1所示的LIGBT为绝缘体上硅型横向绝缘栅双极型晶体管（SOI-LIGBT），包括位于衬底10和漂移区30之间的埋氧层20，其中衬底10为P型衬底，漂移区30为N型漂移区。
参见图2，一实施例中横向绝缘栅双极型晶体管的制造方法，用于制备上述横向绝缘栅双极型晶体管，包括下列步骤：
S210，提供形成有漂移区的衬底。
在本实施例中，是提供形成有衬底、衬底上的埋氧层及埋氧层上的漂移区上的硅片。
S220，高能离子注入P型离子以在漂移区内形成P型埋层。
在阳极端进行注入，由于对注入深度有较高的要求，因此需要采用高能离子注入的方式。在本实施例中注入的是硼离子。
S230，在P型埋层上方注入N型离子，形成N型缓冲区。
S240，热推阱使注入的P型离子和N型离子扩散。
扩散后形成纵向的N型缓冲区和P型埋层的结，P型埋层形成于埋氧层上。
S250，向漂移区内注入P型离子并热退火形成P型体区。
在阴极端注入形成P型体区，作为LIGBT的基区。
S260，光刻并刻蚀形成自N型缓冲区表面贯穿至P型埋层的沟槽。
在本实施例中，是采用反应离子刻蚀（RIE）工艺进行刻蚀。
S270，在沟槽的内表面形成氧化层。
在本实施例中，通过热氧化在沟槽的侧壁和底面均形成一层氧化层作为PMOSFET的栅氧。
S280，在氧化层内填充多晶硅。
在本实施例中，通过淀积工艺形成沟槽内的多晶硅栅作为PMOS的栅极，以及形成阴极端与阳极端之间的多晶硅栅作为LIGBT的栅极。
S290，离子注入形成N型缓冲区表面的P+集电区，以及P型体区表面的P+区和N+区。
形成发射极、集电极及P沟道MOSFET的漏极，其中P+集电区与沟槽内的氧化层接触，同时作为P沟道MOSFET的漏极。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种横向绝缘栅双极型晶体管，包括衬底、设于所述衬底上的阳极端和阴极端，以及位于所述阳极端与所述阴极端之间的漂移区和栅极，所述阳极端包括设于所述衬底上的P型埋层、设于所述P型埋层上的N型缓冲区以及设于所述N型缓冲区表面的P+集电区；所述横向绝缘栅双极型晶体管还包括沟槽栅极，所述沟槽栅极从N型缓冲区和P+集电区表面贯穿至所述P型埋层，所述沟槽栅极包括沟槽内表面的氧化层和填充于所述氧化层内的多晶硅。
  2. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述P型埋层和N型缓冲区之间被所述漂移区分隔开。
  3. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述横向绝缘栅双极型晶体管为绝缘体上硅型横向绝缘栅双极型晶体管，所述横向绝缘栅双极型晶体管还包括位于衬底和漂移区之间的埋氧层，所述P型埋层设于所述埋氧层上。
  4. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述衬底为P型衬底，所述漂移区为N型漂移区。
  5. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述阴极端包括设于所述衬底上的P型体区，以及设于所述P型体区表面的P+区和N+区。
  6. 根据权利要求5所述的横向绝缘栅双极型晶体管，其特征在于，所述阴极端还包括阴极金属，所述栅极包括栅氧化层和设于所述栅氧化层上的多晶硅栅。
  7. 根据权利要求1所述的横向绝缘栅双极型晶体管，其特征在于，所述氧化层的厚度为800埃~2000埃。
  8. 一种横向绝缘栅双极型晶体管的制造方法，包括下列步骤：
    提供形成有漂移区的衬底；
    向所述漂移区内高能离子注入P型离子，形成P型埋层；
    在所述P型埋层上方注入N型离子，形成N型缓冲区；
    热推阱使注入的P型离子和N型离子扩散；
    向所述漂移区内注入P型离子并热退火形成P型体区；
    光刻并刻蚀形成自所述N型缓冲区表面贯穿至所述P型埋层的沟槽；
    在所述沟槽的内表面形成氧化层；
    在所述氧化层内填充多晶硅；
    离子注入形成N型缓冲区表面的P+集电区，以及所述P型体区表面的P+区和N+区，所述P+集电区与所述氧化层接触。
  9. 根据权利要求8所述的方法，其特征在于，所述光刻并刻蚀形成自所述N型缓冲区表面贯穿至所述P型埋层的沟槽的步骤是采用反应离子刻蚀工艺进行刻蚀。
  10. 根据权利要求8所述的方法，其特征在于，所述在所述沟槽的内表面形成氧化层的步骤是通过热氧化形成栅氧层，所述在所述氧化层内填充多晶硅的步骤是通过淀积工艺形成多晶硅栅。
  11. 根据权利要求8所述的方法，其特征在于，所述提供形成有漂移区的衬底的步骤中，漂移区与衬底之间还形成有埋氧层；所述高能离子注入P型离子在漂移区内形成P型埋层的步骤中，P型埋层是形成于所述埋氧层上。
  12. 根据权利要求8所述的方法，其特征在于，所述高能离子注入P型离子在漂移区内形成P型埋层的步骤中，注入的离子为硼离子。
  13. 根据权利要求8所述的方法，其特征在于，所述衬底为P型衬底，所述漂移区为N型漂移区。
  14. 根据权利要求8所述的方法，其特征在于，所述P+集电区与所述沟槽内的氧化层接触，同时作为P沟道MOSFET的漏极。
PCT/CN2015/090914 2014-12-19 2015-09-28 横向绝缘栅双极型晶体管及其制造方法 Ceased WO2016095585A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2017533196A JP6437657B2 (ja) 2014-12-19 2015-09-28 横型絶縁ゲートバイポーラトランジスタ及びその製造方法
US15/537,753 US10084073B2 (en) 2014-12-19 2015-09-28 Lateral insulated-gate bipolar transistor and manufacturing method therefor
EP15869096.6A EP3240042B1 (en) 2014-12-19 2015-09-28 Lateral insulated-gate bipolar transistor and manufacturing method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410799646.0A CN105789298B (zh) 2014-12-19 2014-12-19 横向绝缘栅双极型晶体管及其制造方法
CN201410799646.0 2014-12-19

Publications (1)

Publication Number Publication Date
WO2016095585A1 true WO2016095585A1 (zh) 2016-06-23

Family

ID=56125847

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/090914 Ceased WO2016095585A1 (zh) 2014-12-19 2015-09-28 横向绝缘栅双极型晶体管及其制造方法

Country Status (5)

Country Link
US (1) US10084073B2 (zh)
EP (1) EP3240042B1 (zh)
JP (1) JP6437657B2 (zh)
CN (1) CN105789298B (zh)
WO (1) WO2016095585A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158956B (zh) * 2015-04-08 2020-02-11 无锡华润上华科技有限公司 具有resurf结构的ldmosfet及其制造方法
CN107527811B (zh) 2016-06-21 2020-07-10 无锡华润上华科技有限公司 横向绝缘栅双极型晶体管及其制造方法
CN108389900B (zh) * 2018-03-19 2020-05-26 电子科技大学 一种槽栅短路阳极soi ligbt
TW202137333A (zh) * 2020-03-24 2021-10-01 立錡科技股份有限公司 具有橫向絕緣閘極雙極性電晶體之功率元件及其製造方法
US11569378B2 (en) 2020-12-22 2023-01-31 Texas Instruments Incorporated Semiconductor on insulator on wide band-gap semiconductor
US11557673B2 (en) 2020-12-29 2023-01-17 Texas Instruments Incorporated Hybrid semiconductor device
CN114784102B (zh) * 2022-05-05 2023-05-02 电子科技大学 一种具有混合导电模式的ligbt
CN116130517A (zh) * 2022-11-23 2023-05-16 张家港意发功率半导体有限公司 一种可快速关断的ligbt及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110127602A1 (en) * 2009-12-02 2011-06-02 Alpha And Omega Semiconductor Incorporated Dual Channel Trench LDMOS Transistors and BCD Process with Deep Trench Isolation
CN102148240A (zh) * 2011-03-10 2011-08-10 电子科技大学 一种具有分裂阳极结构的soi-ligbt器件
CN102157550A (zh) * 2011-03-10 2011-08-17 杭州电子科技大学 一种具有p埋层的纵向沟道SOI LIGBT器件单元
CN102169893A (zh) * 2011-03-10 2011-08-31 杭州电子科技大学 一种具有p埋层的横向沟道soi ligbt器件单元

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100187635B1 (ko) * 1996-03-20 1999-07-01 김충환 단락 애노우드 수평형 절연 게이트 바이폴라 트랜지스터
CN1638146A (zh) * 1999-08-31 2005-07-13 松下电器产业株式会社 耐高压的绝缘体上的硅型半导体器件
JP4867251B2 (ja) * 2005-09-26 2012-02-01 トヨタ自動車株式会社 半導体装置
US7605446B2 (en) * 2006-07-14 2009-10-20 Cambridge Semiconductor Limited Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation
JP5167323B2 (ja) * 2010-09-30 2013-03-21 トヨタ自動車株式会社 半導体装置
CN103413824B (zh) * 2013-07-17 2015-12-23 电子科技大学 一种rc-ligbt器件及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110127602A1 (en) * 2009-12-02 2011-06-02 Alpha And Omega Semiconductor Incorporated Dual Channel Trench LDMOS Transistors and BCD Process with Deep Trench Isolation
CN102148240A (zh) * 2011-03-10 2011-08-10 电子科技大学 一种具有分裂阳极结构的soi-ligbt器件
CN102157550A (zh) * 2011-03-10 2011-08-17 杭州电子科技大学 一种具有p埋层的纵向沟道SOI LIGBT器件单元
CN102169893A (zh) * 2011-03-10 2011-08-31 杭州电子科技大学 一种具有p埋层的横向沟道soi ligbt器件单元

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3240042A4 *

Also Published As

Publication number Publication date
EP3240042B1 (en) 2026-04-22
EP3240042A1 (en) 2017-11-01
CN105789298A (zh) 2016-07-20
EP3240042A4 (en) 2018-09-19
US10084073B2 (en) 2018-09-25
US20180069107A1 (en) 2018-03-08
JP6437657B2 (ja) 2018-12-12
JP2018505549A (ja) 2018-02-22
CN105789298B (zh) 2019-06-07

Similar Documents

Publication Publication Date Title
WO2016095585A1 (zh) 横向绝缘栅双极型晶体管及其制造方法
US11121242B2 (en) Method of operating a semiconductor device having a desaturation channel structure
CN104332495B (zh) 一种绝缘栅双极晶体管及其制造方法
US10770572B2 (en) Lateral insulated-gate bipolar transistor and manufacturing method therefor
CN106098762A (zh) 一种rc‑igbt器件及其制备方法
WO2016064923A1 (en) Bidirectional power switching with bipolar conduction and with two control terminals gated by two merged transistors
CN106024892A (zh) 高雪崩耐量的空穴电流分流型功率晶体管及其制备方法
CN106067481A (zh) 一种双通道rc‑igbt器件及其制备方法
JP6430650B2 (ja) 横型絶縁ゲートバイポーラトランジスタ
US9245986B2 (en) Power semiconductor device and method of manufacturing the same
CN110504315B (zh) 一种沟槽型绝缘栅双极晶体管及其制备方法
TWI532179B (zh) 垂直式絕緣閘雙極電晶體及其製造方法
CN117352540A (zh) 半导体器件和半导体器件的控制方法以及制备方法
CN105226089A (zh) 一种igbt芯片及其制作方法
CN105097903A (zh) 绝缘体上硅的横向n型绝缘栅双极晶体管
CN103872134A (zh) 功率半导体器件及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15869096

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017533196

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 15537753

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2015869096

Country of ref document: EP