WO2016106548A1 - Appareil de récupération d'horloge - Google Patents

Appareil de récupération d'horloge Download PDF

Info

Publication number
WO2016106548A1
WO2016106548A1 PCT/CN2014/095520 CN2014095520W WO2016106548A1 WO 2016106548 A1 WO2016106548 A1 WO 2016106548A1 CN 2014095520 W CN2014095520 W CN 2014095520W WO 2016106548 A1 WO2016106548 A1 WO 2016106548A1
Authority
WO
WIPO (PCT)
Prior art keywords
output
signal
phase error
clock phase
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/095520
Other languages
English (en)
Chinese (zh)
Inventor
万文通
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN201480084399.4A priority Critical patent/CN107113159B/zh
Priority to PCT/CN2014/095520 priority patent/WO2016106548A1/fr
Publication of WO2016106548A1 publication Critical patent/WO2016106548A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers

Definitions

  • Embodiments of the present invention relate to communication technologies, and in particular, to a clock recovery device.
  • the receiving end needs to perform the processing of the digital domain algorithm.
  • the rate at which the receiving end performs the algorithm processing and the rate at which the transmitting end sends the data must be consistent at all times to ensure that all transmitted data are timely. It is processed, that is, the transmitting end and the receiving end must ensure clock synchronization. If the clocks of the transmitting end and the receiving end are deviated, the clock needs to be recovered to ensure that the sampling data of the receiving end is the sampling data of the optimal sampling time, so that the data of the receiving end and the transmitting end are kept synchronized.
  • FIG. 1 is a schematic structural diagram of a clock recovery device in the prior art.
  • the device includes an analog-to-digital converter (ADC) 1, a dispersion estimation and compensation circuit 2, a depolarization circuit 3, a buffer 4, and an interpolator (Interpolator). 5, the inverse tangent function and the solution overlap calculation circuit 6, Infinite Impulse Response (IRR) 7 and IIR 8, Phase Detector (PD) 9 and PD 10, low-pass filter (Low Pass Filter, LPF for short) 11, Voltage-Controlled Oscillator (VCO) 12.
  • ADC analog-to-digital converter
  • IRR Infinite Impulse Response
  • IIR Infinite Impulse Response
  • PD Phase Detector
  • PD Low-pass filter
  • LPF Low Pass Filter
  • VCO Voltage-Controlled Oscillator
  • ADC1, dispersion estimation and compensation circuit 2, depolarization circuit 3, PD 9, LPF 11 and VCO 12 form a feedback loop, which completes the low-speed adjustment of the sampling clock of ADC 1, and can handle the low-frequency jitter problem of the clock;
  • ADC1, dispersion The estimation and compensation circuit 2, the depolarization circuit 3, the PD9 and the PD10, the IIR7 and IIR8, the inverse tangent function and the de-overlapping calculation circuit 6, the Buffer4 and the Interpolator 5 form a feedforward loop, and the processing of the clock phase error signal is completed, that is, The clock signal with the error is recovered and can handle the clock high frequency jitter problem.
  • the clock recovery device in the prior art not only needs to recover the clock signal with error, but also needs to design a VCO and an LPF device in the feedback loop to adjust the sampling clock of the ADC, therefore, the circuit design is complicated, Conducive to the realization of hardware circuits.
  • the clock recovery device provided by the embodiment of the invention, when the ADC is within a certain frequency deviation range
  • the input signal is sampled, and the optimal sampling signal can be obtained at the output end of the clock recovery device, and the sampling frequency of the ADC is not required to be corrected by using a device such as a VCO, which simplifies the complexity of the circuit design and is beneficial to the realization of the hardware circuit.
  • a first aspect of the embodiments of the present invention provides a clock recovery apparatus, including: an analog to digital converter ADC, a data buffer, a digital interleaver, a clock phase error estimator, a filter, and a digital controller;
  • an output of the ADC is coupled to an input of the data buffer and a first input of the clock phase error estimator; an output of the data buffer and a first of the digital interleaver An input terminal is coupled; an output of the digital interleaver is coupled to a second input of the clock phase error estimator; an output of the clock phase error estimator is coupled to an input of the digital controller; An output of the digital controller is coupled to a second input of the digital interleaver;
  • the ADC is configured to sample an input signal and output a second sampling signal
  • the clock phase error estimator is configured to perform a clock phase error operation on the second sampling signal output by the ADC and the first output signal fed back by the digital interleaver to obtain a clock phase error signal;
  • the first output signal is an output signal corresponding to the first sampling signal, and the first sampling signal is a previous adjacent sampling signal of the second sampling signal;
  • the digital controller is configured to acquire interpolated information according to the clock phase error signal, where the interpolated information includes an interpolated signal index of the second sampling signal and an interpolated phase of the second sampling signal;
  • the data buffer is configured to store all sampling signals output by the ADC, so that the second sampling signal entering the digital interleaver corresponds to the interpolated information
  • the digital interleaver is configured to adjust the second sampling signal output by the data buffer according to the interpolated information output by the digital controller, so that the acquired second output signal is The output signal at the best sampling time.
  • the clock recovery apparatus further includes a filter
  • An input of the filter is coupled to an output of the clock phase error estimator, and an output of the filter is coupled to an input of the digital controller;
  • the filter is configured to perform high frequency filtering on the clock phase error signal output by the clock phase error estimator, and output the filtered clock phase error signal.
  • the clock phase error estimator comprises a data buffer module, a first calculation module, a second calculation module, a first amplifier, a second amplifier and an adder;
  • the input end of the data cache module is connected to the output end of the ADC, and the output end of the data cache module is connected to the input end of the first calculation module; the output end of the first calculation module is a first input terminal of the first amplifier is connected; an input end of the second calculation module is connected to an output end of the digital interleaver, an output end of the second calculation module and an input end of the second amplifier Connecting; the output of the second amplifier is coupled to the second input of the adder, and the output of the adder is coupled to the filter;
  • the data buffering module is configured to store a sampling signal output by the ADC, so that the sampling signal entering the digital interleaver and the interpolated information of the sampling signal correspond to each other;
  • the first calculating module is configured to calculate an average clock phase deviation of the second sampling signal
  • the second calculating module is configured to calculate an average clock phase deviation of the first output signal.
  • the first calculating module includes a Fourier transform unit, an extended unit, an accumulating unit, an angle unit, and a normalization unit;
  • the input end of the Fourier transform unit is connected to an output end of the data buffer module, and an output end of the Fourier transform unit is connected to an input end of the expansion unit; an output end of the expansion unit Connected to an input end of the accumulating unit; an output end of the accumulating unit is connected to an input end of the angle unit; an output end of the angle unit is connected to an input end of the normalization unit; An output of the unit is coupled to an input of the first amplifier;
  • the Fourier transform unit is configured to perform Fourier transform on the N sampling signal output by the data buffer module, and output a complex value sequence of the sampling signal; wherein N is a positive integer greater than or equal to 1;
  • the expansion unit is configured to expand the complex value sequence and output the expanded complex value sequence
  • the accumulating unit is configured to calculate an average value of a clock phase error of the second sampling signal according to the expanded complex value sequence
  • the angle unit is configured to calculate a clock phase error angle of the second sampling signal according to an average value of the clock phase error of the second sampling signal output by the accumulating unit;
  • the normalization unit is configured to perform normalization processing on the clock phase error angle output by the angle unit, and output an average clock phase deviation of the second sampling signal.
  • the clock recovery apparatus further includes a disturbance polarization controller
  • a first input of the disturbance polarization controller is coupled to an output of the ADC, and a second input of the disturbance polarization controller is coupled to an output of the clock phase error estimator, the disturbance polarization controller
  • the output ends are respectively connected to the input of the data buffer and the first input of the clock phase error estimator;
  • the disturbance polarization controller is configured to cancel interference between two sampling signals simultaneously output by the ADC.
  • the clock recovery apparatus further includes a polarization equalizer
  • An input end of the polarization equalizer is connected to the ADC, and an output end of the polarization equalizer is respectively connected to an input end of the data buffer and a first input end of the clock phase error estimator;
  • the polarization equalizer is configured to perform time domain convolution on the sampling signal output by the ADC according to a dispersion equalization coefficient to eliminate interference between two sampling signals simultaneously output by the ADC.
  • the clock recovery device acquires a clock phase error signal of the sampling signal and the output signal by using a clock phase error estimator, and the interpolated signal index and the interpolating signal including the second sampling signal are acquired by the digital controller according to the clock phase error signal.
  • the digital interleaver corrects the second sampling signal output by the data buffer according to the interpolated signal index and the interpolated phase to obtain the corrected optimal sampling signal, that is, the second output signal, when the ADC
  • the input signal is sampled within a certain frequency deviation range, and the optimal sampling signal can be obtained at the output end of the clock recovery device, and the sampling frequency of the ADC is not required to be corrected by using a device such as a VCO, which simplifies the complexity of the circuit design. It is conducive to the realization of hardware circuits.
  • FIG. 1 is a schematic structural diagram of a clock recovery device in the prior art
  • FIG. 2 is a schematic structural diagram of a clock recovery apparatus according to Embodiment 1 of the present invention.
  • Figure 3 is a schematic diagram of the interleaving principle
  • FIG. 4 is a structural diagram of a clock recovery apparatus according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a clock phase error estimator according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a first computing module according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an accumulation unit according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a second computing module according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a clock recovery apparatus according to Embodiment 3 of the present invention.
  • FIG. 10 is a schematic structural diagram of a clock recovery apparatus according to Embodiment 4 of the present invention.
  • 61 a modular unit
  • 71 a disturbance polarization controller
  • 71 a first input of the disturbance polarization controller
  • FIG. 2 is a schematic structural diagram of a clock recovery apparatus according to Embodiment 1 of the present invention. as shown in picture 2,
  • the apparatus includes an ADC 21, a data buffer 22, a digital interleaver 23, a clock phase error estimator 24, and a digital controller 25.
  • the output of the ADC 21 is coupled to the input of the data buffer 22 and the first input 26 of the clock phase error estimator 24, respectively; the output of the data buffer 22 and the first input 28 of the digital interleaver 23 Connected; the output of the digital interpolator 23 is coupled to the second input 27 of the clock phase error estimator 24; the output of the clock phase error estimator 24 is coupled to the input of the digital controller 25; the output of the digital controller 25 The terminal is connected to the second input 29 of the digital interpolator 23.
  • the ADC 21 is configured to sample the input signal and output a second sampling signal; the clock phase error estimator 24 is configured to perform clock phase on the second sampling signal output by the ADC 21 and the first output signal fed back by the digital interleaver 23.
  • the error calculation is performed to obtain a clock phase error signal, wherein the first output signal is an output signal corresponding to the first sampling signal, and the first sampling signal is a previous adjacent sampling signal of the second sampling signal;
  • the digital controller 25 is configured to The clock phase error signal acquires interpolated information; wherein the interpolated information includes an interpolated signal index of the second sampled signal and an interpolated phase of the second sampled signal; and the data buffer 22 is configured to perform all the sampled signals output by the ADC 21 Stored so that the second sampled signal entering the digital interleaver 23 corresponds to the interpolated information; the digital interleaver 23 is configured to perform the second sampled signal output by the data buffer 22 according to the interpolated information output by the digital controller 25. Adjusted so that the acquired second output signal is the output signal of the optimal sampling time.
  • the clock recovery device provided by the embodiment of the present invention can be applied to a mobile network, a microwave, a metropolitan area network, and the like.
  • the implementation principle of the clock recovery device is as follows: the input signal may be one optical signal of one polarization state after dispersion compensation, or may be other optical signals, and the input signal enters the ADC 21 for sampling, and the ADC 21 The second sampled signal is outputted to the data buffer 22 and the phase error estimator 24, respectively.
  • the clock phase error estimator calculates a clock phase error signal between the second sampling signal and the first output signal for the second sampling signal and the first output signal fed back by the digital interpolator 23, and the digital controller 25 according to the clock phase error
  • the signal acquires an interpolated signal index and an interpolated phase of the second sampled signal, and transmits an interpolated signal index and an interpolated phase of the second sampled signal to the digital interleaver 23, and the digital interleaver according to the second sampled signal
  • the interpolation signal index and the interpolated phase correct the second sampling signal to obtain the corrected sampling signal, that is, the second output signal, and the clock frequency of the second output signal and the clock rate of the second sampling signal are consistent.
  • the time when the data buffer 22 buffers the sampling signal is the sampling signal entering the time phase error estimator.
  • the time taken by the 24 to the digital interleaver 23 to output the interleaved information that is, when the second sampled signal enters the interdigital interpolator 23, the interleaving information of the second sampled signal also enters the interdigital interleaver 23 at the same time,
  • the interpolator 23 can correct the second sampled signal based on the correct interpolated information.
  • Figure 3 is a schematic diagram of the interleaving principle. As shown in Fig. 3, the horizontal axis in the middle is the time axis, and the sampling signals (m k -1) T s , m k T s , (m k +1)T s , (m k +2)T are above the time axis.
  • the sampling signal m k T s is taken as an example to illustrate the principle.
  • the clock phase error signal of the time phase error estimator 24 determines the sampling frequency or phase deviation of the m k T s sampling signal, that is, the sampling signal should not appear. In the position shown in FIG.
  • the digital controller 25 analyzes the clock phase error signal to obtain the interpolated signal index k and the interpolated phase ⁇ k , and the interpolated signal index is equivalent to marking a base point position kT i , that is, m
  • the interpolated phase ⁇ k indicates that the m k T s sampling signal deviates by ⁇ k T s
  • the digital interleaver 23 indexes and interpolates according to the interpolated signal index
  • the phase ⁇ k corrects the m k T s sampling signal, and outputs the corrected post-sampled signal to kT i + ⁇ T i , completing the clock recovery of the sampled signal.
  • the clock recovery apparatus acquires the clock phase error signal of the sampling signal and the output signal through the clock phase error estimator 24, and the interpolated signal index including the second sampling signal is acquired by the digital controller 25 according to the clock phase error signal.
  • the digital interleaver 23 corrects the second sampling signal output by the data buffer 22 according to the interpolated signal index and the interpolated phase to obtain the corrected optimal sampling signal, that is, the second output.
  • the optimal sampling signal can be obtained at the output of the clock recovery device, and the sampling frequency of the ADC is not required to be corrected by using a device such as a VCO, which simplifies the circuit.
  • the complexity of the design is conducive to the realization of the hardware circuit.
  • FIG. 4 is a structural diagram of a clock recovery apparatus according to an embodiment of the present invention. Based on the first embodiment described above, as shown in FIG. 4, the clock recovery device further includes a filter 20.
  • the input of filter 20 is coupled to the output of clock phase error estimator 24, filter 20 The output is connected to the input of the digital controller 25.
  • the filter 20 is for performing high frequency filtering on the clock phase error signal output from the clock phase error estimator 24 and outputting the filtered clock phase error signal.
  • the filter 20 is mainly used to adjust the loop bandwidth and filter out high frequency components, so that the obtained clock phase error signal is more accurate, and the filter 20 can be implemented by using a commonly used proportional integral filter.
  • FIG. 5 is a schematic structural diagram of a clock phase error estimator according to an embodiment of the present invention.
  • the clock phase error estimator 24 includes a data buffer module 31, a first calculation module 32, a second calculation module 33, a first amplifier 34, a second amplifier 35, and an adder 36.
  • the input end of the data buffer module 31 is connected to the output end of the ADC 21, and the output end of the data buffer module 31 is connected to the input end of the first calculation module 32.
  • the output end of the first calculation module 32 and the first amplifier 34 are An input terminal 37 is connected; an input terminal of the second calculation module 33 is connected to an output terminal of the digital interleaver 23, an output terminal of the second calculation module 33 is connected to an input terminal of the second amplifier 35; and an output terminal of the second amplifier 35 Connected to a second input 38 of adder 36, the output of adder 36 is coupled to filter 25.
  • the data buffering module 31 is configured to store the sampling signal output by the ADC 21 to correspond to the interpolated information of the sampling signal entering the digital interleaver and the sampling signal; the first calculating module 32 is configured to calculate the second sampling signal. The average clock phase deviation; the second calculation module 33 is configured to calculate an average clock phase deviation of the first output signal.
  • the input end of the data buffer module 31 is the first input end 26 of the clock phase error estimator 24, and the input end of the second calculating module 33 is the second end of the clock phase error estimator 24.
  • Input 27, the output of adder 36 is the output of clock phase error estimator 24.
  • the working principle of the clock phase error estimator 24 is specifically as follows: the sampling signal output by the ADC 21 enters the data buffer module 31 for storage, and the first calculating module 32 calculates the plurality of sampling signals output by the buffer data module 31. Obtaining an average clock phase deviation E1 of the second sampling signal, and performing gain adjustment through the first amplifier 34.
  • the plurality of output signals are calculated to obtain an average clock phase deviation E2 of the second output signal, and E2 is subjected to gain adjustment by the second amplifier 35.
  • the sampling signal is stored in the data buffer module 31 as x1, x2, x3, x4, x5, x6, ..., xn as an example, and the implementation manners of the first calculating module 32 and the second calculating module 33 are described in detail.
  • FIG. 6 is a schematic structural diagram of a first computing module in an embodiment of the present invention.
  • the first calculation module 32 includes a Fourier transform unit 41, an extension unit 42, an accumulation unit 43, an angle unit 44, and a normalization unit 45.
  • the input end of the Fourier transform unit 41 is connected to the output end of the data buffer module 31, the output end of the Fourier transform unit 41 is connected to the input end of the extension unit 42; the output end of the extension unit 42 and the accumulating unit 43 The input end is connected; the output end of the accumulating unit 43 is connected to the input end of the angle unit 44; the output end of the angle unit 44 is connected to the input end of the normalization unit 45; the output end of the normalization unit 45 is connected to the first amplifier 34 The input is connected.
  • the Fourier transform unit 41 is configured to perform Fourier transform on the plurality of sampled signals output by the data buffer module, and output a complex value sequence of the sampled signal;
  • the expansion unit 42 is configured to expand the complex value sequence of the sampled signal, and after the output is expanded a complex value sequence;
  • the accumulating unit 43 is configured to calculate an average value of the clock phase error of the sampled signal according to the expanded complex value sequence;
  • the angle unit 44 is configured to calculate the sampling signal according to the average value of the clock phase error of the sampled signal output by the accumulating unit
  • the normalization unit 45 is configured to normalize the clock phase error angle output by the angle unit, and output an average clock phase deviation of the sampled signal.
  • the working principle of the first calculating module 32 is specifically as follows: the Fourier transform unit 41 performs Fourier transform on the N sampling signals output by the data buffering module 31, and obtains the complex value of the N sampling signals after the transform.
  • the sequence is set to F1, F2, F3, ..., FN; the extension unit 42 performs head-to-tail expansion on F1, F2, F3, ..., FN.
  • the longer the extension length the more accurate the clock error estimation, but the more time consuming, the response The slower, the more reasonable value is needed according to the actual situation of the system.
  • the complex value sequence is F(N-1), F(N), F(1), F(2), F(3), ..., F(N), F(1), F(2);
  • accumulating unit 43 is operated on the expanded complex value to obtain an average value of the clock phase error of the sampled signal;
  • the angle unit 44 operates on the average value of the clock phase error of the sampled signal to obtain a clock phase error angle of the sampled signal;
  • the normalization unit 45 pairs
  • the clock phase error angle of the sampled signal is normalized, and the average clock phase deviation of the sampled signal is output.
  • the clock phase error angle of the sampled signal is normalized to a sampling point interval of 0-1, and if 0.1, the sampling is performed. The signal is skewed by 0.1 sample interval.
  • FIG. 7 is a schematic structural diagram of an accumulation unit according to an embodiment of the present invention.
  • the accumulating unit 43 includes an averager 51, an averager 52, a plurality of conjugate arithmetic units 53, and a plurality of multipliers 54.
  • the complex-valued sequence F(N-1), F(N), F(1),..., F(N/4-2) and complex sequence F(3N/4-2), F(3N/4-1 ), F(3N/4), ..., F(N-2) is an example to illustrate the working principle of the accumulation unit.
  • the complex sequence F(3N/4-2), F(3N/4-1), F(3N/4), ..., F(N-2) passes through the conjugate operation unit 53, and enters the multiplier 54 and the complex value.
  • the sequences F(N-1), F(N), F(1), ..., F(N/4-2) are multiplied, and the multiplied signals are returned to the averager 51 and other signals entering the averager 51. After averaging, the averaged signal enters multiplier 54 and multiplies the averaged signal of the other branch to obtain the average of the clock phase error of the sampled signal; in the other branch, it is the complex-valued sequence F.
  • complex sequence in the accumulation unit shown in FIG. 7 is not limited to the complex sequence shown in the drawing, and the number of the complex sequence, the conjugate operation unit 53 and the multiplier 54 can be adjusted according to actual conditions.
  • FIG. 8 is a schematic structural diagram of a second computing module according to an embodiment of the present invention.
  • the second calculation module 33 includes a plurality of modulo units 61, an averager 62, two subtractors 63, three power operation units 64, and a multiplier 65.
  • Y1, y2, and y3 are output signals fed back by the digital interleaver 23, and y1, y2, and y3 respectively enter the modulo unit 61 for modulo operation, and y1 and y3 are subjected to modulo operation and subtracted from the signal of the y2 modulo operation, and subtraction is performed.
  • the output signal of the processor 63 enters the power operation unit 64 to perform a power operation, and the output signal of the power operation unit 64 enters the output signal of the multiplier 65 and the subtractor 63 of the other branch.
  • the line multiplication operation obtains the average value of the clock phase error of the output signal.
  • y1 and y3 perform a modulo operation and a power operation, respectively, and then perform a subtraction operation.
  • the output signal of the subtracter 63 is multiplied with the output signal of the power operation unit 64 to obtain an average of the clock phase errors of the output signal.
  • the power operation unit 64 can set different power coefficients, for example, C1, C2, and C3 are integers greater than or equal to 1, and can be appropriately adjusted according to the system modulation format, such as Quadrature Phase Shift Keying (QPSK).
  • QPSK Quadrature Phase Shift Keying
  • FIG. 8 only takes the second calculation unit to calculate the average value of the clock phase error of the three output signals in the preset time period T, and gives a structural schematic diagram of the second calculation unit. According to the actual situation, the adjustment principle is the same as that of Figure 8.
  • the digital controller is configured to provide an interpolated signal index, such as whether the second sampling signal needs to be interpolated or the third sampling signal needs to be interpolated, and is also used to provide an interpolated phase, such as at the index position.
  • an interpolated signal index such as whether the second sampling signal needs to be interpolated or the third sampling signal needs to be interpolated
  • an interpolated phase such as at the index position.
  • the digital interleaver can also be called a digital interpolation filter or a digital interpolator.
  • the function of the data buffer is to temporarily store a sequence of sampled signals of a certain length, and a cache device of the prior art can be used.
  • FIG. 9 is a schematic structural diagram of a clock recovery apparatus according to Embodiment 3 of the present invention.
  • the clock recovery device further includes a disturbance polarization controller 70.
  • the first input 71 of the disturbance polarization controller 70 is coupled to the output of the ADC 21, and the second input 72 of the disturbance polarization controller 70 is coupled to the output of the clock phase error estimator 24 to interfere with the output of the polarization controller 70.
  • the input to data buffer 22 and the first input of clock phase error estimator 24 are coupled, respectively.
  • the disturbance polarization controller 70 is for canceling the interference between the two sampled signals simultaneously output by the ADC 21.
  • two polarization signals may interfere with each other due to polarization mode dispersion, and a disturbance polarization controller 70 may be disposed after the ADC 21. Used to eliminate the mutual interference between the two sampling signals of the output of ADC 21 Disturb.
  • the clock phase error signal output by the clock phase error estimator 24 is fed back to the disturbance polarization controller 70, and the interference polarization controller 70 performs interference cancellation on the two sampling signals until the clock phase error estimator 24 outputs the optimal output.
  • Clock phase error signal The specific implementation of the disturbance polarization controller 70 can be processed according to the intra-channel polarization mode dispersion model shown in equation (1).
  • X is the signal in the polarization direction of the light X
  • Y is the signal in the polarization direction of the light Y
  • ⁇ represents the azimuth angle of the polarized light. Indicates the elliptical angle of the polarized light.
  • the clock recovery device provided in this embodiment eliminates mutual interference between two optically polarized normal signals by setting a disturbance polarization controller, so that the phase error estimator outputs an optimal clock phase error signal to facilitate clock recovery device output.
  • Optimal sampling signal Optimal sampling signal.
  • FIG. 10 is a schematic structural diagram of a clock recovery apparatus according to Embodiment 4 of the present invention.
  • the clock recovery device further includes a polarization equalizer 73.
  • the input of the polarization equalizer 73 is connected to the ADC 21, and the output of the polarization equalizer 73 is connected to the input of the data buffer 22 and the first input 26 of the clock phase error estimator 24, respectively; the polarization equalizer 73 is used for
  • the sampled signal output from the ADC 21 is time-domain convolved according to the dispersion equalization coefficient to eliminate interference between the two sampled signals simultaneously output by the ADC.
  • two polarization signals when two optical polarization signals are simultaneously used as input signals, two polarization signals may interfere with each other due to polarization mode dispersion, and a polarization equalizer 73 may be disposed after the ADC 21 to polarize.
  • the equalizer 73 can directly perform time domain convolution on the sampled signal according to the dispersion equalization coefficient, complete the equalization of the sampled signal, and output a light polarization state signal for clock recovery after equalization, or can output two polarization state signals for two sets respectively. Used for clock recovery systems.
  • the clock recovery device provided in this embodiment provides a polarization equalization device to directly perform time domain convolution on the sampled signal according to the dispersion equalization coefficient, completes the equalization of the sampled signal, and uses the equalized signal to perform clock recovery, so that the clock recovery device outputs the most. Excellent sampling signal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un appareil de récupération d'horloge comprenant : un convertisseur analogique-numérique (CAN) (21), un tampon de données (22), un interpolateur numérique (23), un estimateur d'erreur de phase d'horloge (24), un filtre (20) et un contrôleur numérique (25). Des bornes de sortie du CAN (21) sont connectées respectivement à une borne d'entrée du tampon de données (22) et à une première borne d'entrée (26) de l'estimateur d'erreur de phase d'horloge (24); la borne de sortie du tampon de données (22) est connectée à une première borne d'entrée (28) de l'interpolateur numérique (23); la borne de sortie de l'interpolateur numérique (23) est connectée à une seconde borne d'entrée (27) de l'estimateur d'erreur de phase d'horloge (24); la borne de sortie de l'estimateur d'erreur de phase d'horloge (24) est connectée à la borne d'entrée du contrôleur numérique (25); la borne de sortie du contrôleur numérique (25) est connectée à une seconde borne d'entrée (29) de l'interpolateur numérique (23). La présente invention réduit la complexité de la conception de circuit et facilite la réalisation d'un circuit matériel.
PCT/CN2014/095520 2014-12-30 2014-12-30 Appareil de récupération d'horloge Ceased WO2016106548A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201480084399.4A CN107113159B (zh) 2014-12-30 2014-12-30 时钟恢复装置
PCT/CN2014/095520 WO2016106548A1 (fr) 2014-12-30 2014-12-30 Appareil de récupération d'horloge

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2014/095520 WO2016106548A1 (fr) 2014-12-30 2014-12-30 Appareil de récupération d'horloge

Publications (1)

Publication Number Publication Date
WO2016106548A1 true WO2016106548A1 (fr) 2016-07-07

Family

ID=56283832

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/095520 Ceased WO2016106548A1 (fr) 2014-12-30 2014-12-30 Appareil de récupération d'horloge

Country Status (2)

Country Link
CN (1) CN107113159B (fr)
WO (1) WO2016106548A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019192300A1 (fr) * 2018-04-02 2019-10-10 华为技术有限公司 Appareil et procédé de récupération de phase d'horloge, et puce
WO2020253687A1 (fr) * 2019-06-21 2020-12-24 华为技术有限公司 Dispositif de synchronisation d'horloge, émetteur optique, récepteur optique et procédé
WO2021104516A1 (fr) * 2019-11-29 2021-06-03 深圳市中兴微电子技术有限公司 Procédé et appareil de récupération de données d'horloge, détecteur de phase et support d'informations

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070009074A1 (en) * 2005-07-07 2007-01-11 Ching-Wen Ma Timing recovery apparatus and method with frequency protection
CN101820340A (zh) * 2010-02-22 2010-09-01 中兴通讯股份有限公司 一种时钟恢复装置及方法
CN102016996A (zh) * 2008-09-29 2011-04-13 艾格瑞系统有限公司 用于改进伺服数据操作的系统和方法
CN102377715A (zh) * 2010-08-12 2012-03-14 北京泰美世纪科技有限公司 一种采样时钟同步方法及装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4433438B2 (ja) * 2000-07-24 2010-03-17 日本ビクター株式会社 情報再生装置および位相同期制御装置
CN101674050B (zh) * 2009-09-21 2011-08-17 清华大学 时域并行数字解调系统

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070009074A1 (en) * 2005-07-07 2007-01-11 Ching-Wen Ma Timing recovery apparatus and method with frequency protection
CN102016996A (zh) * 2008-09-29 2011-04-13 艾格瑞系统有限公司 用于改进伺服数据操作的系统和方法
CN101820340A (zh) * 2010-02-22 2010-09-01 中兴通讯股份有限公司 一种时钟恢复装置及方法
CN102377715A (zh) * 2010-08-12 2012-03-14 北京泰美世纪科技有限公司 一种采样时钟同步方法及装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019192300A1 (fr) * 2018-04-02 2019-10-10 华为技术有限公司 Appareil et procédé de récupération de phase d'horloge, et puce
CN110351066A (zh) * 2018-04-02 2019-10-18 华为技术有限公司 时钟相位恢复装置、方法和芯片
US11212070B2 (en) 2018-04-02 2021-12-28 Huawei Technologies Co., Ltd. Clock phase recovery apparatus and method, and chip
CN110351066B (zh) * 2018-04-02 2022-03-08 华为技术有限公司 时钟相位恢复装置、方法和芯片
WO2020253687A1 (fr) * 2019-06-21 2020-12-24 华为技术有限公司 Dispositif de synchronisation d'horloge, émetteur optique, récepteur optique et procédé
US12003275B2 (en) 2019-06-21 2024-06-04 Huawei Technologies Co., Ltd. Clock synchronization apparatus, optical transmitter, optical receiver, and clock synchronization method
WO2021104516A1 (fr) * 2019-11-29 2021-06-03 深圳市中兴微电子技术有限公司 Procédé et appareil de récupération de données d'horloge, détecteur de phase et support d'informations

Also Published As

Publication number Publication date
CN107113159B (zh) 2020-02-14
CN107113159A (zh) 2017-08-29

Similar Documents

Publication Publication Date Title
JP6317467B2 (ja) クロックリカバリ方法、装置、システムおよびコンピュータ記憶媒体
JP5590090B2 (ja) 周波数オフセット補償装置及び方法並びに光コヒーレント受信機
JP6217235B2 (ja) クロック復元用の位相検出方法及び位相検出装置
CN105393487A (zh) 相干光接收器
CN104780131B (zh) 一种色度色散测量方法、装置及数字相干接收机
CN111490866A (zh) 一种高速并行解调结构中的定时恢复方法、数字通信系统
CN102064900A (zh) 一种时钟同步方法与装置
WO2016106548A1 (fr) Appareil de récupération d'horloge
CN116232558B (zh) 一种iq时延补偿方法、装置、电子设备和存储介质
CN103812594A (zh) 一种无数据辅助的并行时钟同步方法及系统
JP5733094B2 (ja) シンボルタイミングリカバリ回路
CN110351066B (zh) 时钟相位恢复装置、方法和芯片
CN106130546B (zh) 一种相位检测方法和装置
US10505768B2 (en) Partially disjoint equalization and carrier recovery
CN100531175C (zh) 内插模块、内插器及其方法
US9768883B2 (en) Low power equalizer for an optical receiver
CN102369706B (zh) 相位偏移和抖动补偿器
CN101867470A (zh) 高动态条件下载波同步装置和方法
WO2016119611A1 (fr) Procédé et dispositif de traitement de données
US20040047463A1 (en) Robust symbol timing recovery circuit for telephone line modem
CN109714144B (zh) 一种定时同步恢复方法及系统
CN113162713A (zh) 基于Gardner算法的变符号速率定时恢复方法及系统
CN116582235A (zh) 一种高速并行定时同步快速收敛方法
EP2976852B1 (fr) Appareil de récupération du rythme
JP6009953B2 (ja) 光受信装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14909360

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14909360

Country of ref document: EP

Kind code of ref document: A1