WO2016123768A1

WO2016123768A1 - Updating firmware with audio

Info

Publication number: WO2016123768A1
Application number: PCT/CN2015/072263
Authority: WO
Inventors: Morgan James Colmer
Original assignee: Global Silicon Ltd
Current assignee: Global Silicon Ltd
Priority date: 2015-02-04
Filing date: 2015-02-04
Publication date: 2016-08-11
Anticipated expiration: 2017-08-04
Also published as: CN108475191A

Abstract

A method for modifying a system configuration on a programmable device is disclosed comprising generating a modify file in a digital media content format; storing the modify file on a digital media content player; connecting the digital media content player to the programmable device; playing the modify file with the digital media content player for transmitting data for modifying the system configuration of the programmable device.

Description

UPDATING FIRMWARE WITH AUDIO

Technical Field

The invention relates generally to a method and apparatus for updating firmware in electronic consumer devices such as programmable input/output (I/O) device peripherals, e.g. audio/video devices, and more particularly to a method and apparatus for updating firmware in such electronic devices via digital audio files.

Background Art

Consumer demand has increased for programmable input/output (I/O) peripherals such as audio/video devices to play digital media content stored on computing platforms such as smart/feature phones, tablet computers, laptop computers, desktop computers, standalone media players, smart televisions (TV), portable media players, and the like. Such programmable I/O peripherals typically have firmware programmed into persistent memory that may require updating or upgrading with new versions of the firmware to incorporate a new feature, functionality, compatibility, modification, enhancements, or the like.

In view of the number of different computing platforms, operating systems and new media, manufacturers and developers typically spend substantial time and expense to develop proprietary applications for each type of computing platform and operating systems being used to deliver firmware updates or upgrades.

US2010/0161689 discloses method for updating/modifying/upgrading the system configuration of a stand-alone non-network connectible device. The method is performed while a portable device is docked to the non-network connectible device. System configuration update information is embedded within the ordinary data content that is received from the portable device during the routine operation of the stand- alone non-network connectible device. Upon receiving the embedded system configuration update information the non-network connectible device decrypts the embedded information and updates the system configuration accordingly. Generation of the embedded system configuration update information is performed in the portable docking device, and installation is performed on the non-network connectible device without requiring a network connection in the stand-alone device.

The method taught by US2010/0161689 suffers from problems associated with low frequency offsets. Furthermore, if there is a phase inversion in the data, the data encoding will fail, and it cannot use compressed audio formats.

There is therefore a need to address or at least alleviate or mitigate some of the above issues to reduce the overhead associated with updating or upgrading firmware.

Technical Solution

In a first main aspect, the invention provides a method for modifying a system configuration of a programmable device comprising: providing a modify file in a digital media content format to an electronic device adapted to play a digital media content file; connecting said electronic device to the programmable device; and playing the modify file with the electronic device for transmitting data in an analog signal format to said programmable device for modifying the system configuration of the programmable device.

In a second main aspect, the invention provides an electronic system for modifying a system configuration of a programmable device, said electronic system being capable of playing a digital media content file, the electronic system comprising: memory for storing a modify file in a digital media content format; means for connecting to a programmable device; and means for playing the modify file and formatting data of said modify file to an analog signal format to transmit said data in said analog signal format to said programmable device.

In a third main aspect, the invention provides a method of formatting a digital media content file into an audio signal format comprising: converting data of said media content file from an m bit code space to respective n bit channel symbols, where m and n are positive integers, m < n and the channel symbols are chosen from an available set of channel symbols to have zero DC content.

In a fourth main aspect, the invention provides a computer readable medium comprising program code executable by a processor of an electronic device to implement the steps of the methods of the first or third main aspects of the invention.

Description of Drawings

The accompanying drawings incorporated herein and forming a part of the specification illustrate several aspects of the present invention and, together with the description, serve to explain the principles of the invention. While the invention will be described in connection with certain embodiments, there is no intent to limit the invention to those embodiments described. On the contrary, the intent is to cover all alternatives, modifications and equivalents as included within the scope of the invention as defined by the appended claims. In the drawings:

FIG. 1 is a simplified schematic view of a digital media content player connected to a programmable device in accordance with an embodiment of the invention;

FIG. 2 is a simplified block diagram of the basic signal path from the digital media content player to the programmable device in accordance with an embodiment of the invention;

FIG. 3 is a flow chart in accordance with an embodiment of the invention;

FIG. 4 is a graph showing a simulation of a received sampled signal in accordance with an embodiment of the invention;

FIG. 5 is a graph showing an ADC digital filter frequency response in accordance with an embodiment of the invention;

FIG. 6 is a simplified block diagram of the soft-decision threshold with physical layer calibration phase in accordance with an embodiment of the invention;

FIG. 7 is a graph showing the upper and lower thresholds assigned during the calibration process in accordance with an embodiment of the invention;

FIG. 8 is a truth table for the differential encoder and decoder in accordance with an embodiment of the invention;

FIG. 9 is a diagram showing two possible input signals to the differential decoder that will result in the same decoded channel symbol in accordance with an embodiment of the invention;

FIG. 10 is a simplified block diagram of the differential encoder in accordance with an embodiment of the invention;

FIG. 11 is a simplified block diagram of the differential decoder in accordance with an embodiment of the invention;

FIG. 12 is a simplified block diagram of the four-to-six demodulator and four-to-six modulator in accordance with an embodiment of the invention;

FIG. 13 is a four-to-six encoding/decoding table in accordance with an embodiment of the invention;

FIG. 14 is a graph showing a four-to-six modulation example in accordance with an embodiment of the invention;

FIG. 15 is a graph showing the sync-symbol at the beginning of each 64 symbol packet in accordance with an embodiment of the invention;

FIG. 16 is a channel code and channel symbol table in accordance with an embodiment of the invention;

FIG. 17 is diagram showing the general data packet structure in accordance with an embodiment of the invention;

FIG. 18 is timing diagram showing the physical layer calibration of sync symbol in accordance with an embodiment of the invention;

FIG. 19 is a diagram showing the sequence in accordance with an embodiment of the invention;

FIG. 20 is a diagram showing the general packet format structure in accordance with an embodiment of the invention;

FIG. 21 is a diagram showing the packet data format structure at the receiver in accordance with an embodiment of the invention;

FIG. 22 is 4-bit data fields table in accordance with an embodiment of the invention;

FIG. 23 is a file control packet table in accordance with an embodiment of the invention;

FIG. 24 is a file CRC packet table in accordance with an embodiment of the invention;

FIG. 25 is a left and right audio channel data table in accordance with an embodiment of the invention;

FIG. 26 is a graph of a simulation of a perfect recovery of 2 symbols from the analog data in accordance with an embodiment of the invention;

FIG. 27 is a graph of a white data undetermined sample in accordance with an embodiment of the invention;

FIG. 28 is a graph of results of sample discriminator in accordance with an embodiment of the invention; and

FIG. 29 is a simplified block diagram of forward error correction in accordance with an embodiment of the invention.

Mode for Invention

A protocol and system is disclosed to enable transmission of firmware upgrades or the like to consumer electronic devices from electronic devices such as computing platforms or smart/feature phones without the need to develop proprietary applications for each type of platform being used to deliver the firmware upgrade.

The system uses custom encoded, uncompressed wave files (.WAV) to pass data in a specially modulated signal format to the device being upgraded using an analog audio signal over a connection between the computing platform and the programmable consumer electronic device. The connection may be a wireless connection, but, in preferred embodiments, the connection comprises an audio cable connection and, more particularly, a stereo cable connected from the smart phone, for example, to the device being upgraded. In an embodiment, the consumer electronic device is a speaker box or system which is also equipped with a microcontroller unit (MCU) and a 3.5mm stereo input jack. Most computing platforms capable of playing a digital media content file such as a .WAV file have a compatible output connector such as , for example, a headphone connector.

Referring to FIG. 1, a simplified schematic view 10 is shown of an electronic device such as a digital media content player 12 connected to a programmable device 14 in accordance with an embodiment of the invention. The player 12 may be connected to the programmable device 14 via wire or wireless means such as by stereo analog audio cable, Bluetooth™, or the like.

Electronic devices or computing platforms which may be used to deliver the wave file include, are not limited to, smart/feature phones, tablet computers, laptop computers, desktop computers, standalone media players, smart TVs, MP3 players, etc. The advantage to the consumer is that all 'smart' media player type products are compatible with this system, because the system requires no special software application or hardware and is operating system (OS) agnostic. The advantage to the manufacturer or developer is that the development overheads are minimised. Many modern speaker systems have MCUs included that have some limited digital signal processing (DSP) capabilities and have access to the digitized audio stereo input signal stream. These speakers typically also have an auxiliary analog input port, often called a line-in, to allow wired audio sources to be accommodated.

Within the speaker, the line in analog signal is digitized with an analog to digital converter (ADC). Within most media playback devices such as handsets, there is the reverse process occurring, the digital audio that is rendered by the media player software application is turned into an analog signal and fed to an analog audio output, often comprising a headphone socket.

The system description given here is for a specific embodiment, however, it will be appreciated that the basic principles apply even if the modulation scheme, data rates, frame structure or purpose of the data exchange are modified to suit other applications. In practice, the user would: download a short wave file with the special encoding included; place the target system into a special firmware upgrade mode, although this is not an essential step; and then just play the file in the native media player application on the electronic device. In doing so, the data of the modify wave file is transmitted to the programmable device to thereby upgrade its firmware. It will also be appreciated that this feature may be automatic. After the file has been played, the target device's firmware is upgraded using the transmitted data.

FIG. 2 is a simplified block diagram 20 of the basic signal path from the digital media content player to the programmable device in accordance with an embodiment of the invention. The digital media content player 12 comprises a wave file 22, media player application 24, and a digital to analog converter 26. The programmable device 14 comprises an analog to digital converter (ADC) 30 a microprocessor (MCU) 32, and a flash memory 34.

If the handset is playing back a specially encoded data sequence then it is possible to pass digital data to the speaker from playback of a wave file. Because wave files are not compressed and run at their native sample rate, the digital data recovered at the MCU in the speaker will be a close approximation to the original data sequence. Special encoding techniques are described below that are used to overcome some of the limitations in achieving digital communications, i.e. noise, spectral distortion of the channel and absence of direct clock synchronization.

In this application, the purpose is to allow remote reprogramming of the firmware for the speaker's MCU using the existing small flash memory 34, for example used for storing audio samples, as a temporary buffer storage, the program is located inside the MCU in on-chip flash memory.

FIG. 3 is a flow chart 40 in accordance with an embodiment of the invention. The method in accordance with an embodiment of the invention comprises modifying a system configuration on a programmable device 14 by generating 41 a modify file in a digital media content format. The modify file is then stored 42 on a digital media content player 12, and the digital media content player 12 is connected 44 to the programmable device 14. The digital media content player 12 plays 46 the modify file for transmitting 48 data for modifying the system configuration of the programmable device 14.

FIG. 4 is a graph 50 showing a simulation of a received sampled signal in accordance with an embodiment of the invention. Within the analog domain, digital bits are represented as voltage levels. In the data transmission device there is a media player that will take digital samples in signed 16 bit format and deliver these to the digital to analog converter (DAC) that will reproduce this signal in the analog domain. Within the digital domain, the two possible output values are for 1's: 0x7FFF and for 0's: 0x8000 to give the maximum possible channel SNR. In the analog domain, these may be represented as a number of different values depending upon the device but it is always assumed that the receiver and the transmitter will have matched analog levels. At the receiving device's ADC, these will be once again mapped into digital values but with the bandwidth and noise of the channel imposed. FIG. 4 is a simulation of a typical received sampled signal with a decision threshold of +/- 0.5 applied.

FIG. 5 is a graph 60 showing an ADC digital filter frequency response in accordance with an embodiment of the invention. FIG. 5 shows an ADC digital filter frequency response, in the simulations shown, the spectral distortion has been exaggerated in order to demonstrate that the proposed system will operate correctly in all system configurations. The output frequency response of the media player's DAC also needs to be considered but in general these are equivalent to the above.

FIG. 6 is a simplified block diagram 70 of the soft-decision threshold with physical layer calibration phase in accordance with an embodiment of the invention. On the face of it, turning an analog signal into a binary bit stream would appear to be a trivial task but in this application there are a number of challenges that come from the diversity of physical links available.

At the beginning of every data session there is a physical layer calibration phase, this process is to normalize the data slicing thresholds and establish a baseline for zero. The analog data slicing needs to have hysteresis to reduce the effect of noise manifesting itself as jitter on the digital signal output.

FIG. 7 is a graph 80 showing the upper and lower thresholds assigned during the calibration process in accordance with an embodiment of the invention. During the calibration process, the upper and lower thresholds are preferably assigned to be symmetrical around the baseline value found for zero and are expected to be within the range of +/-25% to +/-50% of the nominal 1 or 0 as shown in FIG. 7.

FIG. 8 is a truth table 90 for the differential encoder and decoder in accordance with an embodiment of the invention. Channel data is send via NRZ differentially encoded serial data in four-to-six modulation (FSM) format. Each FSM data symbol is differentially encoded so that a '1' represents a data transition and a '-1' (or logical '0') represents no data transition. The truth table for the differential encoder and decoder is dependent upon the previous input X[n-1] and the current input X[n] as shown in FIG. 8.

FIG. 9 is a diagram 110 showing two possible input signals to the differential decoder that will result in the same decoded channel symbol in accordance with an embodiment of the invention. In this way data may be in inverted or normal sense and the decoded data symbols are unchanged. The diagram of FIG. 9 shows two possible input signals to the differential decoder that will result in the same decoded channel symbol. It will be appreciated that the previous state determines the polarity of the decoder output, for this reason, every packet has a fixed polarity start sequence (see sync-symbol) that overrides the differential encoder.

FIG. 10 is a simplified block diagram 110 of the differential encoder in accordance with an embodiment of the invention, and FIG. 11 is a simplified block diagram 120 of the differential decoder in accordance with an embodiment of the invention. The equivalent circuit of the differential encoder is show in FIG. 10 where the channel clock is assumed to be 12 KHz, but this is not an inherent limitation. Other frequencies may be used. This is used at the final stage of the encoder before the wave file is written. The equivalent circuit of the differential decoder is show in FIG. 11, the channel clock is also assumed to be 12 KHz. This is the first stage in the decoding process and directly from the audio data received.

FIG. 12 is a simplified block diagram 130 of the four-to-six demodulator and four-to-six modulator in accordance with an embodiment of the invention. Due to the nature of audio analog input and outputs, care must be taken to remove any low frequency content from the data spectrum. This is achieved by four-to-six modulation (FSM). The FSM encoder/decoder will convert data from 4 bit code space into 6 bit channel symbols (or visa-versa), as shown in FIG. 12. The channel symbols have been chosen to all have zero DC content (i.e. equal numbers of 1's and 0's per symbol). From the 64 symbols available from 6-bit encoding, only 20 have zero DC content. Of these, a subset of 16 have been chosen as the channel symbols for the data 0x0 to 0xF, the remaining 4 symbols can be allocated as optional sub-codes for potential future system developments or expansion. Whilst four-to-six modulation/demodulation is preferred, other size bit code space to different sized bit channel symbols may be utilized. The use of bit code space to bit channel symbol modulation mitigates the effect of any DC blocking circuits of both the digital content media player and the device being upgraded which might otherwise introduce an offset leading eventually to the discrimination thresholds of one or both devices being exceeded.

FIG. 13 is a four-to-six encoding/decoding table 140 in accordance with an embodiment of the invention. Encoding and decoding are exactly juxtaposed so that encoding data to FSM and then decoding back to data will result in the same data value. It is anticipated that this will be achieved with a basic look-up table. The fact that all channel symbols have been chosen to have exactly zero DC content removes the need for any protocol overhead to include dynamic 'merging bits' to push the DC out of band.

FIG. 14 is a graph 150 showing a four-to-six modulation example in accordance with an embodiment of the invention. As an example of the channel coding, FIG. 14 is the example of two pieces of 4-bit data (0x0 and 0x1) being encoded to FSM (analog + digital representation with assumed channel filter properties simulated) and then differentially encoded. In this case the FSM encoded data is 0x04 and 0x09 which becomes 000111 and 001110 after differential encoding. It will be appreciated that data format is most significant bits first.

FIG. 15 is a graph 160 showing the sync-symbol at the beginning of each 64 symbol packet in accordance with an embodiment of the invention. At the beginning of each 64 symbol packet is a unique pair of channel symbols called the sync-symbol. This is used to identify the beginning of each packet and consists of 6 + 6 channel bits set 6 low followed by 6 high as shown in FIG. 15. The sync-symbol may not be differentially encoded as its phase is fixed, during the decoding process, the differential decoder will accept this symbol as the initializing state for the decoder for the whole data packet. The sync-symbol detection process will occur before differential decoding.

FIG. 16 is a channel code and channel symbol table 170 in accordance with an embodiment of the invention. There are 4 additional codes available in the FSM coding which meet the criteria of having zero net DC content. These have been reserved for future use as semaphores or sub-codes decoded over multiple packets or frames. They are defined as 'not a number' (NAN). In future enhancements to the system, these could be allocated as bit weightings and thus result in sub-code data over successive packets or frames.

FIG. 17 is diagram 180 showing the general data packet structure in accordance with an embodiment of the invention. A data session is defined as a set of packets that form a complete transmission/reception session. Both audio channels have the same PLC and FPC but the GDP packets and CRCs are different to allow the bandwidth of the system to be doubled. The overall file structure per session on each audio channel with 'n' general data packets has the following overall structure, as shown in FIG. 17.

FIG. 18 is timing diagram 190 showing the physical layer calibration of sync symbol in accordance with an embodiment of the invention. The calibration process is the first event that occurs in the data transmission process. The purpose of this delay is to ensure that the output and input stages of the transmitter and receiver have settled down to their zero DC level before the system begins sending data. During this time, the transmitter will send digital silence and the receiver will calibrate the DC level representing zero and establish soft thresholds for states of 1 and 0 during the 5 sync-symbols that are interspersed in the PLC. In this embodiment, the calibration time will be approximately 0.16 seconds long in total divided into 5 sections with 1536 samples (32ms) of digital silence on both audio channels starting with a SYNC symbol also on both audio channels.

When all 5 cycles are added, the sequence as shown in FIG 19 is formed. FIG. 19 is a diagram 200 showing the sequence in accordance with an embodiment of the invention.

FIG. 20 is a diagram 210 showing the general packet format structure in accordance with an embodiment of the invention. Each data packet is atomic and has a fixed format regardless of the type of packet or data usage. There is not a fixed number of packets per file, the FCP (file control packet) contains the file length and is described later. The general packet format is as follows and all packet types have the same structure. After the SYNC symbol, there are 64 4-bit data elements in each packet, after which the sequence continues from the SYNC symbol again until all data packets have been sent. In each packet there are therefore 66 x 6 channel bits = 396 channel bits. Each channel bit is quarter-multiple of the fundamental sampling rate of 48 KHz so each packet takes 33ms to transmit and contains (after decoding) 32 bytes (16 words) of data.

At the receiver the 4-bit data from each packet is then re-ordered into 16-bit data structures as shown in FIG. 21. FIG. 21 is a diagram 220 showing the packet data format structure at the receiver in accordance with an embodiment of the invention. Because there are two audio channels that are active in sending data, the two data streams need to be later merged into the final file format which is discussed later.

FIG. 22 is 4-bit data fields table 230 in accordance with an embodiment of the invention. The file control packet is the first packet sent after calibration during data transmission and it contains information about the type of file being sent, its size and application. The FCP is transmitted by both audio channels at the same time with the same data, because this packet is not included in the file CRC packet check process, two identical copies must be received and validated before the main data file is received. The packet structure is identical to the general data packet structure but with specific data fields regarding the data file being sent. The FCP also has its own CRC field for validity checking. The 4-bit data fields are defined as follows as shown in FIG. 22, and the file control packet has the layout shown in the table of FIG. 23 of its elements within the packet, data width and bit order in accordance with an embodiment of the invention.

The FCP CRC check is the CRC-16-ANSI standard created by IBM® systems using a check polynomial of 0x8005. This algorithm requires that all data is fed through a polynomial long division process in 16-bit format. This applies to all data in the FCP from D0 to D59 inclusive.

FIG. 24 is a file CRC packet table 250 in accordance with an embodiment of the invention. This is a 32 bit CRC of the entire data manifest with the exception of the CRC packet and the FCP. Each channel (left/right) encodes its own independent 32 bit CRC and each must be separately checked for consistency. The purpose of this data check is reduce the possibility of programming damaged data into the device, potentially preventing further upgrades being possible. The possibility of both channels CRCs being incorrect and the data matching this for both channels is over 4x10²⁴ : 1, and the CRC packet is generated using CRC-32-ANSI, the same open standard using in PNG, PKZIP and many other file types. The check polynomial is 0x04C11DB7 as shown in FIG. 24.

FIG. 25 is a left and right audio channel data table 260 in accordance with an embodiment of the invention. The file format is type specific; in this case the definition is for a firmware binary file used to re-program the MCU applications. The file is 38 Kbytes (38912 bytes) of actual data which is contained within the GDPs. In general the firmware update files will be kept at a constant length regardless of the size of the actual firmware, the full program memory will be accommodated. For the GS123 MCU, there will be 608 general data packets sent to each audio channel (1216 in total) allowing the MCU to be upgraded in under 21 seconds. The general data packets are first assembled upon receipt into 16 x 16-bit blocks and then these are placed though each channel's CRC checking algorithm on a packet-by-packet basis. After passing through the CRC checking algorithm, the packets are stored in external flash memory in contiguous blocks, following a LEFT channel first, RIGHT channel second ordering; this is the final order of the data for programming the flash memory. Once all 1216 packets have been received, the CRC computation from both audio channels will have arrived at a result, the next packet to arrive on each audio channel is the GDP CRC-32 packet. Once this has been compared with the result computed for each audio channel and found to be correct, the flash burning process may begin and the new code image may be burnt into the MCU's internal flash. Should the CRC be found to be incorrect for either audio channel, all of the data is discarded, the user is notified that the programming has failed and the target system should re-boot.

In view of the fact that the crystal oscillators that generate the clocks on both the handset and the speaker are in no way synchronized, the system must adapt to the variance in clock rates at the receiver. One of the reasons that in this 48 KHz sampled system, the channel clock is a quarter of that is that the oversampling may be used to remove the significance of this cycle slip. The typical accuracy of a crystal oscillator used in a speaker or handset is at least 50ppm accurate, this method will accommodate inaccuracies as much as 100 times that level. If the inaccuracy is as much as 500ppm then this will result is a gained or lost sample occurring at a rate of around 50 times per second. This system may cope with at least 8000 gained or lost cycles per second.

FIG. 26 is a graph 270 of a simulation of a perfect recovery of 2 symbols from the analog data in accordance with an embodiment of the invention. The sample-discriminator is able to cope with +/- one 48 KHz sample error. Essentially any sample transitions that are found to have occurred either one sample early or one sample too late are fixed in the data decoding process and a sample is either inserted or deleted to make the number of received 1's or 0's correct. FIG. 26 shows a simulation of a perfect recovery of 2 symbols from the analog data and the data sequence it produces: 001110 001110.

FIG. 27 is a graph 280 of a white data undetermined sample in accordance with an embodiment of the invention. FIG. 27 is the same data sequence that has been degraded by changing the timing by one sample. This results in some data samples that may not be resolved within the +/-0.5 decision threshold. Because this level of errors falls within the 3-to-5 threshold, the soft-decision unit may correct the data. The white data sample below is an undetermined sample.

FIG. 28 is a graph 290 of results of sample discriminator in accordance with an embodiment of the invention. In this case above, the white sample may be determined by the sample discriminator to be a 0. In the example shown in FIG. 28, the data quality has fallen unacceptably low and the sample discriminator may not always be certain to give the correct result as there are two samples that are either added or removed. The results could be either 001110 001110 or 001110 011110. Upon encountering the situation or two samples in error, the bit-discriminator must mark the bit as an erasure (0?1110) and later may further process this in the symbol-discriminator.

Due to the encoding of the four-to-six modulation in order to produce an error that will change a valid symbol into another valid symbol, two bits must be changed. In the above example, a symbol has a marked erasure or 0?1110 and this only has two possible states, 011110 and 001110, of which only one is a valid symbol. Upon finding an erasure in a symbol, the symbol discriminator needs to search the valid symbol table for the symbol that matches the other 5 known bits; the erasure may then be replaced with the correct bit. This also gives a basic level of error correction; the system may recover 2 samples in error within 24.

The sample discriminator may fix errors of up to +/-1 sample. The symbol discriminator may fix errors of +/-2 samples. If there are 3 or 4 sample errors then both the sample discriminator and the symbol discriminator will not detect or correct the error but the resulting symbol will be invalid. In the case of +/-3 or 4 samples in error, the error symbol may then be compared to the table of valid FSM symbols with a search algorithm until it arrives at a symbol where on one bit change is needed to produce a correct symbol. Because of the nature of the valid code distribution within the FSM code table, there will only be one valid symbol capable of meeting the criteria of a single bit in error. This increases the error correction capability to 4 samples within 24, or 1 bit in 6.

FIG. 29 is a simplified block diagram 300 of forward error correction in accordance with an embodiment of the invention. Should the data error rate begin to become noticeable then a further enhancement to the system is the forward error correction (FEC). The technique chosen is Reed-Solomon error coding and correction using a Galois Field of GF(2⁸) with the following polynomial:

P_(x) = x⁸ + x⁴ + x³ + x² +1

The primitive of this prime polynomial is alpha, defined as 0x02 (00000010). Because they are working with packet sizes of 32 bytes, this lends itself to a 32/28 coding gain, essentially with the loss of 4 bytes of data per packet may allow the correction of up to 1 byte per packet with a very low chance of mis-correction but given that the overall data file has a further very secure CRC then it is possible to correct up to 2 bytes per 32 byte packet.

The file length will become increased by the addition of error correction as there are now 4 party symbols per 28 bytes of data. These parity symbols may be used in a number of ways, they may be used to either detect errors, or they may be used to locate and correct errors but not both at the same time. An example of the limitations is given. If all 4 parity (syndromes) are used for error checking then all 32 bits are available to detect an error and the potential for misdetection is very low (1 : 2³²). When an error is found, one of the syndrome bytes may be used to locate the error and another to correct the error; then only 2 syndromes are left which gives us a 1 : 2¹⁶ chance of mis-correction. The process of error correcting requires complex math in the Galois field GF(2⁸) but there are short cuts available in the form of two look-up tables, each 256 bytes long to evaluate powers and logarithms within the GF. All 4 syndrome bytes should be inverted at encoding and re-inverted at decoding to prevent the situation of 28 bytes of zero data giving zero parity.

It is envisaged that the embodiments of the invention can achieve 1/4 of the audio sample rate because allowance is made for audio clock-slip in the decoding process. Consequently, it is possible to achieve a bit rate considerable greater than that of US2010/0161689 such that the audio WAV file in the present application can be considerably smaller. For example, for a 32Kbyte DSP/MCU, it is possible to upgrade a peripheral device or the like in under 20 seconds.

In the present invention, the use of differential encoding renders the phase of the data unimportant. As such, this mitigates the prior art problem where a phase inversion in the data, i.e. a '1' appears as a '0' or vice-versa, can cause the data to be unrecognized and thus the encoding to fail.

The deliberate redundancy in the symbol table of the present invention affords one or more levels of error correction which is advantageous over the known systems.

In preferred embodiments of the invention, left and right stereo channels are utilized. It will be understood that more channels could be used in a multi-channel system thereby further enhancing the efficiency of the method of the invention.

The synch process of the invention acts as a trigger for the DSP/MCU to automatically switch the programmable device to its upgrade mode and to stop any digital noise at the speakers as the system will mute the speakers or only play stored upgrade sound.

The method of the invention is adapted to also use compressed audio formats enabling short-range wireless connections such as Bluetooth™ to be utilized instead of a cable connection.

Furthermore, there is no requirement in the present invention to provide an interface unit between the digital content media player and the device being upgraded as the standard input line of a typical audio device will work and the firmware of the device being upgraded provides the interface as such.

In general, the invention provides a method for modifying a system configuration on a programmable device is disclosed comprising generating a modify file in a digital media content format; storing the modify file on a digital media content player; connecting the digital media content player to the programmable device; playing the modify file with the digital media content player for transmitting data for modifying the system configuration of the programmable device.

Embodiments of the invention have been described herein, including the best mode known to the inventors for carrying out the invention. Variations of those preferred embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for the invention to be practiced otherwise than as specifically described herein. Accordingly, this invention includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by the applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the invention unless otherwise indicated herein or otherwise clearly contradicted by context.

Claims

A method for modifying a system configuration of a programmable device comprising:

providing a modify file in a digital media content format to an electronic device adapted to play a digital media content file;

connecting said electronic device to the programmable device; and

playing the modify file with the electronic device for transmitting data in an analog signal format to said programmable device for modifying the system configuration of the programmable device.
The method of claim 1, wherein the step of modifying the system configuration of the programmable device comprises upgrading firmware of said programmable device.
The method of claim 2 or claim 3, wherein said programmable device comprises a non-network connected device.
The method of any one of claims 1 to 3, wherein the electronic device is connected to the programmable device by an analog audio connection.
The method of claim 4, wherein the analog audio connection is between a headphone output port of the electronic device and an analog input port or a line-in port of the programmable device.
The method of any one of the preceding claims, wherein the connecting of the electronic device to the programmable device comprises connecting the electronic device to the programmable device using a stereo analog audio cable.
The method of any one of the preceding claims further comprises placing the programmable device into a modifying mode prior to playing the modify file with the electronic device.
The method of any one of the preceding claims, wherein the step of providing the modify file in a digital media content format comprises providing the modify file in a waveform audio format (WAVE) having a '.wav' file format extension.
The method of any one of the preceding claims, wherein the step of providing the modify file comprises differential encoding an uncompressed modulated digital media content file to transmit data to the programmable device for modifying the system configuration of the programmable device.
The method of any one of the preceding claims, wherein the step of providing the modify file comprises inserting at the beginning of a data session a physical layer calibration phase to normalize data slicing thresholds and establish a baseline for zero.
The method of claim 10, wherein the step of providing the modify file comprises providing hysteresis to the analog data slicing to reduce noise manifesting and jitter of digital signal output.
The method of any one of the preceding claims, wherein the step of providing the modify file comprises removing low frequency content from the data spectrum of the modify file.
The method of claim 12 wherein the step of providing the modify file comprises selecting channel symbols with zero DC content.
The method of any one of the preceding claims, wherein the playing of the modify file with the electronic device for transmitting data for modifying the system configuration of the programmable device comprises transmitting data across two data streams of two audio channels.
The method of claim 14 further comprising merging the two data streams into a final file format.
The method of claim 2 wherein placing the programmable device into the modifying mode comprises muting speakers of the programmable device.
An electronic system for modifying a system configuration of a programmable device, said electronic system being capable of playing a digital media content file, the electronic system comprising:

memory for storing a modify file in a digital media content format;

means for connecting to a programmable device; and

means for playing the modify file and formatting data of said modify file to an analog signal format to transmit said data in said analog signal format to said programmable device.
A method of formatting a digital media content file into an audio signal format comprising: converting data of said media content file from an m bit code space to respective n bit channel symbols, where m and n are positive integers, m < n and the channel symbols are chosen from an available set of channel symbols to have zero DC content.
The method of claim 18, wherein m = 4 and n = 6 to provide a four-to-six modulation scheme.
A computer readable medium comprising program code executable by a processor of an electronic device to implement the steps of the methods of any one of claims 1 to 16 or 18 and 19.