WO2016150484A1 - Circuit de commutation avec atténuateur intégré - Google Patents

Circuit de commutation avec atténuateur intégré Download PDF

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Publication number
WO2016150484A1
WO2016150484A1 PCT/EP2015/056160 EP2015056160W WO2016150484A1 WO 2016150484 A1 WO2016150484 A1 WO 2016150484A1 EP 2015056160 W EP2015056160 W EP 2015056160W WO 2016150484 A1 WO2016150484 A1 WO 2016150484A1
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WO
WIPO (PCT)
Prior art keywords
switch
port
impedance
node
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2015/056160
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English (en)
Inventor
Kristoffer ANDERSSON
Mingquan Bao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
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Telefonaktiebolaget LM Ericsson AB
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Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Priority to PCT/EP2015/056160 priority Critical patent/WO2016150484A1/fr
Publication of WO2016150484A1 publication Critical patent/WO2016150484A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/44—Transmit/receive switching
    • H04B1/48—Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Definitions

  • Embodiments herein relate to a switch circuitry.
  • they relate to a switch circuitry with integrated attenuator employed in a front-end device of a communication system.
  • the front-end device of a pulsed radar system or a time division duplex communication system usually comprises a transmit branch and a receive branch.
  • the transmit branch generally comprises driver amplifiers, digital step attenuators, power amplifiers and filters.
  • the receive branch generally comprises low noise amplifiers and filters. Two transmit/receive switches are used to select the branch depending on whether the front-end receives or transmits signals.
  • the transmit/receive switch in the front-end device is a critical component.
  • the transmit/receive switch must be designed to both withstand high output power while providing low-loss.
  • Attenuators are circuits used to control amplitude of a signal either continuously or in steps.
  • the attenuator is referred as a digital step attenuator.
  • digital step attenuators may be needed to control the amplitude of received and/or transmitted signals.
  • a major problem associated with digital step attenuators is undesired insertion loss.
  • the undesired insertion loss may reach 3 dB which is probably higher than the desired attenuation of, for instance, 0.5 dB only. This insertion loss must be compensated for by increasing the gain in the driver amplifier and/or in the power amplifier, at the cost of increased circuit area and increased power consumption.
  • the object is achieved by a switch circuitry comprising a first port, a second port and a third port.
  • the switch circuitry further comprises a first switch transistor coupled between the first port and the second port; a second switch transistor coupled between the first port and the third port; a third switch transistor coupled between the second port and a ground node; and a fourth switch transistor coupled between the third port and the ground node.
  • the switch circuitry further comprises a first switch and attenuator unit having a first node and second node.
  • the first node is coupled to the first port and the second node is coupled to the second port.
  • the first switch and attenuator unit is in parallel with the first switch transistor.
  • the first switch and attenuator unit further comprises an impedance network.
  • the first and second terminals of the impedance network are coupled to the first and second nodes of the first switch and attenuator unit via respective switch transistors.
  • the switch circuitry integrates a digital step attenuator, i.e. the first switch and attenuator unit, into the transmit/receive switches, i.e. the first and/or second switches, by paralleling the first switch and attenuator unit with the first switch transistor. In this way, a series switch transistor in the digital step attenuator is omitted, thus the undesired insertion loss of the digital step attenuator due to the series switch transistor is mitigated.
  • the first switch and attenuator unit comprises an impedance network which may be switched in to the transmit and/or receive branch, or switched out from the transmit and/or receive branch by two switch transistors, different attenuation levels may be provided.
  • embodiments herein provide an integrated switch and step attenuator circuitry with improved performance on e.g. insertion loss, attenuation levels etc.
  • Figure 1 shows schematic views of (a) a transmit/receive switch, (b) a T-type step attenuator, (c) a Pi-type step attenuator, and (d) a transmit/receive switch cascade with step attenuators according to prior art.
  • Figure 2 is a schematic block view illustrating a switch circuitry according to embodiments herein.
  • Figure 3 shows schematic views illustrating (a) a T-type impedance network and (b) a Pi- type impedance network according to embodiments herein.
  • Figure 4 is a block diagram illustrating a wireless communication device in which
  • Broadband transmit/receive switches are typically implemented as shunt-series switches as shown in Figure 1 (a).
  • the transmit/receive switch in Figure 1 (a) has one input port, denoted as Common, and two output ports, denoted as Port 1 and Port 2.
  • Port 1 is switched to the Common port by turning on transistors Tb and turning off transistors Ta, while keeping Port 2 isolated by switching off transistor Tc and turning on transistor Td.
  • the main switching action is provided by the series transistors Tb and Tc, while the shunt transistors Ta and Td provide isolation.
  • the on-resistance of the series transistors Tb and Tc determines the insertion loss, low on-resistance means low insertion loss.
  • switching transistors Ta and Tb are used to switch between high attenuation, i.e. Ta is on, Tb is off, and low attenuation i.e. Ta is off and Tb is on.
  • switching transistors Ta, Tb and Tc are used to switch between high attenuation, i.e. Ta and Tb are on, Tc is off, and low attenuation i.e. Ta and Tb are off and Tc is on.
  • the series switching transistor, i.e. Tb in Figure 1 (b), Tc in Figure 1 (c) is used to bypass series elements of a resistive attenuator network, i.e. R1 and R2 in Figure 1 (b), R1 in Figure 1 (c).
  • the shunt switching transistors i.e. Ta in Figure 1 (b), Ta and Tb in Figure 1 (c), are used to isolate shunt resistors, i.e. R3 in Figure 1 (b), R2 and R3 in Figure 1 (c).
  • the insertion loss of the step attenuator at low attenuation state is dominated by the on resistance of the series switching transistor.
  • the step attenuator needs to have a large ratio between the on resistance of the series switching transistor and the resistance of the series resistors. Hence it is difficult to design step attenuators having low insertion loss at the low attenuation state and having high attenuation at the high attenuation state.
  • the digital step attenuator(s) is in cascade with the transmit/receive switch.
  • transmit/receive switch SW is cascaded with a first digital step attenuator DA1 and a second digital step attenuator DA2.
  • both the transmit/receive switch SW and the step attenuator DA1 /DA2 employs a series switching transistor.
  • the series switching transistors Tc in the digital step attenuator DA1 is in series with the series switching transistors T1 .
  • the series switching transistors Tc in the digital step attenuator DA2 is in series with the series switching transistors T2 in the transmit/receive switch SW.
  • the on resistance of the series switching transistor Tc in the step attenuators DA1 and DA2 will cause insertion loss at low attenuation state.
  • Tc in the digital step attenuators DA1 and DA2 are combined with the series switching transistors T1 and T2 in the transmit/receive switch SW.
  • the series switching transistors Tc in the digital step attenuators DA1 and DA2 are removed or omitted. Instead, the series switching transistors T1 and T2 in transmit/receive switch SW are re-used in the step attenuator.
  • an integrated switch and attenuator circuitry is configured as shown in Figure 2, denoted as a switch circuitry 200.
  • the switch circuitry 200 comprises a first port 201 , a second port 202 and a third port 203.
  • the switch circuitry 200 further comprises a first switch transistor T1 coupled between the first port 201 and the second port 202; a second switch transistor T2 coupled between the first port 201 and the third port 203; a third switch transistor T3 coupled between the second port 202 and a ground node; and a fourth switch transistor T4
  • the switch circuitry 200 further comprises a first switch and attenuator unit 210 having a first node N11 and second node N12.
  • the first node N1 1 is coupled to the first port 201 and the second node N12 is coupled to the second port 202.
  • the first switch and attenuator unit 210 is in parallel with the first switch transistor T1 .
  • the first switch and attenuator unit 210 comprises an impedance network 212.
  • the first and second terminals N13, N14 of the impedance network 212 are coupled to the first and second nodes N1 1 , N12 of the first switch and attenuator unit 210 via respective switch transistors T1 1 , T12.
  • the switch circuitry 200 further comprises a second switch and attenuator unit 220 having a first node N21 and second node N22.
  • the first node N21 is coupled the first port 201 and the second node N22 is coupled to the third port 203.
  • the second switch and attenuator unit 220 is in parallel with the second switch transistor T2.
  • the dotted line connections of the second switch and attenuator unit 222 to the second switch transistor T2 means that the second switch and attenuator unit 222 is optional.
  • the second switch and attenuator unit 220 may have similar structure as the first switch and attenuator unit 210.
  • the second switch and attenuator unit 220 comprises an impedance network 222.
  • the first and second terminals N23, N24 of the impedance network 222 are coupled to the first and second nodes N21 , N22 of the second switch and attenuator unit 220 via respective switch transistors T21 , T22.
  • the impedance network 212, 222 may comprise a Pl- type impedance network 214, as shown in Figure 3 (a).
  • the Pl-type impedance network 214 comprises a first impedance R1 coupled between the first terminal N1 and the second terminal N2 of the impedance network 214, a second impedance R2 coupled between the second terminal N2 and the ground node, and a third impedance R3 coupled between the first terminal N1 and the ground node.
  • the impedance network 212, 222 may comprise a T- type impedance network 216, as shown in Figure 3 (b).
  • the T-type impedance network 216 comprises a first impedance R1 connected in series with a second impedance R2 and coupled between the first terminal N1 and the second terminal N2 of the impedance network; and a third impedance R3 coupled between the ground node and a middle node NO formed by the connection of the first impedance R1 and second impedance R2.
  • the first and second switch and attenuator units 210, 220 may further comprise a fourth impedance R41 , R42.
  • the fourth impedance R41 is connected between the first node N1 l and second node N12 of the first switch and attenuator unit 210.
  • the fourth impedance R42 is connected between the first node N21 and second node N22 of the second switch and attenuator unit 220.
  • the dotted line connections of the fourth impedance R41 , R42 to the first node N1 1 , N21 and second node N12, N22 as shown in Figure 2 means that the fourth impedance R41 , R42 is optional.
  • the fourth impedance R41 , R42 may be a variable resistor, or a variable resistor connected in series or in parallel with inductors or capacitors.
  • the impedance network 212, 222 may be a variable resistance network, and the impedances R1 , R2, R3 comprised in the impedance network 212, 222 are variable resistors.
  • the impedance network 212, 222 may be a variable impedance network, and the impedances R1 , R2, R3 comprised in the impedance network 212, 222 are variable resistors connected in series or in parallel with inductors or capacitors.
  • the switch and attenuator unit 210, 220 may be incorporated into one or both branches i.e. in transmit branch and/or receive branch.
  • the shunt switch transistors T1 1 , T12, T21 , T22 are used to engage an attenuator, i.e. the Pi-type or T-type impedance network 212, 222 to the transmit/receive switch T1 /T2.
  • the fourth impedance R41 , R42 is optional and in most practical implementations it may be omitted. However, for relative high attenuation, e.g.
  • the fourth impedance R41 , R42 may be included with a resistance value of about 70 Ohms or larger in a system with 50 Ohm input/output impedance.
  • this branch may be configured to have four operating modes: isolated, low loss, X dB attenuation and Y dB attenuation.
  • the amount of attenuation, X dB and Y dB may be controlled by selecting impedances R1 , R2, R3, and R41 .
  • the Y dB attenuation mode is an extra mode that provides less attenuation than X dB.
  • the impedances R1 , R2, R3, and R41 may comprise a resistor connected in series or in parallel with an inductor or capacitor.
  • the reactive component i.e. the inductor and capacitor are used to reduce the influence of parasitic capacitances and improve impedance matching.
  • the table below shows a mapping between the operating modes and the switch transistor states, i.e. either on or off.
  • the table is valid for the case where the switch and attenuator unit 210 is incorporated in one branch between Port 201 and Port 202, e.g. the transmit branch TX and no switch and attenuator unit 220 in the receive branch RX between Port 201 and Port 203.
  • the simulated switch circuitry comprises 4x100 um Field-Effect Transistors (FETs) as the series switch transistors T1 and T2 and 2x100 um FETs as the shunt switch transistors T1 1 and T12.
  • FETs Field-Effect Transistors
  • the isolation transistors T3 and T4 are two 2x100 um FETs in parallel.
  • the simulation results show that the insertion loss at 4GHz for the transmit branch is - 1 .6dB for 0-dB attenuation mode, -4.7dB for 3-dB attenuation mode, and -8.4dB for 8-dB attenuation mode.
  • the insertion loss for the receive mode is -1 .5dB.
  • the degradation in the insertion loss due to the switch and attenuator unit 210 is only 0.1 dB which is negligible.
  • the simulation results also show that the isolation between the transmit TX and receive RX branch is not hampered by adding the switch and attenuator unit 210.
  • integration of a digital step attenuator with the transmit/receive switch as implemented in the switch circuitry 200 has several advantages.
  • the foremost advantage is that the undesired insertion loss associated with the digital step attenuator is completely mitigated, since the insertion loss of the step attenuator is absorbed by the transmit/receive switch and the insertion loss is set only by the transmit/receive switch.
  • the second advantage is that due to the integration, the size of the front-end device module or circuitry, DC power consumption can be greatly reduced.
  • high gain, high power, highly efficient and low noise front-ends may be designed by employing the switch circuitry 200 according to embodiments herein.
  • FIG. 4 shows a block diagram of a communication device 400, which may be, e.g. a user equipment or a mobile device and/or a base station.
  • the communication device 400 may comprise other units, where a transceiver 430 comprising a receiver 410 and a transmitter 420 and a processing unit 440 are shown.
  • the switch circuitry 200 is coupled between the receiver 410 and transmitter 420.
  • the processing unit 440 may interact with the switch circuitry 200 for different attenuation settings or operating modes.
  • switch transistors in the switch circuitry 200 as shown in Figure 2 are Field-Effect Transistors (FET), any other types of transistors, e.g. Metal-Oxide-Semiconductor FET (MOSFET), Junction FET (JFET), Bipolar Junction Transistors (BJT), High-Electron-Mobility Transistor (HEMT), Heterojunction Bipolar Transistor (HBT), PIN diode, i.e. diode with wide, undoped Intrinsic semiconductor region between a P-type semiconductor and an N-type semiconductor region, etc. may be comprised in the switch circuitry 200.
  • FET Field-Effect Transistors
  • MOSFET Metal-Oxide-Semiconductor FET
  • JFET Junction FET
  • BJT Bipolar Junction Transistors
  • HEMT High-Electron-Mobility Transistor
  • HBT Heterojunction Bipolar Transistor
  • PIN diode i.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Attenuators (AREA)

Abstract

L'invention concerne un circuit de commutation (200) qui comprend un premier port (201), un deuxième port (202) et un troisième port (203). Le circuit de commutation (200) comprend en outre un premier transistor de commutation (T1) couplé entre le premier port (201) et le deuxième port (202) ; un deuxième transistor de commutation (T2) couplé entre le premier port (201) et le troisième port (203) ; un troisième transistor de commutation (T3) couplé entre le deuxième port (202) et un nœud de masse ; et un quatrième transistor de commutation (T4) couplé entre le troisième port (203) et le nœud de masse. Le circuit de commutation (200) comprend en outre une première unité de commutateur et d'atténuateur (210) comportant un premier nœud (N11) et un second nœud (N12). Le premier nœud (N11) est couplé au premier port (201) et le second nœud (N12) est couplé au second port (202) et, de ce fait, est en parallèle avec le premier transistor de commutation (T1). La première unité de commutateur et d'atténuateur (210) comprend un réseau d'impédance (212). Les première et seconde bornes (N13, N14) du réseau d'impédance (212) sont couplées aux premier et second nœuds (N11, N12) de la première unité de commutateur et d'atténuateur (210) par l'intermédiaire de transistors de commutation (T11, T12) respectifs.
PCT/EP2015/056160 2015-03-23 2015-03-23 Circuit de commutation avec atténuateur intégré Ceased WO2016150484A1 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109412554A (zh) * 2018-09-22 2019-03-01 复旦大学 一种宽带高精度数控有源衰减器
CN115276628A (zh) * 2022-08-03 2022-11-01 西南科技大学 一种提高通道隔离度的模拟开关
EP4187798A1 (fr) * 2021-11-24 2023-05-31 Qorvo US, Inc. Commutateurs de spdt avec atténuateurs intégrés
EP4344060A1 (fr) * 2022-09-21 2024-03-27 Nxp B.V. ATTÉNUATEUR INDUCTIF cOMMUTABLE AVEC COMPENSATION DE PHASE CAPACITIVE ET INCORPORATION DANS UN COMMUTATEUR QUART D'ONDE TX / RX
US12424723B2 (en) 2022-09-21 2025-09-23 Nxp B.V. Circuit with first and second terminals coupled together via a branch-interconnection arrangement

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0594434A2 (fr) * 1992-10-22 1994-04-27 Kokusai Electric Co., Ltd. Radio émitteur-récepteur
US5777530A (en) * 1996-01-31 1998-07-07 Matsushita Electric Industrial Co., Ltd. Switch attenuator
US20130072134A1 (en) * 2011-09-16 2013-03-21 Renesas Electronics Corporation Attenuating antenna switch and communication device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0594434A2 (fr) * 1992-10-22 1994-04-27 Kokusai Electric Co., Ltd. Radio émitteur-récepteur
US5777530A (en) * 1996-01-31 1998-07-07 Matsushita Electric Industrial Co., Ltd. Switch attenuator
US20130072134A1 (en) * 2011-09-16 2013-03-21 Renesas Electronics Corporation Attenuating antenna switch and communication device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109412554A (zh) * 2018-09-22 2019-03-01 复旦大学 一种宽带高精度数控有源衰减器
EP4187798A1 (fr) * 2021-11-24 2023-05-31 Qorvo US, Inc. Commutateurs de spdt avec atténuateurs intégrés
US12362730B2 (en) 2021-11-24 2025-07-15 Qorvo Us, Inc. SPDT switches with embedded attenuators
CN115276628A (zh) * 2022-08-03 2022-11-01 西南科技大学 一种提高通道隔离度的模拟开关
EP4344060A1 (fr) * 2022-09-21 2024-03-27 Nxp B.V. ATTÉNUATEUR INDUCTIF cOMMUTABLE AVEC COMPENSATION DE PHASE CAPACITIVE ET INCORPORATION DANS UN COMMUTATEUR QUART D'ONDE TX / RX
US12424723B2 (en) 2022-09-21 2025-09-23 Nxp B.V. Circuit with first and second terminals coupled together via a branch-interconnection arrangement

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