WO2016193377A1 - Dispositif à semi-conducteur amélioré comportant une diode schottky - Google Patents

Dispositif à semi-conducteur amélioré comportant une diode schottky Download PDF

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Publication number
WO2016193377A1
WO2016193377A1 PCT/EP2016/062507 EP2016062507W WO2016193377A1 WO 2016193377 A1 WO2016193377 A1 WO 2016193377A1 EP 2016062507 W EP2016062507 W EP 2016062507W WO 2016193377 A1 WO2016193377 A1 WO 2016193377A1
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WO
WIPO (PCT)
Prior art keywords
region
diffusion
conductivity type
doped
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2016/062507
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German (de)
English (en)
Inventor
Michael Reschke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DIOTEC SEMICONDUCTOR AG
Original Assignee
DIOTEC SEMICONDUCTOR AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DIOTEC SEMICONDUCTOR AG filed Critical DIOTEC SEMICONDUCTOR AG
Priority to RU2017141853A priority Critical patent/RU2683377C1/ru
Priority to EP16726576.8A priority patent/EP3268991A1/fr
Publication of WO2016193377A1 publication Critical patent/WO2016193377A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/129—Cathode regions of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates

Definitions

  • the invention relates to an improved semiconductor device with a Schottky diode, which, while maintaining the electrical data, an increased current density over known
  • a guard ring is diffused into the epitaxial layer in order to improve the breakdown behavior, Such a guard ring is disclosed, for example, in DE 199 39 484 A1.
  • the less doped semiconductor layer of a first doping or of a first conductivity type required for the production of the Schottky clock on a highly doped or more highly doped substrate with the same
  • a more highly doped enrichment layer of the second conductivity type implanted to a lateral penetration of the space charge zone in the area of the second
  • DE 10 2009 056 603 A1 uses a brake oxide which is required for the p (+) implantation, whereby the application of an LTO / CVD layer is omitted.
  • the invention is therefore based on the object, an improved semiconductor device with Schottky diode
  • a semiconductor device having a Schottky diode comprising a guard ring structure, an epitaxial layer and a
  • a diffusion region of the second conductivity type is formed with a concentration gradient that forms a grad n, p junction with a simultaneously diffusing higher doped layer of the first conductivity type.
  • Epitaxial region a positive concentration gradient in the direction of the epitaxial substrate and, thus, a reduction in the effective resistance of the web. Furthermore, the penetration depth of the region becomes of the second conductivity type
  • An advantageous embodiment may provide that in the diffusion region of the second conductivity type 31, a highly doped region 8 is formed close to the surface, wherein the lateral dimensioning of the heavily doped region 8 is formed such that lateral boundaries of the propagation of a
  • a field ring may be arranged outside the concentric region of the second conductivity type such that a vertical distance between the field ring and the diffusion region of the second conductivity type is greater than one of constant
  • Residual layer thickness of the epitaxial layer and layer thickness of the graduated area of composite layer thickness are Residual layer thickness of the epitaxial layer and layer thickness of the graduated area of composite layer thickness.
  • Cross-section B of the structure p (+), p, n, grad n, n (+) is present.
  • a development of the invention may additionally provide that in a more highly doped region of the second conductivity type, a further, even more highly doped region of the second conductivity type is arranged.
  • a semiconductor device comprises a Schottky diode having a region of the first conductivity type, a higher doped region of the first conductivity type and at least one region of the second
  • the region of the first conductivity type may be configured as an epitaxial layer and in particular as an n-epitaxial layer.
  • the higher doped region of the first conductivity type may be referred to as
  • Epitaxy substrate be configured.
  • the region of the second conductivity type may be configured as a diffusion region.
  • first and second conductivity type can be reversed accordingly.
  • the transition area may be formed as a graduated area.
  • the diffusion region of the second conductivity type may form an n, p junction with a concentration gradient of a simultaneously diffusing higher doped layer of the first conductivity type, and preferably form a grad n, p junction.
  • the region of the second conductivity type may be non-contact with the higher-doped region of the first conductivity type
  • the region of the second conductivity type predominantly in the region of the first
  • Line type can be arranged.
  • the invention can provide that at least one field ring is arranged at least in a partial region of the region of the first conductivity type.
  • the at least one field ring may be arranged concentrically to the at least one region of the second conductivity type. It is also particularly advantageous if the at least one
  • Field ring of the second conductivity type is arranged at a distance to the at least one region of the second conductivity type, which is greater than or equal to a layer thickness of the region of the first conductivity type and / or greater than or equal to a composite layer thickness of area of the first
  • Invention may provide that the area from the first
  • Line type has a same or greater layer thickness compared to the higher doped region of the first conductivity type
  • the semiconductor device with an effective epitaxial layer thickness of 2 pm and a spec.
  • Epitaxial layer thicknesses can be the differential
  • the invention may also provide a method of fabricating a semiconductor device having a Schottky diode having an n, p junction, and preferably a grad n, p junction, in which between a region of the first conductivity type and a more highly doped region of the first
  • a transition region of the first conductivity type is introduced with a concentration gradient.
  • the invention may further provide a method in which, to form a guard ring structure, a diffusion region of the second doping type in a homogeneously doped region up to a concentration-graded region of a first conductivity type is introduced on a high-concentration epitaxial substrate of the first conductivity type.
  • At least one field ring can be introduced into at least one region of the first conductivity type.
  • the at least one field ring may be preferably concentric and more preferably outside concentric with a guard ring and / or a second conductivity type region such that a distance between guard ring and / or second conductivity type region and field ring is greater than the layer thickness of the region of first conductivity type or the total layer thickness of the first conductivity type region and the first conductivity type region and the junction region.
  • the invention also provides a method for producing a Schottky diode, wherein, in a first process step, an oxidation of the epitaxial wafer serving as the starting product
  • the oxide window becomes
  • Implantation opened in front of boron and a thin oxide generated before implantation. Here it is essential that considerably lower
  • the contact area of the Schottky area is opened by means of a photo step.
  • the invention also provides a method for producing a Schottky diode, starting from a starting product comprising at least one n (+) substrate, a graded epitaxial region and a constant doped epitaxial region.
  • boron diffuses in and a grad n, p transition is formed and preferably simultaneously
  • n (+) - substrate wherein a preferably simultaneous diffusion from the n (+) - substrate takes place in a direction opposite to the diffusion of boron through both the constantly doped epitaxial region and in the graded epitaxial region and
  • Track region occurs in a direction opposite to the diffusion of boron through both the constant doped epitaxial region and the graded epitaxial region.
  • an optimized Schottky diode with reduced sheet resistance can be provided.
  • the corresponding Schottky diode can be made of a smaller size. Applications of such Schottky diodes can be extended thereby.
  • the method according to the invention for the production of Schottky diodes with reduced sheet resistance provides for the reduction of the constantly doped epitaxial region in at least two steps, one step involving oxidation and one Step at least one preferably simultaneously
  • the invention can provide that in a first reduction, the layer thickness of the epitaxial epitaxial region doped constant from about 0.5 ⁇ is reduced to about 0.3 pm and in a second reduction of about 0.3 pm to about 0.1 pm
  • the invention also provides a Schottky diode comprising contact metallizations, a Schottky barrier, an n (+) substrate, a graded epitaxial region, a constant
  • doped epitaxial region an oxide, a p (+) region and a p-type region and is characterized in that the epitaxial epitaxial region doped constant has a layer thickness of about 0.1 pm and the graduated epitaxial region has a layer thickness of about 2 ⁇ .
  • Such a Schottky diode according to the invention has a reduced sheet resistance and a correspondingly increased
  • the characteristic sheet resistance of the graduated layer of a Schottky diode which has a layer thickness of the epitaxial epitaxial region of approximately 0.1 ⁇ m, is reduced to approximately 15mOhm mm 2 in the case of the 40V voltage class.
  • a total resistance of about 25mOhm mm 2 which allows the current density to increase to about 4A / mm 2 .
  • the dominant residual currents are due to the Schottky barrier and the surface concentration of about 0.1 pm
  • the invention is based on
  • FIG. 1 Schematic sectional view of the invention
  • FIG. 3 enlarged schematic sectional view of a
  • FIG. 4 enlarged schematic sectional view of a
  • FIG. 5 Schematic sectional view of a starting product for the production of a Schottky diode according to the invention
  • FIG. 6 is a schematic sectional view of that shown in FIG.
  • FIG. 7 Schematic sectional view of FIG. 6 after
  • FIG. 8 Schematic sectional view of FIG. 7 after
  • FIG. 9 Schematic sectional view of FIG. 8 after
  • FIG. 10 Schematic sectional view of FIG. 9 after
  • FIG. 11 is a schematic sectional view of an embodiment of a Schottky diode according to the invention, produced in accordance with the process steps shown in FIGS. 5 to 10
  • Fig. 1 is an embodiment of the invention
  • Metallization 1 arranged oxide 2 on.
  • barrier metal layer 5 is provided below the
  • Barrier metal layer 5 and the oxide 2 is a
  • Epitaxial layer 4 arranged.
  • the epitaxial layer 4 is in the embodiment of the first conductivity type, as n
  • the Schottky diode semiconductor device 12 comprises
  • the highly doped epitaxial substrate 7 of the first conductivity type furthermore a highly doped epitaxial substrate 7 of the first conductivity type.
  • Epitaxy substrate 7 formed as an n (+) epitaxial substrate.
  • the Schottky diode semiconductor device 12 also has at least one diffusion region 31 of the second conductivity type, which may also be configured as a guard ring structure.
  • the diffusion region 31 penetrates vertically into a graded region 6, without the diffusion front of n (+) from the
  • the graduated region 6 in the exemplary embodiment is the result of a prior art step profile of the epitaxy process whose vertical diffusion component leads to concentration elevation in region 4 and formation of end state of region 6, as well as endpoint of contraverse diffusion of region 31 through region 4 in region 6th
  • the diffusion region 31 of the second conductivity type is in
  • Embodiment designed as a p area within the diffusion region 31 is a higher doped region 8 of the second conductivity type, in the embodiment according to p (+), introduced such that the covered by the barrier metal layer 5 region of the epitaxial layer 4 and the
  • This higher-doped region 8 of the second conductivity type is structurally designed such that a laterally into the
  • Diffusion region 31 penetrating depletion zone is not limited by the region 8 of the second conductivity type.
  • the higher doped region 8 of the second conductivity type is located near the surface in the diffusion region 31 of the second conductivity type. The necessity of the higher-doped area 8 of the second
  • Conduction type results in particular by avoiding parasitic barriers on or in contrast to the lower doped diffusion region 31 of the second conductivity type.
  • An increase in the current density is achieved by arranging a diffusion region 31 of the second conductivity type, such that it forms into a simultaneously diffusing, more highly doped, first conductivity type, graduated region 6
  • Epitaxial substrate 7 not reached. Thus, there is no p, (n +) transition but a grad n, p transition 9.
  • the adjustable concentration gradient of the graduated region 6 reaches the epitaxial layer 4 and increases its concentration gradually, but without it
  • Barrier transitions are directed vertically and laterally. The vertical transition is from the second conductivity type diffusion region 31 to the graded region 6 from the first
  • the propagation of the space charge zone takes place in the vertical direction predominantly in the diffusion region 31 of the second conductivity type as well as in the direction of the graduated region 6 in the sense of a linearization of the p, n junction 10
  • the propagation of the space charge zone occurs both in the diffusion region 31 of the second conductivity type and in the epitaxial layer 4 of the first conductivity type.
  • Line type is additionally introduced in the embodiment shown, at least one field ring 32, which causes a limitation of the external electric field.
  • this distance referred to as x1
  • x1 is greater than the residual thickness of the epitaxial layer Wxn-grad (n +).
  • the distance x 1 is also greater than the summed layer thickness of the epitaxial layer 4 and the graduated area 6.
  • n, p, p (+), p, n and a vertical cross section (B) of the structure p (+), p, grad n, n (+) is present. It can also be provided that either such a lateral
  • Cross section A or such a vertical cross section B is present.
  • Fig. 3 is shown how the higher doped region 8 from the second
  • Conduction type is arranged so aligned with respect to the oxide 2 and within the region 31 of the second conductivity type that the distance x2 according to the above explanations is further defined.
  • the second conductivity type field ring 32 does not have a higher doped region 8 of the second conductivity type.
  • Fig. 4 shows an additional embodiment in which in the higher doped region 8 of the second conductivity type, corresponding to p (+) another, even higher doped region 11 of the second conductivity type, corresponding to p (++) is arranged.
  • the second conductive type region 8 may be arranged as shown in Fig. 3, and may additionally have a still higher doped region of the second conductive type.
  • the inventive method for producing a Schottky diode is shown schematically in FIGS. 5 to 10.
  • the starting product 108 comprises an n (+) substrate 102, a graduated epitaxial region 103 (in the exemplary embodiment about 3. 5 * 10 ⁇ 15 / ⁇ ) and a constant doped epitaxial region 104, which in the exemplary embodiment, a layer thickness of about 0.5 ⁇ on.
  • the 40V voltage class is described by way of example. It finds one here
  • Epitaxy region 104 of about 0.5 ⁇ (Fig. 5) to about 0.3 pm instead (see Fig. 6).
  • the oxide 105 In the following photo step, the oxide 105 or
  • Open oxide window for boron implantation and generate an oxide prior to implantation see FIG. 7).
  • This may be, for example, diffusion of arsenic.
  • Schottky diode 100 includes contact metallizations 101, 101a, a Schottky barrier 110, an n (+) substrate 102 (gradient about 1 * 10 ⁇ 19 / ⁇ ), a graded epitaxial region 103, a constant doped epitaxial region 104, an oxide 105, a p (+ ) Area 107 and a p-area 106.
  • the constantly doped epitaxial region 104 in this case has a layer thickness of about 0.1 pm, which graduated
  • Epitaxy region 103 (gradient about 3.5 ⁇ 10EXP19 / pm) has a layer thickness of about 2 ⁇ m.
  • a Schottky diode 100 according to the invention in the 40V voltage class has a reduced characteristic sheet resistance, which is approximately 25mOhm mm 2 .
  • Comparable prior art Schottky diode has a bulk resistance of about 40mOhm.mm 2 .
  • Schottky diode and Schottky diode semiconductor device are equivalent

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  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un dispositif à semi-conducteur (12) comportant une diode Schottky, comprenant une structure d'anneau de protection, une couche épitaxiale (4) et un substrat d'épitaxie (7). La diode présente une région de diffusion (31) du second type de conduction, qui forme une jonction de type n, p avec un gradient de concentration d'une couche du premier type de conduction qui est dopée de manière supérieure et qui diffuse simultanément.
PCT/EP2016/062507 2015-06-02 2016-06-02 Dispositif à semi-conducteur amélioré comportant une diode schottky Ceased WO2016193377A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
RU2017141853A RU2683377C1 (ru) 2015-06-02 2016-06-02 Усовершенствованный полупроводниковый прибор с диодом шоттки
EP16726576.8A EP3268991A1 (fr) 2015-06-02 2016-06-02 Dispositif à semi-conducteur amélioré comportant une diode schottky

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102015108728.6 2015-06-02
DE102015108728 2015-06-02

Publications (1)

Publication Number Publication Date
WO2016193377A1 true WO2016193377A1 (fr) 2016-12-08

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PCT/EP2016/062507 Ceased WO2016193377A1 (fr) 2015-06-02 2016-06-02 Dispositif à semi-conducteur amélioré comportant une diode schottky

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EP (1) EP3268991A1 (fr)
DE (1) DE102016110203B4 (fr)
RU (1) RU2683377C1 (fr)
WO (1) WO2016193377A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110890361A (zh) * 2019-12-23 2020-03-17 苏州晶讯科技股份有限公司 一种多端口低容电压浪涌保护芯片及其制作方法
RU231051U1 (ru) * 2024-10-29 2024-12-28 Федеральное государственное унитарное предприятие "Всероссийский научно-исследовательский институт автоматики им. Н.Л. Духова" (ФГУП "ВНИИА") Диод Шоттки

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4206540A (en) 1978-06-02 1980-06-10 International Rectifier Corporation Schottky device and method of manufacture using palladium and platinum intermetallic alloys and titanium barrier
JP2000036607A (ja) * 1998-07-21 2000-02-02 Sanyo Electric Co Ltd ショットキーバリアダイオード
DE19939484A1 (de) 1998-09-01 2000-03-09 Int Rectifier Corp Schottky-Diode
US6177712B1 (en) 1996-12-10 2001-01-23 Fuji Electric Co., Ltd. Schottky barrier diode having a guard ring structure
US20090134405A1 (en) * 2007-11-27 2009-05-28 Kabushiki Kaisha Toshiba Semiconductor substrate and semiconductor device
US20090256197A1 (en) * 2008-04-09 2009-10-15 Yoshito Nakazawa Semiconductor device and manufacturing method thereof
DE102009018971A1 (de) 2009-04-25 2010-11-04 Secos Halbleitertechnologie Gmbh Konstruktion einer Schottkydiode mit verbessertem Hochstromverhalten und Verfahren zu deren Herstellung
EP2259326A1 (fr) * 2008-03-17 2010-12-08 Mitsubishi Electric Corporation Dispositif à semi-conducteur
DE102009056603A1 (de) 2009-12-02 2011-06-09 Eris Technology Corp. Verfahren zur Herstellung einer Schottkydiode mit verbessertem Hochstromverhalten
JP2011129738A (ja) * 2009-12-18 2011-06-30 Nippon Inter Electronics Corp ショットキーバリアダイオード
US20150034970A1 (en) * 2011-05-18 2015-02-05 Rohm Co., Ltd. Semiconductor device and method for producing same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010001338A1 (fr) * 2008-07-01 2010-01-07 Nxp B.V. Fabrication de dispositifs à semi-conducteur
RU2390880C1 (ru) * 2009-05-25 2010-05-27 Общество с ограниченной ответственностью "Мегаимпульс" ИНТЕГРИРОВАННЫЙ ШОТТКИ-pn ДИОД НА ОСНОВЕ КАРБИДА КРЕМНИЯ

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4206540A (en) 1978-06-02 1980-06-10 International Rectifier Corporation Schottky device and method of manufacture using palladium and platinum intermetallic alloys and titanium barrier
US6177712B1 (en) 1996-12-10 2001-01-23 Fuji Electric Co., Ltd. Schottky barrier diode having a guard ring structure
JP2000036607A (ja) * 1998-07-21 2000-02-02 Sanyo Electric Co Ltd ショットキーバリアダイオード
DE19939484A1 (de) 1998-09-01 2000-03-09 Int Rectifier Corp Schottky-Diode
US20090134405A1 (en) * 2007-11-27 2009-05-28 Kabushiki Kaisha Toshiba Semiconductor substrate and semiconductor device
EP2259326A1 (fr) * 2008-03-17 2010-12-08 Mitsubishi Electric Corporation Dispositif à semi-conducteur
US20090256197A1 (en) * 2008-04-09 2009-10-15 Yoshito Nakazawa Semiconductor device and manufacturing method thereof
DE102009018971A1 (de) 2009-04-25 2010-11-04 Secos Halbleitertechnologie Gmbh Konstruktion einer Schottkydiode mit verbessertem Hochstromverhalten und Verfahren zu deren Herstellung
DE102009056603A1 (de) 2009-12-02 2011-06-09 Eris Technology Corp. Verfahren zur Herstellung einer Schottkydiode mit verbessertem Hochstromverhalten
JP2011129738A (ja) * 2009-12-18 2011-06-30 Nippon Inter Electronics Corp ショットキーバリアダイオード
US20150034970A1 (en) * 2011-05-18 2015-02-05 Rohm Co., Ltd. Semiconductor device and method for producing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110890361A (zh) * 2019-12-23 2020-03-17 苏州晶讯科技股份有限公司 一种多端口低容电压浪涌保护芯片及其制作方法
RU231051U1 (ru) * 2024-10-29 2024-12-28 Федеральное государственное унитарное предприятие "Всероссийский научно-исследовательский институт автоматики им. Н.Л. Духова" (ФГУП "ВНИИА") Диод Шоттки

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Publication number Publication date
RU2683377C1 (ru) 2019-03-28
EP3268991A1 (fr) 2018-01-17
DE102016110203B4 (de) 2019-11-21
DE102016110203A1 (de) 2016-12-08

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