WO2016206143A1 - Circuit de multiplexage de grille de transmission à base de polysilicium basse température et panneau d'affichage à cristaux liquides - Google Patents

Circuit de multiplexage de grille de transmission à base de polysilicium basse température et panneau d'affichage à cristaux liquides Download PDF

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Publication number
WO2016206143A1
WO2016206143A1 PCT/CN2015/083985 CN2015083985W WO2016206143A1 WO 2016206143 A1 WO2016206143 A1 WO 2016206143A1 CN 2015083985 W CN2015083985 W CN 2015083985W WO 2016206143 A1 WO2016206143 A1 WO 2016206143A1
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WO
WIPO (PCT)
Prior art keywords
transmission gate
multiplexing circuit
inverter
display panel
type transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/083985
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English (en)
Chinese (zh)
Inventor
田勇
赵莽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Publication of WO2016206143A1 publication Critical patent/WO2016206143A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an LTPS-based transmission gate multiplexing circuit and a liquid crystal display panel.
  • LTPS low temperature polysilicon
  • SOP System on Panel
  • the control signals of the general transmission gate type Demux (multiplexer) circuit in the LTPS display panel all need to be extracted from the IC (integrated circuit), which will cause excessive IC control signals in the LTPS display panel, and increase the IC. Design difficulty.
  • the present invention provides a transmission gate multiplexing circuit and a liquid crystal display panel based on LTPS, which are used to reduce the number of IC control signals and reduce the difficulty of IC design.
  • an LTPS-based transmission gate multiplexing circuit comprising:
  • a transfer gate comprising a pair of N-type transistors and P-type transistors having complementary structures
  • An inverter is disposed on a switch side of the transmission gate such that the same turn-on signal before and after the inversion performs control of the transmission gate multiplexing circuit.
  • the inverter is disposed in an array wiring area of the display panel.
  • the same turn-on signal is transmitted to the transfer gate multiplexing circuit through a wiring of a pad extension wiring region.
  • the same turn-on signal is transmitted through a wiring provided by the pad extension wiring region.
  • a wiring for transmitting the same turn-on signal in the pad extension wiring region extends to the array wiring region and is divided into two branches, one of which is reversed by the inverter The phase then reaches a switch side of the transmission gate and the other branch directly reaches the other switch side of the transmission gate.
  • the inverter is disposed on a switching side of the N-type transistor.
  • the inverter is disposed on a switching side of the P-type transistor.
  • the N-type transistor and the P-type transistor are MOSFET tubes.
  • the N-type transistor and the P-type transistor are TFT thin film transistors.
  • a liquid crystal display panel using the transmission gate multiplexing circuit of any of the above is also provided.
  • the invention reduces the number of control signals drawn from the IC side under the premise of ensuring the normal operation of the transmission gate multiplexing circuit, thereby reducing the number of control signal lines drawn from the IC side.
  • the invention effectively utilizes the vacant part of the WOA area for the design of the inverter for controlling the inversion processing of the signal before entering the transmission gate multiplexing circuit, thereby avoiding the vacant part of the bulk of the WOA area and reducing the The load effect phenomenon caused by uneven metal etching.
  • the transmission gate multiplexing circuit trace design provided by the invention reduces the input of the IC side control signal line, effectively shortens the height of the FOUT area, reduces the length of the lower border of the display panel, and is favorable for the display panel to be narrow. The design of the border.
  • FIG. 1 is a schematic structural diagram of a structure of an LTPS display panel in the prior art
  • FIG. 2 is a schematic diagram showing the design of a Demux circuit input to the AA area in the prior art
  • FIG. 3 is a schematic diagram of a Demux circuit design based on a transmission gate in the prior art
  • FIG. 5 is a schematic diagram of driving of a LTPS-based transmission gate multiplexing circuit in accordance with one embodiment of the present invention.
  • the GOA technology is a technology for realizing the progressive scan driving of the gate line by using the existing thin film transistor liquid crystal display Array (array substrate) process to fabricate the gate line scanning driving signal circuit on the Array substrate.
  • the present invention is described by taking an LTPS display panel having a GOA structure as an example, but the scope of application of the present invention is not limited thereto.
  • FIG. 1 is a schematic structural diagram of a LTPS display panel in the prior art, and includes: an AA area, a GOA area, a FOUT area, a WOA area, an IC area, and an FPC area.
  • the AA area is a display area for screen display, and is internally provided with a plurality of pixel units composed of red sub-pixels, green sub-pixels and blue sub-pixels;
  • the GOA area is a gate array area for generating TFTs in the display panel The gate drive signal of the (thin film transistor);
  • the FOUT area is the pad extension wiring area for the trace connection of the IC and the AA area data line;
  • the WOA (Wire On Array) area is the array wiring area for display The connection of the traces around the panel;
  • the IC area is an integrated circuit area for the binding of the IC, and the circuit and the TFT in the panel are driven by the IC;
  • the FPC (Flexible Printed Circuit Board) area is the flexible
  • FIG. 2 is a schematic diagram showing the design of a Demux (multiplexer selector) circuit input to the AA area in the prior art.
  • the Demux circuit uses a time-sharing principle to control one data line for three columns of pixels, such as R (red), G (green), and B (blue) in three columns of pixels.
  • the Demux circuit uses an NMOS type device for control of the Demux circuit. When a single NMOS or PMOS is used for transmission gate switch control, the parasitic capacitances Cgd and Cgs cause a feedthrough effect on the control signal line, causing severe distortion of the signal input to the AA area.
  • FIG. 3 is a schematic diagram of a Demux circuit design based on a transmission gate in the prior art.
  • the Demux circuit utilizes the complementary characteristics of the NMOS and the PMOS to ensure that the waveform of the D signal at the output of the data line signal is normally output. Since the feedthrough effects caused by the parasitic capacitances of NMOS and PMOS cancel each other out, the output waveform does not deform.
  • this Demux circuit control method has a disadvantage in that the number of required CK (clock) control signal lines will be twice that of the single NMOS or PMOS Demux circuit of FIG.
  • FIG. 4 is a schematic diagram of driving of a Demux circuit generally based on a transmission gate in the prior art.
  • each sub-pixel requires a Demux circuit.
  • the unit requires six CK control signal lines to be led out from the IC side.
  • the six CK control signal lines reach the Demux circuit control port via the FOUT area and the WOA area.
  • the circuit in Figure 4 adds three CK control signal lines relative to a single pass gate NMOS or PMOS Demux circuit. The resulting effect is that the IC control signal is too much, increasing the design difficulty of the IC.
  • FIG. 5 is a schematic diagram showing the driving of the LTPS-based transmission gate multiplexing circuit according to an embodiment of the present invention. The present invention will be described in detail below with reference to FIG. Wherein, one transmission gate multiplexing circuit corresponds to one sub-pixel in the control pixel unit.
  • the LTPS-based transmission gate multiplexing circuit includes a transmission gate and an inverter.
  • the transfer gate is composed of a pair of N-type transistors and P-type transistors having complementary structures.
  • the inverter is disposed on a switch side of the transmission gate such that the same turn-on signal before and after the inversion realizes control of the transmission gate multiplexing circuit. Specifically, the same turn-on signal directly reaches the switch side of one transistor in the transfer gate before inverting, and the same turn-on signal is inverted by the inverter and reaches the switch side of the other transistor in the transfer gate.
  • the inverter is disposed within the array wiring area of the display panel, that is, the inverter of FIG. 5 is disposed in the WOA area of FIG.
  • the inverter in the transmission gate multiplexing circuit is placed in the WOA area, effectively utilizing the free portion of the WOA area, avoiding wasting a large vacant portion of the WOA area. Since the inverter is disposed in the WOA region, the concentration of the etching liquid is reduced when the metal layer of the WOA region is formed, and the metal etching unevenness due to the uneven concentration of the etching liquid is reduced, thereby reducing Loading Effect due to uneven metal etching.
  • the same turn-on signal is transmitted to the transfer gate multiplexing circuit through the wiring of the pad extension wiring region.
  • the turn-on signal generated by the IC reaches the inverter located in the WOA area through the wiring disposed in the FOUT area.
  • the turn-on signal is inverted by the inverter and reaches the switch terminal of the N-type transistor or the P-type transistor in the transfer gate multiplexing circuit.
  • the same turn-on signal generated by the IC goes directly through the other branch to the switch terminal of the other transistor in the multiplexer circuit.
  • the same open letter is transmitted through a wiring provided by the pad extension wiring area. number.
  • the same turn-on signal generated by the IC is transmitted through a wire in the FOUT region, and after the wire enters the WOA region, the branch is led to the inverter. Setting a wire to transmit the same turn-on signal in the FOUT area can reduce the number of traces in the FOUT area, effectively shorten the height of the FOUT area, and reduce the length of the lower border of the display panel, which is beneficial to the design of the narrow frame.
  • the GOA is located on the left and right sides of the display panel, when the CK signal is used to control the GOA, it is more suitable to set the inverter in the transmission gate multiplexing circuit on both sides. WOA area.
  • a branch in the transmission gate where no inverter is provided is disposed in the WOA area, and the idle portion in the WOA area is utilized more fully to reduce the wiring setting in the FOUT area. That is to say, a wiring that transmits the same turn-on signal in the FOUT region extends to the WOA region and is divided into two branches, one of which is inverted by the inverter and reaches the switching side of a transistor in the transmission gate multiplexing circuit. The other branch directly reaches the switching side of the other transistor in the transmission gate multiplexing circuit.
  • the inverter is disposed on the switching side of the N-type transistor, that is, the output of the inverter disposed in the WOA region is coupled to the switching side of the N-type transistor.
  • the turn-on signal output by the IC is inverted by the inverter and reaches the switch side of the N-type transistor, and the same turn-on signal output by the IC directly reaches the switch side of the P-type transistor.
  • the inverter is disposed on the switching side of the P-type transistor, that is, the output of the inverter disposed in the WOA region is coupled to the switching side of the P-type transistor.
  • the turn-on signal output by the IC is inverted by the inverter and reaches the switch side of the P-type transistor.
  • the same turn-on signal output by the IC directly reaches the switch side of the N-type transistor.
  • the inverter is disposed on the switching side of the N-type transistor in the transmission gate or on the switching side of the P-type transistor, and is related to the set ON signal level.
  • the N-type transistor and the P-type transistor are MOSFET tubes. Specifically, a pair of N-type MOSFETs and P-type MOSFETs having complementary structures are used to form a transfer gate in the multiplexer circuit.
  • the N-type transistor and the P-type transistor are TFT thin film transistors. Specifically, a pair of transmission gates in a multiplexing circuit are fabricated using a pair of N-type TFT thin film transistors having complementary structures and P-type TFT thin film transistors. On the liquid crystal display panel, especially when more and more driving circuits are fabricated on an Array substrate by an Array process, a TFT thin film transistor is preferable.
  • the MOSFET can also be used when the pass gate multiplexing circuit is not disposed on the array substrate or in other types of circuits.
  • a liquid crystal display panel employing the above transmission gate multiplexing circuit.
  • the liquid crystal display panel reduces the number of CK control signal lines drawn from the IC side under the premise of ensuring the normal operation of the transmission gate multiplexing circuit.
  • the liquid crystal display panel also effectively utilizes the vacant part of the WOA area to design the inverter for inverting processing before the CK control signal enters the transmission gate multiplexing circuit, thereby avoiding the vacant part of the WOA area and reducing the vacant part of the WOA area. Small load effect due to uneven metal etching.
  • the liquid crystal display panel The input of the IC side signal line is reduced, the height of the FOUT area is effectively shortened, and the length of the lower border of the display panel is reduced, which is advantageous for the design of the narrow frame.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention concerne un circuit de multiplexage de grille de transmission à base de polysilicium basse température (LTPS) et un panneau d'affichage à cristaux liquides. L'invention concerne un circuit comprenant : une grille de transmission formée par un transistor de type N et un transistor de type P qui présentent des structures complémentaires ; et un onduleur, agencé sur un côté commutateur de la grille de transmission de manière à exécuter la commande du même signal d'ouverture avant et après inversion sur le circuit de multiplexage de grille de transmission. Le nombre de lignes de signal de commande de sortie est réduit, et la hauteur d'une zone FOUT est efficacement réduite ; la longueur d'une trame inférieure du panneau d'affichage est réduite, ce qui facilite la conception d'une trame étroite ; et une grande partie inoccupée dans une zone WOA est évitée, et le phénomène d'effet de charge provoqué par une gravure métallique irrégulière est réduit.
PCT/CN2015/083985 2015-06-26 2015-07-14 Circuit de multiplexage de grille de transmission à base de polysilicium basse température et panneau d'affichage à cristaux liquides Ceased WO2016206143A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510364820.3 2015-06-26
CN201510364820.3A CN104950496B (zh) 2015-06-26 2015-06-26 基于ltps的传输门多路复用电路及液晶显示面板

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113689820A (zh) * 2021-08-17 2021-11-23 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810173B (zh) * 2016-05-31 2018-08-14 武汉华星光电技术有限公司 多路复用型显示驱动电路
TWI710838B (zh) 2019-10-02 2020-11-21 友達光電股份有限公司 畫素陣列基板
CN115576444B (zh) * 2022-09-21 2025-10-28 武汉华星光电技术有限公司 触控显示面板
CN118785692B (zh) * 2023-03-29 2025-10-03 长鑫存储技术有限公司 电容结构及其制备方法、存储器
CN118116306A (zh) * 2024-02-28 2024-05-31 合肥维信诺科技有限公司 一种栅极驱动电路和显示面板

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Publication number Priority date Publication date Assignee Title
CN1428757A (zh) * 2001-12-26 2003-07-09 Lg.飞利浦Lcd有限公司 液晶显示器的数据驱动装置及方法
CN101375326A (zh) * 2006-01-31 2009-02-25 夏普株式会社 驱动电路、设置有驱动电路的显示设备
CN103226928A (zh) * 2013-03-13 2013-07-31 友达光电股份有限公司 显示器及其中的信号传送方法
CN103366701A (zh) * 2012-08-06 2013-10-23 友达光电股份有限公司 具多路复用器馈通效应补偿架构的显示装置与其驱动方法
US20140198135A1 (en) * 2013-01-17 2014-07-17 Ki-Myeong Eom Organic light emitting display device
CN104464597A (zh) * 2014-12-23 2015-03-25 厦门天马微电子有限公司 多路选择电路和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1428757A (zh) * 2001-12-26 2003-07-09 Lg.飞利浦Lcd有限公司 液晶显示器的数据驱动装置及方法
CN101375326A (zh) * 2006-01-31 2009-02-25 夏普株式会社 驱动电路、设置有驱动电路的显示设备
CN103366701A (zh) * 2012-08-06 2013-10-23 友达光电股份有限公司 具多路复用器馈通效应补偿架构的显示装置与其驱动方法
US20140198135A1 (en) * 2013-01-17 2014-07-17 Ki-Myeong Eom Organic light emitting display device
CN103226928A (zh) * 2013-03-13 2013-07-31 友达光电股份有限公司 显示器及其中的信号传送方法
CN104464597A (zh) * 2014-12-23 2015-03-25 厦门天马微电子有限公司 多路选择电路和显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113689820A (zh) * 2021-08-17 2021-11-23 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置

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