WO2017000852A1 - Procédé de fabrication de boîtier sur tranche à distribution en éventail - Google Patents

Procédé de fabrication de boîtier sur tranche à distribution en éventail Download PDF

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Publication number
WO2017000852A1
WO2017000852A1 PCT/CN2016/087232 CN2016087232W WO2017000852A1 WO 2017000852 A1 WO2017000852 A1 WO 2017000852A1 CN 2016087232 W CN2016087232 W CN 2016087232W WO 2017000852 A1 WO2017000852 A1 WO 2017000852A1
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WO
WIPO (PCT)
Prior art keywords
chip
layer
substrate
fabricating
wafer level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/087232
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English (en)
Chinese (zh)
Inventor
姜峰
陆原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Filing date
Publication date
Application filed by National Center for Advanced Packaging Co Ltd filed Critical National Center for Advanced Packaging Co Ltd
Publication of WO2017000852A1 publication Critical patent/WO2017000852A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body

Definitions

  • the invention discloses a method for fabricating a wafer level fan-out package, and the invention belongs to the technical field of microelectronic package.
  • Fan-out WLP is the next-generation platform that supports future integration, especially for wireless devices.
  • the object of the present invention is to overcome the deficiencies in the prior art and provide a wafer level package structure. Packaging method.
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip is fixed at a set position by an adhesive containing the same area as the chip, and the input and output end of the chip faces upward;
  • the layer of plastic sealing material encapsulates the chip, and the input and output ends of the chip are exposed;
  • the material of the substrate is silicon, ceramic, sapphire or glass material, and the thickness of the substrate is 100 um - 1 mm.
  • the binder is made of a liquid or film-like material mainly composed of an epoxy resin or a silica material, and the binder has a thickness of 5 um to 50 um.
  • the material of the plastic sealing material layer is a resin mainly composed of epoxy resin, and the thickness of the plastic sealing material layer is flush with the upper surface of the chip.
  • the layer of molding material is completed by a conventional filling process, a spraying process, a lamination process or a printing process.
  • the dielectric layer is made of silicon dioxide, phenol resin or polyimide, and the dielectric layer has a thickness of 1 um to 20 ⁇ m.
  • the lead wires are formed by conventional electroplating, printing or deposition processes.
  • step c the upper surface of the dielectric layer is covered with a protective layer.
  • the protective layer is made of silica, silicon nitride, phenol resin or polyimide, and the protective layer has a thickness of 2 um to 20 ⁇ m.
  • the packaging method of the invention can greatly reduce the process steps of the fan-out packaging process, greatly reduce the packaging cost, avoid the use of temporary bonding and debonding processes, and fix the chip on the substrate through the adhesive.
  • the position of the chip is fixed after being attached to the substrate, the patch precision is high, and the reliability of the package is ensured.
  • FIG. 1 is a schematic view showing the structure of a package obtained in the step a of the present invention.
  • FIG. 2 is a schematic view showing the structure of a package obtained in the step b of the present invention.
  • Figure 3 is a schematic view showing the structure of the package obtained in the step c of the present invention.
  • Figure 4 is a schematic view showing the structure of the package obtained in the step d of the present invention.
  • Figure 5 is a schematic view showing the structure of the package obtained in the step e of the present invention.
  • Figure 6 is a schematic view showing the structure of the package obtained in the step f of the present invention.
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip 1 is mounted on the upper surface of the substrate 6 by the adhesive 7, the input and output end of the chip 1 is upward, the material of the substrate 6 is silicon and the thickness is 100 um, and the material of the adhesive 7 is epoxy resin and thickness. 5um, as shown in Figure 1;
  • a conventional filling process on the upper surface of the substrate 6 forms a layer of the molding material 2
  • the layer of the molding material 2 encapsulates the chip 1, the input and output ends of the chip 1 are exposed, and the material of the layer 2 of the molding material is a resin mainly composed of epoxy resin. ,as shown in picture 2;
  • the dielectric layer 4 is made of silicon dioxide and having a thickness of 1 um, and the upper surface of the dielectric layer 4 is covered with a protective layer.
  • the protective layer 5 is made of silicon dioxide and has a thickness of 2 um, as shown in FIG. 3;
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip 1 is mounted on the upper surface of the substrate 6 by the adhesive 7, and the input and output ends of the chip 1 are facing
  • the material of the substrate 6 is ceramic and the thickness is 400 um
  • the material of the adhesive 7 is a liquid material mainly composed of silica material and has a thickness of 20 ⁇ m, as shown in FIG. 1;
  • the dielectric layer 4 is made of a phenol resin and having a thickness of 5 ⁇ m, and the upper surface of the dielectric layer 4 is covered with a protective layer 5
  • the protective layer 5 is made of silicon nitride and has a thickness of 5 um, as shown in FIG. 3;
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip 1 is mounted on the upper surface of the substrate 6 by the adhesive 7, the input and output end of the chip 1 is upward, the material of the substrate 6 is sapphire and the thickness is 700 um, and the material of the adhesive 7 is made of silicon dioxide.
  • the main film material and thickness is 40um, as shown in Figure 1;
  • the dielectric layer 4 is made of polyimide and has a thickness of 15 um, and the upper surface of the dielectric layer 4 is covered with a layer of protection.
  • Layer 5 the protective layer 5 is made of phenol resin and has a thickness of 15 um, as shown in FIG. 3;
  • a method for fabricating a wafer level fan-out package includes the following steps:
  • the chip 1 is mounted on the upper surface of the substrate 6 by the adhesive 7, the input and output end of the chip 1 is upward, the material of the substrate 6 is glass material and the thickness is 1 mm, and the material of the adhesive 7 is silica material. a predominantly membranous substance with a thickness of 50 um, as shown in Figure 1;
  • the dielectric layer 4 is made of polyimide and has a thickness of 20 um, and the upper surface of the dielectric layer 4 is covered with a layer of protection.
  • Layer 5 the material of the protective layer 5 is polyimide and the thickness is 20um, as shown in FIG. 3;

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

L'invention porte sur un procédé de fabrication d'un boîtier sur tranche à distribution en éventail, comprenant les étapes suivantes : montage d'une puce (1) sur une surface supérieure d'un substrat (6) à l'aide d'un liant (7) ; réalisation d'une formation d'encapsulation en plastique sur la surface supérieure du substrat (6), une couche de matériau d'encapsulation en plastique (2) encapsulant la puce (1) ; application d'un matériau diélectrique sur une surface supérieure de la couche de matériau d'encapsulation en plastique (2) pour former une couche diélectrique (4) ; enlèvement de la couche diélectrique (4) à des positions correspondant à des extrémités d'entrée et de sortie de la puce (1), puis formation d'une ligne de sortie (3) et d'une bille de soudure (8) au niveau des positions d'enlèvement ; réalisation d'un amincissement le long d'une surface inférieure du substrat (6) ; élimination du substrat (6), du liant (7) et d'une partie de la surface inférieure de la couche de matériau d'encapsulation en plastique (2) et de la puce (1) de manière qu'une surface de meulage finale soit présente au niveau d'une position prédéfinie de la puce (1) pour former un produit semi-fini encapsulé ; et découpe le long d'une ligne de découpe entre deux puces adjacentes sur le produit semi-fini encapsulé pour former des structures encapsulées individuelles à partir du produit semi-fini encapsulé. L'invention permet de réduire fortement les étapes de traitement dans le processus d'encapsulation à distribution en éventail et de réduire fortement les coûts d'encapsulation tout en garantissant la fiabilité d'encapsulation.
PCT/CN2016/087232 2015-07-01 2016-06-27 Procédé de fabrication de boîtier sur tranche à distribution en éventail Ceased WO2017000852A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510377660.6 2015-07-01
CN201510377660.6A CN105097566A (zh) 2015-07-01 2015-07-01 一种晶圆级扇出封装的制作方法

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Publication Number Publication Date
WO2017000852A1 true WO2017000852A1 (fr) 2017-01-05

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WO (1) WO2017000852A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
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CN114496820A (zh) * 2022-01-20 2022-05-13 甬矽半导体(宁波)有限公司 晶圆级芯片封装方法、晶圆级芯片封装结构和电子设备
CN115676774A (zh) * 2022-11-14 2023-02-03 美迪凯(浙江)智能光电科技有限公司 Mems器件光学穿孔封装工艺

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CN105097566A (zh) * 2015-07-01 2015-11-25 华进半导体封装先导技术研发中心有限公司 一种晶圆级扇出封装的制作方法
CN106876291B (zh) * 2016-12-30 2020-04-10 清华大学 一种薄芯片柔性扇出封装方法及所制备的封装结构
CN107300807A (zh) * 2017-06-01 2017-10-27 武汉华星光电技术有限公司 一种光学元件、液晶显示模组及蛾眼微结构的制备方法
CN107863363A (zh) * 2017-11-20 2018-03-30 苏州晶方半导体科技股份有限公司 芯片的封装结构及其制作方法
CN108108681A (zh) * 2017-12-14 2018-06-01 江西合力泰科技有限公司 具有高抵抗外力能力的生物识别模组及其制备方法
CN108321215B (zh) * 2018-03-07 2024-09-13 苏州晶方半导体科技股份有限公司 光学指纹识别芯片的封装结构及其制作方法
CN109659278A (zh) * 2018-12-26 2019-04-19 合肥矽迈微电子科技有限公司 多芯片堆叠封装方法及多芯片堆叠封装体
CN111128918B (zh) * 2019-12-31 2021-10-26 山东盛品电子技术有限公司 一种芯片封装方法及芯片
CN116994958A (zh) * 2022-04-26 2023-11-03 矽磐微电子(重庆)有限公司 内嵌式芯片封装方法及半导体结构

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CN114496820A (zh) * 2022-01-20 2022-05-13 甬矽半导体(宁波)有限公司 晶圆级芯片封装方法、晶圆级芯片封装结构和电子设备
CN115676774A (zh) * 2022-11-14 2023-02-03 美迪凯(浙江)智能光电科技有限公司 Mems器件光学穿孔封装工艺

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