WO2017107048A1 - Circuit de protection d'un contenu de mémoire - Google Patents

Circuit de protection d'un contenu de mémoire Download PDF

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Publication number
WO2017107048A1
WO2017107048A1 PCT/CN2015/098221 CN2015098221W WO2017107048A1 WO 2017107048 A1 WO2017107048 A1 WO 2017107048A1 CN 2015098221 W CN2015098221 W CN 2015098221W WO 2017107048 A1 WO2017107048 A1 WO 2017107048A1
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Prior art keywords
memory
resistor
cpu
power module
control signal
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Ceased
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PCT/CN2015/098221
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English (en)
Chinese (zh)
Inventor
顾学虎
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201580083222.7A priority Critical patent/CN108027780B/zh
Priority to PCT/CN2015/098221 priority patent/WO2017107048A1/fr
Publication of WO2017107048A1 publication Critical patent/WO2017107048A1/fr
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents

Definitions

  • the present invention relates to the field of electronic circuit technologies, and in particular, to a memory content protection circuit.
  • the majority of the boards in the network device adopts the form of the central processing unit CPU + external program/status information memory, and realizes the program/status information storage function of the small system.
  • These memories can be parallel, serial flash memory or electric memory.
  • a read-only ROM memory of the type such as an erasable programmable read-only memory EEPROM, or a synchronous static random access memory (SSRAM) using battery backup.
  • the inventor of the technical solution found in the research process that whether the CPU is a microprocessor MIPS architecture without internal interlocking pipeline level or an advanced reduced instruction set machine ARM architecture or an enhanced reduced instruction set computer RISC performance optimization POWERPC architecture,
  • the CPU core voltage Vcore is powered off before the CPU's input and output IO power supply pin voltage Vio-1 and the memory IO power supply pin voltage Vio-2, the CPU may be disordered by the kernel.
  • Some abnormal waveforms appear on the IO pins of the CPU and memory corresponding to the signal line between the CPU and the memory, and the abnormal waveform may cause the contents of the memory to be overwritten.
  • the invention discloses a memory content protection circuit for setting a memory to be prohibited from being accessed before the CPU core voltage Vcore is powered down, which is beneficial to improving the security of the memory content.
  • a first aspect of the present invention discloses a memory content protection circuit, including a first power module, a second power module, a central processing unit CPU, a power failure detection circuit, a control signal processing circuit, and a memory, wherein:
  • the first output end of the first power module is connected to the input end of the second power module, and the output end of the second power module is connected to the core voltage port of the CPU;
  • the second output end of the first power module is connected to the input end of the power failure detecting circuit
  • a signal output end of the power failure detecting circuit is connected to a first input end of the control signal processing circuit, and a signal output end of the CPU is connected to a second input end of the control signal processing circuit, where the control signal processing circuit is a signal output terminal is connected to the access control signal pin of the memory; a signal line is connected between the signal input/output IO pin of the control memory of the CPU and the IO pin of the memory;
  • the first power module is configured to supply power to the second power module
  • the second power module is configured to provide a core voltage to the CPU, where the power failure detection is performed.
  • the circuit is configured to send a reference control signal to the control signal processing circuit when the mother power source V1 provided by the first power module is lower than a preset threshold, the control signal processing circuit is configured to receive the reference control signal At the time, a disable access control signal for controlling the memory to be in an access disabled state is generated, and the disable access control signal is transmitted to the memory.
  • the power failure detecting circuit includes a resistor R1, a resistor R2, a capacitor C1, and a voltage comparator;
  • the control signal processing circuit includes an AND gate chip
  • the second output end of the first power module is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the first end of the resistor R2, the signal input end of the voltage comparator, and the capacitor a first end of the resistor R2, the second end of the resistor R2 is grounded, and a signal output end of the voltage comparator is connected to the first input end of the AND gate chip, the CPU The signal output end is connected to the second input end of the AND gate chip;
  • the signal output end of the AND gate chip is connected to a reset signal pin of the memory.
  • the power failure detecting circuit includes a resistor R1, a resistor R2, a capacitor C1, and a voltage comparator;
  • the control signal processing circuit includes an AND gate chip
  • the second output end of the first power module is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the first end of the resistor R2, the signal input end of the voltage comparator, and the capacitor a first end of C1, a second end of the resistor R2 and a second end of the capacitor C1 are grounded, the voltage ratio a signal output end of the comparator is connected to the first input end of the AND gate chip, and a signal output end of the CPU is connected to the second input end of the AND gate chip;
  • the signal output terminal of the AND gate chip is coupled to the chip select signal pin of the memory.
  • the AND gate chip includes any one of the following: a two-input gate chip and a four-input gate chip.
  • the power failure detecting circuit includes a resistor R1, a resistor R2, a capacitor C1, and a voltage comparator;
  • the control signal processing circuit includes a transmission gate chip and a pull-up resistor R3.
  • the second end of the resistor R1 is connected to the first end of the resistor R2, the signal input end of the voltage comparator, and the first end of the capacitor C1.
  • the second end of the resistor R2 and the second end of the capacitor C1 are grounded, and the signal output end of the voltage comparator is connected to the control signal input end of the transmission gate chip;
  • a signal output end of the CPU is connected to a transmission signal input end of the transmission gate chip
  • the signal output end of the transmission gate chip is connected to the chip select signal pin of the memory and the first end of the pull-up resistor R3, and the second end of the pull-up resistor R3 is connected to the IO power supply of the memory. Foot Vio-2.
  • the power failure detecting circuit is disposed inside the first power module.
  • the voltage comparator in the brownout detection circuit includes a voltage comparator in the watchdog chip, and the watchdog chip includes at least one of the following: AMD706, MAX793, and ST85.
  • the first power module includes a DC-DC conversion DC-DC power chip or an AC-DC conversion AC-DC power chip;
  • the second power module includes a DC-DC conversion DC-DC power chip.
  • the memory includes at least one of the following: a flash memory, an electrically erasable programmable read only memory (EEPROM), and a synchronous static random access memory (SSRAM).
  • a flash memory an electrically erasable programmable read only memory (EEPROM), and a synchronous static random access memory (SSRAM).
  • EEPROM electrically erasable programmable read only memory
  • SSRAM synchronous static random access memory
  • the signal line includes at least one of the following: a data signal line, an address signal line, a control signal line, and a clock signal line.
  • the first power module is used to supply power to the second power module; the second power module is used to provide a core voltage to the CPU; and the power failure detecting circuit is configured to when the voltage of the first power module is lower than a preset threshold. Transmitting a reference control signal to the control signal processing circuit; the control signal processing circuit is configured to generate, when the reference control signal is received, a disable access control signal for controlling the memory to be in an access disabled state, and send a disable access control signal to the memory .
  • the memory content protection circuit of the embodiment of the present invention can generate and send a disable access control signal to the memory when detecting that the mother power source V1 output by the first power module is lower than a preset threshold, thereby implementing a core voltage at the CPU.
  • Vcore is forbidden from accessing the memory before power-off. In this way, when the CPU core voltage Vcore is powered down, the abnormal waveform appearing on the CPU and memory IO pins corresponding to the signal line between the CPU and the memory rewrites the memory contents. It is beneficial to improve the security of memory content protection.
  • FIG. 1 is a structural diagram of a memory content protection circuit disclosed in a first embodiment of the present invention
  • FIG. 2 is a structural diagram of a memory content protection circuit disclosed in a second embodiment of the present invention.
  • FIG. 3 is a structural diagram of a memory content protection circuit according to a third embodiment of the present invention.
  • FIG. 4 is a structural diagram of a memory content protection circuit disclosed in a fourth embodiment of the present invention.
  • the invention discloses a memory content protection circuit for setting a memory to be prohibited from being accessed before the CPU core voltage Vcore is powered down, which is beneficial to improving the security of the memory content. The details are described below separately.
  • FIG. 1 is a structural diagram of a memory content protection circuit according to a first embodiment of the present invention.
  • the memory content protection circuit can include a first power module, a second power module, a central processing unit CPU, a power failure detection circuit, a control signal processing circuit, and a memory, wherein:
  • the first output end of the first power module is connected to the input end of the second power module, the output end of the second power module is connected to the core voltage port of the CPU; and the second output of the first power module is The terminal is connected to the input end of the power failure detecting circuit; the signal output end of the power failure detecting circuit is connected to the first signal input end of the control signal processing circuit, and the signal output end of the CPU is connected to the control signal processing circuit a second input end, a signal output end of the control signal processing circuit is connected to an access control signal pin of the memory; a connection between a signal input/output IO pin of the control memory of the CPU and an IO pin of the memory Have signal lines;
  • the memory content protection circuit shown in Figure 1 works as follows:
  • the first power module is configured to supply power to the second power module
  • the second power module is configured to provide a core voltage to the CPU
  • the power failure detecting circuit is configured to be provided by the first power module
  • sending a reference control signal to the control signal processing circuit where the control signal processing circuit is configured to generate, when the reference control signal is received, to control the memory to be disabled.
  • the state disables the access control signal and transmits the disable access control signal to the memory to disable the memory from being accessed.
  • the memory content protection circuit described in the embodiments of the present invention can be applied to a motherboard of various electronic devices such as a mobile phone, a tablet computer, a wearable device (a smart watch, a smart wristband, etc.), and a network device.
  • the power detection module is capable of generating and transmitting a disable access control signal to the memory when detecting that the mother power source V1 output by the first power module is lower than a preset threshold, thereby implementing The CPU core voltage Vcore is disabled from accessing the memory before power-off. In this way, it is possible to avoid abnormal waveforms appearing on the CPU and memory IO pins corresponding to the signal line between the CPU and the memory when the CPU core voltage Vcore is powered down. The situation of content occurs, which is beneficial to improve the security of memory content protection.
  • the input/output IO power supply pin of the CPU is connected to the IO power supply pin of the memory.
  • the specific implementation manners of the power-down detection circuit and the control signal processing circuit in the foregoing memory content protection circuit may be various, and the specifics of the power-down detection circuit and the control signal processing circuit described in the following embodiments are specific.
  • the structure is merely an example structure, and the specific implementation of the power failure detecting circuit and the control signal processing circuit is not limited in the present invention.
  • FIG. 2 is a structural diagram of a memory content protection circuit according to a second embodiment of the present invention.
  • the memory content protection circuit shown in FIG. 2 is optimized for the memory content protection circuit shown in FIG. 1.
  • the memory content protection circuit shown in FIG. Compared with the memory content protection circuit shown in FIG. 1, the memory content protection circuit shown in FIG. :
  • the power failure detecting circuit includes a resistor R1, a resistor R2, a capacitor C1, and a voltage comparator;
  • the control signal processing circuit includes an AND gate chip
  • the second output end of the first power module is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the first end of the resistor R2, the signal input end of the voltage comparator, and the capacitor a first end of the resistor R2, the second end of the resistor R2 is grounded, and a signal output end of the voltage comparator is connected to the first input end of the AND gate chip, the CPU The signal output end is connected to the second input end of the AND gate chip;
  • the signal output end of the AND gate chip is connected to a reset signal pin of the memory.
  • the resistor R1 and the resistor R2 are used for voltage division.
  • the memory content protection circuit shown in Figure 2 works as follows:
  • the signal output by the CPU is given to the gate chip, and the signal output from the power-down detection circuit is supplied to the gate chip, and the signal output from the gate chip is supplied to the memory;
  • the power failure detection circuit does not detect that the first power module is powered down (ie, when the output mother power source V1 is greater than or equal to a preset threshold), and the power failure detection circuit outputs a high level to the gate chip.
  • the output signal of the chip is controlled by the output signal of the CPU, that is, the CPU can operate the memory normally;
  • the power failure detecting circuit detects that the first power module is powered down, the power failure detecting circuit outputs a low level, and the memory receives the low level. After that, the setting memory contents are prohibited from being accessed.
  • the voltage comparator is internal to the watchdog chip.
  • a voltage comparator the voltage reference of the voltage comparator is 1.25V;
  • the preset threshold is 9V, that is, when the mother power source V1 drops to 9V, the voltage comparator should generate a first low level, and
  • the gate chip transmits the first low level, and when the AND gate chip receives the first low level, generates a second low level, and sends the second low level to a reset signal pin of the memory After the memory receives the second low level through the reset signal pin, setting the content of the memory to be prohibited from being accessed, thereby preventing access to the memory before the core voltage Vcore of the CPU is powered down, thus avoiding When the core voltage Vcore of the CPU is powered off, the abnormal waveform appearing on the CPU and the IO pin of the memory corresponding to the signal line between the CPU and the memory rewrites the memory contents, which is advantageous for improving the security
  • the AND gate chip includes any one of the following: a two-input gate chip and a four-input gate chip.
  • the power failure detecting circuit may be disposed inside the first power module.
  • the voltage comparator in the power failure detecting circuit includes a voltage comparator in the watchdog chip, and the watchdog chip includes at least one of the following: AMD706, MAX793, and ST85. .
  • the first power module includes a DC-DC conversion DC-DC power supply chip or an AC-DC conversion AC-DC power supply chip;
  • the second power module includes a DC-DC conversion DC-DC power chip.
  • the memory includes at least one of the following: a flash memory, an electrically erasable programmable read only memory (EEPROM), and a synchronous static random access memory (SSRAM).
  • a flash memory an electrically erasable programmable read only memory (EEPROM), and a synchronous static random access memory (SSRAM).
  • EEPROM electrically erasable programmable read only memory
  • SSRAM synchronous static random access memory
  • the signal line includes at least one of the following:
  • the signal input/output IO pin of the control memory of the CPU is a data signal pin of the CPU, and the IO pin of the memory is a data signal pin of the memory;
  • the signal input/output IO pin of the control memory of the CPU is an address signal pin of the CPU
  • the IO pin of the memory is an address signal pin of the memory
  • the signal input/output IO pin of the control memory of the CPU is a control signal pin of the CPU, and the IO pin of the memory is a control signal pin of the memory;
  • the signal input/output IO pin of the control memory of the CPU is a clock signal pin of the CPU, and the IO pin of the memory is a clock signal pin of the memory;
  • the female power source V1 provided by the first output end of the first power module is a 12V voltage signal
  • the female power source V1 provided by the second output end of the first power module is a 12V voltage signal.
  • the input/output IO power supply pin of the CPU is connected to the IO power supply pin of the memory.
  • the memory content protection circuit in the embodiment of the present invention can be applied to a motherboard of various electronic devices such as a mobile phone, a tablet computer, a wearable device (a smart watch, a smart wristband, etc.), a network device, and the like.
  • the voltage comparator detects that the mother power source V1 is lower than a preset threshold, and generates a first low level. And sending a first low level to the AND gate chip, after the gate chip receives the first low level, generating a second low level, and sending a second low level to the reset signal pin of the memory.
  • the memory receives the second low level, and the content of the set memory is prohibited from being accessed, thereby prohibiting access to the memory before the core voltage Vcore of the CPU is powered down.
  • the CPU and the memory can be avoided when the core voltage Vcore of the CPU is powered down.
  • the occurrence of an abnormal waveform appearing on the IO pin of the CPU and the memory corresponding to the signal line occurs to rewrite the memory contents, which is advantageous for improving the security of the memory content protection.
  • FIG. 3 is a structural diagram of a memory content protection circuit according to a third embodiment of the present invention.
  • the memory content protection circuit shown in FIG. 3 is optimized for the memory content protection circuit shown in FIG. 1.
  • the memory content protection circuit shown in FIG. Compared with the memory content protection circuit shown in FIG. 1, the memory content protection circuit shown in FIG. :
  • the power failure detecting circuit includes a resistor R1, a resistor R2, a capacitor C1, and a voltage comparator;
  • the control signal processing circuit includes an AND gate chip
  • the second output end of the first power module is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the first end of the resistor R2, the signal input end of the voltage comparator, and the capacitor a first end of the resistor R2, the second end of the resistor R2 is grounded, and a signal output end of the voltage comparator is connected to the first input end of the AND gate chip, the CPU The signal output end is connected to the second input end of the AND gate chip;
  • the signal output terminal of the AND gate chip is coupled to the chip select signal pin of the memory.
  • the resistor R1 and the resistor R2 are used for voltage division.
  • the memory content protection circuit shown in Figure 3 works as follows:
  • the signal output by the CPU is given to the gate chip, and the signal output from the power-down detection circuit is supplied to the gate chip, and the signal output from the gate chip is supplied to the memory;
  • the power failure detection circuit does not detect that the first power module is powered down (ie, when the output mother power supply V is greater than or equal to a preset threshold), and the power failure detection circuit outputs a high level to the gate chip.
  • the output signal of the chip is controlled by the output signal of the CPU, that is, the CPU can operate the memory normally;
  • the power failure detecting circuit detects that the first power module is powered down, the power failure detecting circuit outputs a low level, and the memory receives the low level. After that, the setting memory contents are prohibited from being accessed.
  • the voltage comparator is internal to the watchdog chip.
  • a voltage comparator the voltage reference of the voltage comparator is 1.25V;
  • the preset threshold is 9V, that is, when the mother power source V1 drops to 9V, the voltage comparator should generate a first low level, and
  • the gate chip transmits the first low level, and when the AND gate chip receives the first low level, generates a second low level, and sends the second low power to a chip select signal pin of the memory After the memory receives the second low level through the chip select signal pin, setting the content of the memory to be prohibited from being accessed, thereby prohibiting access to the memory before the core voltage Vcore of the CPU is powered down.
  • the AND gate chip includes any one of the following: a two-input gate chip and a four-input gate chip.
  • the power failure detecting circuit may be disposed inside the first power module.
  • the voltage comparator in the power failure detecting circuit includes a voltage comparator in the watchdog chip, and the watchdog chip includes at least one of the following: AMD706, MAX793, and ST85. .
  • the first power module includes a DC-DC conversion DC-DC Power chip or AC-DC conversion AC-DC power chip;
  • the second power module includes a DC-DC conversion DC-DC power chip.
  • the memory includes at least one of the following: a flash memory, an electrically erasable programmable read only memory (EEPROM), and a synchronous static random access memory (SSRAM).
  • a flash memory an electrically erasable programmable read only memory (EEPROM), and a synchronous static random access memory (SSRAM).
  • EEPROM electrically erasable programmable read only memory
  • SSRAM synchronous static random access memory
  • the signal line includes at least one of the following:
  • the signal input/output IO pin of the control memory of the CPU is a data signal pin of the CPU, and the IO pin of the memory is a data signal pin of the memory;
  • the signal input/output IO pin of the control memory of the CPU is an address signal pin of the CPU
  • the IO pin of the memory is an address signal pin of the memory
  • the signal input/output IO pin of the control memory of the CPU is a control signal pin of the CPU, and the IO pin of the memory is a control signal pin of the memory;
  • the signal input/output IO pin of the control memory of the CPU is a clock signal pin of the CPU, and the IO pin of the memory is a clock signal pin of the memory;
  • the female power source V1 provided by the first output end of the first power module is a 12V voltage signal
  • the female power source V1 provided by the second output end of the first power module is a 12V voltage signal.
  • the input/output IO power supply pin of the CPU is connected to the IO power supply pin of the memory.
  • the memory content protection circuit in the embodiment of the present invention can be applied to a motherboard of various electronic devices such as a mobile phone, a tablet computer, a wearable device (a smart watch, a smart wristband, etc.), a network device, and the like.
  • the voltage comparator detects that the mother power source V1 is lower than the preset threshold, generates a first low level, and sends a first low level to the AND gate chip, and the AND gate receives the first After the low level, generating a second low level, and sending a second low level to the chip select signal pin of the memory, the memory receiving the second low level, setting the content of the memory to be prohibited from being accessed, thereby realizing
  • the core voltage Vcore of the CPU is forbidden from accessing the memory before the power is turned off, and when the CPU core voltage Vcore is powered off, the abnormal waveform appearing on the CPU and the IO pin of the memory corresponding to the signal line between the CPU and the memory rewrites the memory contents. Occurs to improve the security of memory content protection.
  • FIG. 4 is a structural diagram of a memory content protection circuit according to a fourth embodiment of the present invention.
  • the memory content protection circuit shown in FIG. 4 is optimized for the memory content protection circuit shown in FIG. 1.
  • the memory content protection circuit shown in FIG. Compared with the memory content protection circuit shown in FIG. 1, the memory content protection circuit shown in FIG. :
  • the power failure detecting circuit includes a resistor R1, a resistor R2, a capacitor C1, and a voltage comparator;
  • the control signal processing circuit includes a transmission gate chip and a pull-up resistor R3;
  • the second end of the resistor R1 is connected to the first end of the resistor R2, the signal input end of the voltage comparator, and the first end of the capacitor C1, the second end of the resistor R2 and the capacitor C1 The two ends are grounded, and the signal output end of the voltage comparator is connected to the control signal input end of the transmission gate chip;
  • a signal output end of the CPU is connected to a transmission signal input end of the transmission gate chip
  • the signal output end of the transmission gate chip is connected to the chip select signal pin of the memory and the first end of the pull-up resistor R3, and the second end of the pull-up resistor R3 is connected to the IO power supply of the memory. Foot Vio-2.
  • the resistor R1 and the resistor R2 are used for voltage division.
  • the memory content protection circuit shown in Figure 4 works as follows:
  • the signal output by the CPU is sent to the transmission gate chip, and the signal output from the gate chip is transmitted to the memory, and the control signal of the transmission gate is controlled by the output signal of the power-down detection circuit;
  • the output signal of the CPU can be normally transmitted to the memory through the transmission gate
  • the power failure detecting circuit detects power failure, and outputs a control signal to the transmission gate chip.
  • the transmission gate chip After the transmission gate chip receives the control signal, the transmission gate chip cuts off the signal transmission of the CPU. a connection between the output terminal and the chip select signal pin of the memory, the output signal of the CPU cannot be transmitted to the transfer gate, and at this time, the control signal outputted by the transfer gate chip is pulled to a high level by the pull-up resistor. After the memory receives the high level, the set memory contents are prohibited from being accessed.
  • the voltage comparator is internal to the watchdog chip.
  • the voltage reference of the voltage comparator is 1.25V
  • the predetermined threshold is 9V, that is, when the mother power source V1 drops to 9V, the voltage comparator should generate a first low level and transmit to the a control signal input end of the gate chip transmits the first low level, and when the transfer gate chip receives the first low level, the transfer gate chip cuts off a signal output end of the CPU and a chip select of the memory a connection between signal pins, the transmission gate chip outputs a high impedance, an output signal of the transmission gate chip is pulled up to a high level by the resistor R3, and the memory receives the high level, the memory setting The memory content is forbidden to be accessed.
  • the power failure detecting circuit may be disposed inside the first power module.
  • the voltage comparator in the power failure detecting circuit includes a voltage comparator in the watchdog chip, and the watchdog chip includes at least one of the following: AMD706, MAX793, and ST85. .
  • the first power module includes a DC-DC conversion DC-DC power supply chip or an AC-DC conversion AC-DC power supply chip;
  • the second power module includes a DC-DC conversion DC-DC power chip.
  • the memory includes at least one of the following: a flash memory, an electrically erasable programmable read only memory (EEPROM), and a synchronous static random access memory (SSRAM).
  • a flash memory an electrically erasable programmable read only memory (EEPROM), and a synchronous static random access memory (SSRAM).
  • EEPROM electrically erasable programmable read only memory
  • SSRAM synchronous static random access memory
  • the signal line includes at least one of the following:
  • the signal input/output IO pin of the control memory of the CPU is a data signal pin of the CPU, and the IO pin of the memory is a data signal pin of the memory;
  • the signal input/output IO pin of the control memory of the CPU is an address signal pin of the CPU
  • the IO pin of the memory is an address signal pin of the memory
  • the signal input/output IO pin of the control memory of the CPU is a control signal pin of the CPU, and the IO pin of the memory is a control signal pin of the memory;
  • the signal input/output IO pin of the control memory of the CPU is a clock signal pin of the CPU, and the IO pin of the memory is a clock signal pin of the memory;
  • the female power source V1 provided by the first output end of the first power module is a 12V voltage signal
  • the female power source V1 provided by the second output end of the first power module is a 12V voltage signal.
  • the input/output IO power supply pin of the CPU is connected to the IO power supply pin of the memory.
  • the memory content protection circuit in the embodiment of the present invention can be applied to a motherboard of various electronic devices such as a mobile phone, a tablet computer, a wearable device (a smart watch, a smart wristband, etc.), a network device, and the like.
  • the voltage comparator detects that the mother power source V1 is lower than a preset threshold, and generates a first low level. And sending a first low level to the transmission gate chip, after the transmission gate chip receives the first low level, the transmission gate cuts off the signal output end of the CPU and the chip select signal pin of the memory In the connection, the transmission gate chip outputs a high impedance, the output signal of the transmission gate chip is pulled up to a high level by the pull-up resistor R3, and the memory receives the high level, and the content of the set memory is prohibited from being accessed.

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

La présente invention concerne un circuit de protection de contenu de mémoire qui consiste en un premier module de puissance, un second module de puissance, une unité centrale (UC), un circuit de détection de mise hors tension, un circuit de traitement du signal de commande et une mémoire. Une première extrémité de sortie du premier module de puissance est connectée à une extrémité d'entrée du second module de puissance et une extrémité de sortie du second module de puissance est connectée à un port de tension du cœur de l'UC. Une seconde extrémité de sortie du premier module de puissance est connectée à une extrémité d'entrée du circuit de détection de mise hors tension. Une extrémité de sortie du signal du circuit de détection de mise hors tension est connectée à une première extrémité d'entrée du circuit de traitement du signal de commande. Une extrémité de sortie du signal de l'UC est connectée à une seconde extrémité d'entrée du circuit de traitement du signal de commande. Une extrémité de sortie du signal du circuit de traitement du signal de commande est connectée à une extrémité d'entrée du signal de commande d'accès de la mémoire. Le circuit de protection de contenu de mémoire est destiné à régler la mémoire sur « accès interdit » avant la déconnexion de la tension de cœur de l'UC, facilitant le perfectionnement de la sécurité du contenu de mémoire.
PCT/CN2015/098221 2015-12-22 2015-12-22 Circuit de protection d'un contenu de mémoire Ceased WO2017107048A1 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110442217A (zh) * 2019-06-27 2019-11-12 芜湖康爱而电气有限公司 一种dsp芯片的外围电路结构
CN111796139A (zh) * 2020-07-28 2020-10-20 苏州浪潮智能科技有限公司 一种电压掉电监控电路及方法
CN112271704A (zh) * 2020-11-16 2021-01-26 深圳市德兰明海科技有限公司 一种掉电保护电路与集成芯片
CN114609465A (zh) * 2022-04-29 2022-06-10 中国工程物理研究院总体工程研究所 一种异常环境试验用存储测试系统的电源供电程控装置
CN117409833A (zh) * 2023-12-14 2024-01-16 合肥康芯威存储技术有限公司 一种嵌入式存储器及电子设备

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11593240B2 (en) * 2020-02-12 2023-02-28 Samsung Electronics Co., Ltd. Device and method for verifying a component of a storage device
CN113724751A (zh) * 2021-09-23 2021-11-30 珠海一微半导体股份有限公司 一种电源管理芯片、存储器保护系统及方法
CN115631779A (zh) * 2022-10-09 2023-01-20 深圳市广和通无线股份有限公司 数据保护电路、方法、装置、电子设备及存储介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007066232A (ja) * 2005-09-02 2007-03-15 Seiko Epson Corp データ処理装置
CN102033826A (zh) * 2010-12-03 2011-04-27 创新科存储技术有限公司 内存掉电数据保护的装置和方法
CN103135733A (zh) * 2012-12-21 2013-06-05 华为技术有限公司 掉电监控装置、方法及控制器
CN104391559A (zh) * 2014-11-11 2015-03-04 广东省电子信息产业集团有限公司 备用电源的控制方法和控制系统
CN104834369A (zh) * 2015-05-11 2015-08-12 北方信息控制集团有限公司 实时控制系统的掉电数据保护装置
US20150248920A1 (en) * 2014-02-28 2015-09-03 Kyocera Document Solutions Inc. Storage apparatus, image forming apparatus, abnormality detecting method by instantaneous power failure of hard disk, and abnormality recovery method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538677A (en) * 1978-09-13 1980-03-18 Hitachi Ltd Semiconductor memory with function of detecting power failure
CN101470501B (zh) * 2007-12-26 2010-12-15 珠海中慧微电子有限公司 一种延时复位控制电路及方法
CN102063933A (zh) * 2009-11-17 2011-05-18 智微科技股份有限公司 信号产生电路及相关储存装置
US8904161B2 (en) * 2010-10-20 2014-12-02 Samsung Electronics Co., Ltd. Memory system and reset method thereof to prevent nonvolatile memory corruption due to premature power loss
CN105138287B (zh) * 2012-07-22 2018-11-20 北京忆恒创源科技有限公司 存储设备、中断控制方法以及供电时间测量方法
CN103872785B (zh) * 2012-12-10 2017-02-22 华为技术有限公司 电能储存装置
CN104122967B (zh) * 2013-04-24 2019-04-05 深圳市祈飞科技有限公司 一种上电掉电复位控制电路及计算机
CN203376686U (zh) * 2013-05-31 2014-01-01 深圳市艾克姆科技发展有限公司 一种用于数据记忆保护的电压检测及数据选择电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007066232A (ja) * 2005-09-02 2007-03-15 Seiko Epson Corp データ処理装置
CN102033826A (zh) * 2010-12-03 2011-04-27 创新科存储技术有限公司 内存掉电数据保护的装置和方法
CN103135733A (zh) * 2012-12-21 2013-06-05 华为技术有限公司 掉电监控装置、方法及控制器
US20150248920A1 (en) * 2014-02-28 2015-09-03 Kyocera Document Solutions Inc. Storage apparatus, image forming apparatus, abnormality detecting method by instantaneous power failure of hard disk, and abnormality recovery method thereof
CN104391559A (zh) * 2014-11-11 2015-03-04 广东省电子信息产业集团有限公司 备用电源的控制方法和控制系统
CN104834369A (zh) * 2015-05-11 2015-08-12 北方信息控制集团有限公司 实时控制系统的掉电数据保护装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110442217A (zh) * 2019-06-27 2019-11-12 芜湖康爱而电气有限公司 一种dsp芯片的外围电路结构
CN111796139A (zh) * 2020-07-28 2020-10-20 苏州浪潮智能科技有限公司 一种电压掉电监控电路及方法
CN112271704A (zh) * 2020-11-16 2021-01-26 深圳市德兰明海科技有限公司 一种掉电保护电路与集成芯片
CN114609465A (zh) * 2022-04-29 2022-06-10 中国工程物理研究院总体工程研究所 一种异常环境试验用存储测试系统的电源供电程控装置
CN117409833A (zh) * 2023-12-14 2024-01-16 合肥康芯威存储技术有限公司 一种嵌入式存储器及电子设备
CN117409833B (zh) * 2023-12-14 2024-05-07 合肥康芯威存储技术有限公司 一种嵌入式存储器及电子设备

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