WO2017113758A1 - 转换电路及检测电路 - Google Patents

转换电路及检测电路 Download PDF

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Publication number
WO2017113758A1
WO2017113758A1 PCT/CN2016/090468 CN2016090468W WO2017113758A1 WO 2017113758 A1 WO2017113758 A1 WO 2017113758A1 CN 2016090468 W CN2016090468 W CN 2016090468W WO 2017113758 A1 WO2017113758 A1 WO 2017113758A1
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Prior art keywords
coupled
transistor
circuit
current
conversion circuit
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Ceased
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PCT/CN2016/090468
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English (en)
French (fr)
Inventor
皮涛
张孟文
詹昶
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Huiding Technology Co Ltd
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Priority to KR1020177024889A priority Critical patent/KR101957623B1/ko
Priority to EP16880555.4A priority patent/EP3255789B1/en
Publication of WO2017113758A1 publication Critical patent/WO2017113758A1/zh
Priority to US15/693,555 priority patent/US10349848B2/en
Anticipated expiration legal-status Critical
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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/02—Detecting, measuring or recording for evaluating the cardiovascular system, e.g. pulse, heart rate, blood pressure or blood flow
    • A61B5/024—Measuring pulse rate or heart rate
    • A61B5/02416—Measuring pulse rate or heart rate using photoplethysmograph signals, e.g. generated by infrared radiation
    • A61B5/02427—Details of sensor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
    • H03F1/086—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers with FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/005—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H03F3/082—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H03F3/087—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with IC amplifier blocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H03F3/3022—CMOS common source output SEPP amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/54—Input signal sampled and held with linear return to datum
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B2562/00—Details of sensors; Constructional details of sensor housings or probes; Accessories for sensors
    • A61B2562/02—Details of sensors specially adapted for in-vivo measurements
    • A61B2562/0233—Special features of optical sensors or probes classified in A61B5/00
    • A61B2562/0238—Optical sensor arrangements for performing transmission measurements on body tissue
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/249—A switch coupled in the input circuit of an amplifier being controlled by a circuit, e.g. feedback circuitry being controlling the switch
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/264—An operational amplifier based integrator or transistor based integrator being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/297—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage comprising a capacitor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/372—Noise reduction and elimination in amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/375—Circuitry to compensate the offset being present in an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/462—Indexing scheme relating to amplifiers the current being sensed

Definitions

  • the patent application belongs to the field of electronic technology, and in particular relates to a conversion circuit and a detection circuit capable of eliminating background light current.
  • wearable electronic devices have the function of heartbeat detection, which is to illuminate a light-emitting diode (LED) toward a human body and use a photodiode or a phototransistor to sense The light that penetrates or reflects from the human body is measured, and the optical signal (ie, photocurrent) sensed by the photodiode or the phototransistor is converted into a voltage signal by using a heartbeat detecting circuit.
  • heartbeat detection is to illuminate a light-emitting diode (LED) toward a human body and use a photodiode or a phototransistor to sense The light that penetrates or reflects from the human body is measured, and the optical signal (ie, photocurrent) sensed by the photodiode or the phototransistor is converted into a voltage signal by using a heartbeat detecting circuit.
  • LED light-emitting diode
  • the heartbeat detection circuit converts the photocurrent flowing through the photodiode or the phototransistor into a transimpedance amplifier (TIA), which is also called a current-to-voltage converter (Current-to-Voltage Converter). Voltage signal.
  • TIA transimpedance amplifier
  • the amplitude of the heartbeat signal is quite small and is susceptible to background light from the environment, while the transimpedance amplifier cannot eliminate the background light current and affect the accuracy of the heartbeat signal interpretation.
  • the transimpedance amplifier has higher power consumption and is more susceptible to noise. Therefore, the prior art has a need for improvement.
  • a first technical problem to be solved by some embodiments of the present invention is to provide a conversion circuit that eliminates the influence of background light current.
  • One embodiment of the present invention provides a conversion circuit for converting a current signal flowing through a sensing component into a first output voltage signal, the conversion circuit including:
  • a first current cancellation circuit for canceling a first current in the current signal, the first current cancellation circuit comprising:
  • a current driving circuit coupled between the sensing component and the current sampling and holding circuit
  • a second current cancellation circuit coupled to the sensing component for canceling a second current in the current signal
  • An integrating circuit coupled to the sensing component for integrating a third current in the current signal, having a first integrated output and a second integrated output, at the first integrated output
  • the first output voltage signal is output between the second integrated output terminals.
  • a photodiode for receiving reflected light and generating a current signal according to the reflected light
  • Fully differential amplifier circuit including:
  • the conversion circuit of some embodiments of the present invention can eliminate the background photocurrent and the substrate current in the current signal, and integrate the heartbeat current in the current signal by the integration circuit to eliminate the influence of the background photocurrent and the substrate current on the heartbeat current, and further Improve detection efficiency.
  • FIG. 1 is a schematic diagram of a detection circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a conversion circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the inverting amplifier of FIG. 2 according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of another inverting amplifier of FIG. 2 according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the buffer of FIG. 1 according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the fully differential amplifying circuit of FIG. 1 according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the analog-to-digital converter of FIG. 1 according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a detection circuit 10 according to an embodiment of the present invention.
  • the detecting circuit 10 can be used to detect the heartbeat of the human body, and includes a driving circuit 102, a light emitting diode LED, a photodiode PD, a conversion circuit 100, a fully differential amplifying circuit 104, and an analog to digital converter ADC.
  • the driving circuit 102 is coupled to the LEDs for generating a substrate signal SIG to drive the LEDs.
  • the light emitting diode LED generates incident light ⁇ 1 according to the substrate signal SIG, the incident light ⁇ 1 is irradiated to a specific part of the human body, such as the finger FG, and the finger FG can generate the reflected light ⁇ 2, and the photodiode PD is used to receive the reflected light ⁇ 2 and according to the reflected light ⁇ 2 A current signal I PD is generated.
  • the conversion circuit 100 is coupled to the photodiode PD for converting the current signal I PD into an output voltage V O1 and outputting the output voltage V O1 to the fully differential amplifying circuit 104.
  • the fully differential amplifying circuit 104 amplifies the output voltage V O1 . and a voltage V O2 to voltage V O2 outputs an analog digital converter ADC, analog digital converter ADC converts the analog signal into a digital voltage V O2 V O3, and outputs the digital signal V O3 to the rear end into the operating circuit for subsequent operation And processing.
  • the detection circuit 10 can include switches S1, S2 and buffers BF1, BF2, and the switches S1, S2 and the buffers BF1, BF2 are coupled between the conversion circuit 100 and the fully differential amplification circuit 104, for example, a switch S1 and the buffer BF1 are connected in series between the first output end of the conversion circuit 100 and the first input end of the fully differential amplifier circuit 104, and the switch S2 and the buffer BF2 are serially connected to the second output end of the 100 and the first of the 104 Between the two inputs.
  • the incident light ⁇ 1 generated by the LED is modulated light
  • the heartbeat signal of the human body is modulated on the base signal SIG to generate the reflected light ⁇ 2
  • the substrate current I SIG is the modulated substrate current associated with the signal SIG
  • the heartbeat current I HB is a useful signal that reflects the heartbeat of the human body.
  • the heartbeat current I HB appears relatively small with respect to the background photocurrent I BG and the substrate current I SIG .
  • the conversion circuit 100 can extract the heartbeat current I HB from the current signal I PD , that is, the heartbeat current I HB It is distinguished from the background photocurrent I BG and the substrate current I SIG .
  • the conversion circuit 100 may signal current I PD eliminate the background current I BG light and the base current I SIG, and the heartbeat signal current I PD of the current I HB integrates a result, the output voltage V O1 to Really reflects the heartbeat of the human body.
  • FIG. 2 is a schematic diagram of a conversion circuit 100 according to an embodiment of the present invention.
  • the conversion circuit 100 includes a current cancellation circuit 120 (corresponding to the first current cancellation circuit), a current cancellation circuit 122 (corresponding to the second current cancellation circuit), a noise suppression capacitor C AN1 (corresponding to the first noise suppression capacitor), and C AN2 (corresponding to the first The second noise suppression capacitor) and the integration circuit 124.
  • the current cancellation circuit 120, the current cancellation circuit 122 and the integration circuit 124 are all coupled to the photodiode PD, and the current cancellation circuit 120 is used to cancel the background photo current I BG (corresponding to the first current) in the current signal I PD , and the current cancellation circuit 122 to eliminate the background current I SIG signal current I PD (corresponding second current), the integrating circuit 124 to the current heartbeat signal current I PD is I HB (corresponding to the third current) is integrated, generating an output voltage V O1 (corresponding to the first output voltage) and outputting the output voltage V O1 to the integral output terminals N1, N2 of the integrating circuit 124, and the detecting circuit 10 transmits the output voltage V O1 through the switches S1, S2 and the buffers BF1, BF2 To the fully differential amplifying circuit 104.
  • the noise suppression capacitors C AN1 and C AN2 are respectively coupled to the integrated output terminals N1 and N2, and the noise suppression capacitors C AN1 and C AN2 are used to reduce the bandwidth of the entire conversion circuit 100, thereby reducing the position between the integrated output terminals N1 and N2. The energy of the noise, and the effect of suppressing noise.
  • the integrating circuit 124 includes an inverting amplifier INV, integrating capacitors C int1 , C int2 , integrating switches S int1 , S int2 , and switches S3 and S4 .
  • the inverting amplifier INV has an input end and an output end. As shown in FIG. 2, the integrating capacitors C int1 and C int2 are respectively coupled between the input end of the inverting amplifier INV and the integral output terminals N1 and N2, and the switches S3 and S4 are also The integrators S int1 and S int2 are respectively coupled between the integrating output terminals N1 and N2 and the output terminal of the inverting amplifier INV.
  • the integral switches S int1 and S int2 are respectively controlled by the signals Phi, Phi', wherein the signals Phi, Phi' are frequency signals that do not overlap each other.
  • the integral switch S int1 is turned off and the integrating switch S int2 is turned on, and the integrating circuit 124 integrates the heartbeat current I HB in the current signal I PD by using the integrating capacitor C int1 while suppressing the noise C AN1 suppresses the noise of the integral capacitor C int1 ; and in the second time, the integrating switch S int2 is turned off and the integrating switch S int1 is turned on, and the integrating circuit 124 integrates the heartbeat current I HB in the current signal I PD by using the integrating capacitor C int2 , At the same time, the noise suppression capacitor C AN2 suppresses the noise of the integral capacitor C int2 .
  • the noise suppression capacitors C AN1 and C AN2 are respectively coupled.
  • the noise suppression capacitors C AN1 , C AN2 do not generate an excessive step response (Step Response) to reduce the power consumption of the inverting amplifier INV, so the detection circuit 10 is coupled to the integral output.
  • the noise suppression capacitors C AN1 and C AN2 of terminals N1 and N2 achieve low power consumption and low noise performance.
  • the current cancellation circuit 122 can be implemented by an N-type field effect transistor, and the current cancellation circuit 122 can be controlled by the signal Phi'. In other words, the current cancellation circuit 122 can generate a current to offset the current signal I in the second time.
  • the substrate current I SIG in the PD can be implemented by an N-type field effect transistor, and the current cancellation circuit 122 can be controlled by the signal Phi'. In other words, the current cancellation circuit 122 can generate a current to offset the current signal I in the second time.
  • the substrate current I SIG in the PD is the current cancellation circuit 122 .
  • the current cancellation circuit 120 includes a current sample and hold circuit 140 and a current drive circuit 142.
  • the current sample and hold circuit 140 includes a transistor M7, a sample and hold capacitor CSH, and a sample and hold switch S SH1 .
  • the transistor M7 can be a P-type Field Effect Transistor
  • the sample-and-hold capacitor C SH is coupled between the source and the gate of the transistor M7
  • the sample-and-hold switch S SH1 is coupled.
  • the current driving circuit 142 is coupled between the current sample and hold circuit 140 and the photodiode PD.
  • the current driving circuit 142 includes transistors M8, M9, M10 and a sample and hold switch S SH2 .
  • the transistor M9 can be a P-type field effect transistor, and the transistors M8 and M10 can be an N-type Field Effect Transistor.
  • the transistor M9 is coupled between the source of the transistor M7 and the gate of the transistor M8.
  • the drain of the transistor M8 is coupled to the drain of the transistor M7, and the source of the transistor M8 and the gate of the transistor M10 are coupled to the photodiode. PD.
  • One end of the sample-and-hold switch S SH2 is coupled to the gate of the transistor M8 and the drain of the transistor M9, and the other end is coupled to the drain of the transistor M10.
  • the current cancel circuit 120 When the sample and hold switches S SH1 , S SH2 are simultaneously turned off, the current cancel circuit 120 rapidly generates a current to cancel the background photo current I BG in the current signal I PD .
  • the current cancellation circuit 120 is a fast current sample-and-hold circuit.
  • the equivalent capacitance inside the photodiode PD can be quickly charged to accelerate. The initialization time required by the conversion circuit 100, which in turn reduces power consumption.
  • the conversion circuit 100 uses the current cancellation circuit 120 to cancel the background photo current I BG in the current signal I PD , and the current cancellation circuit 122 to cancel the base current I SIG in the current signal I PD , and the current is integrated by the integration circuit 124 .
  • the heartbeat current I HB in the signal I PD is integrated to improve the detection efficiency.
  • the conversion circuit 100 suppresses noise by using the noise suppression capacitors C AN1 , C AN2 coupled to the integration outputs N1 and N2 to achieve low power consumption and low noise.
  • the implementation of the inverting amplifier INV in the integrating circuit 124 is not limited to a particular architecture.
  • FIG. 3, is a schematic diagram of the inverting amplifier 30.
  • the inverting amplifier 30 can be used to implement an inverting amplifier INV, the inverting amplifier 30 includes transistors M31, M32, the transistor M31 is a P-type field effect transistor, and the transistor M32 is an N-type field effect transistor.
  • the gate and the drain of the transistor M31 are respectively coupled to the gate and the drain of the transistor M32, the gates of the transistor M31 and the transistor M32 form the input terminal of the inverting amplifier 30, and the drains of the transistor M31 and the transistor M32 form an inverting amplifier.
  • the output of 30 is the input terminal of the inverting amplifier 30.
  • FIG. 4 is a schematic diagram of another inverting amplifier 40 according to an embodiment of the present invention.
  • the inverting amplifier 40 can also be used to implement an inverting amplifier INV.
  • the inverting amplifier 40 includes transistors M41 to M44 and a bias.
  • Circuit 400 is placed.
  • Bias circuit 400 includes transistors M45, M46 and resistors R1, R2. Among them, the transistors M41, M43, and M45 are P-type field effect transistors, and the transistors M42, M44, and M46 are N-type field effect transistors.
  • the gate of the transistor M41 is coupled to the gate of the transistor M42 to form an input terminal of the inverting amplifier 40, and the drain of the transistor M43 is coupled to the drain of the transistor M44 to form an output of the inverting amplifier 40. end.
  • the drain of the transistor M41 is coupled to the source of the transistor M43
  • the drain of the transistor M42 is coupled to the source of the transistor M44
  • the gate of the transistor M43 is coupled to the drain of the transistor M46
  • the gate of the transistor M44 is coupled to the gate of the transistor M44.
  • the gate of the transistor M45 is coupled to the gate of the transistor M46
  • the resistor R1 is coupled between the gate and the drain of the transistor M45
  • the resistor R2 is coupled to the gate and the drain of the transistor M46. between.
  • the transistors M41 and M42 form a cascode with the transistors M43 and M44, which can further improve the DC gain of the inverting amplifier, thereby reducing the signal between the first time and the second time of the integrating circuit 124.
  • the degree of coupling increases the linearity and signal to noise ratio of the integrating circuit 124.
  • the transistors M45 and M46 of the bias circuit 400 are mirror images of the transistors M41 and M42, respectively.
  • the voltage of the bias circuit 400 changes adaptively.
  • the circuit 400 can increase the dynamic range of the inverting amplifier 40.
  • resistors R1, R2 can pull the gate voltage of transistor M43 low and pull the gate voltage of transistor M44 high to prevent transistors M41, M42 from entering the linear region.
  • FIG. 5 is a schematic diagram of a buffer 50 according to an embodiment of the present invention.
  • the buffer 50 can be used to implement the buffer BF1 and Any of the BF2.
  • Buffer 50 includes switches 501, 503, 504, capacitor 502, and transistors 505, 506.
  • switches 501, 503 are closed and switch 504 is open, capacitor 502 sampling the output voltage of integrating circuit 124; and at the fourth time, switch 504 is closed and switches 501, 503 are open, buffer 50 is integrated
  • the output voltage of the circuit 124 is held and output to the fully differential amplifying circuit 104.
  • FIG. 6 is a schematic diagram of a fully differential amplifying circuit 60 according to an embodiment of the present invention.
  • the fully differential amplifying circuit 60 can be used to implement Fully differential amplifier circuit 104.
  • the fully differential amplifier circuit 60 includes a fully differential operational amplifier 610, capacitors 603, 606, 607, 603', 606', 607' and switches 601, 602, 604, 605, 608, 609, 601', 602', 604', 605', 608', 609'.
  • Switches 602, 605, 609, 602', 605', 609' are controlled by signal Phi, while switches 601, 604, 608, 601', 604', 608' are controlled by signal Phi'.
  • the switches 601, 604, 608, 601', 604', 608' are closed and the switches 602, 605, 609, 602', 605', 609' are open, the capacitors 603, 603' are from the buffer BF1
  • the output voltage of BF2 is sampled; in the first time, switches 602, 605, 609, 602', 605', 609' are turned off and switches 601, 604, 608, 601', 604', 608' are turned on, fully differential Amplifying circuit 104 transfers the charge stored in capacitors 603, 603' into capacitors 606, 606'.
  • FIG. 7 is a schematic diagram of an analog to digital converter 70 that can be used to implement an analog to digital converter ADC.
  • the analog to digital converter 70 includes a first correlation array 701, a second correlation array 702, a capacitance array 703, a comparator 704, and a logic module 705.
  • the first correlation array 701 and the second correlation array 702 each include a switch B1 BBN, and the first correlation array 701 and the second correlation array 702 are both coupled to the capacitor array 703, and the capacitor array 703 includes the capacitor C, 2C ⁇ 2 N C
  • the logic module 705 controls the conduction states of the switches B1 B BN in the first correlation array 701 and the second correlation array 702 according to the output result of the comparator 704 to convert the analog voltage V O2 into a digital signal V O3 .
  • the remaining operational details of analog to digital converter 70 are well known to those skilled in the art and are not described herein.
  • the conversion circuit of some embodiments of the present invention can eliminate the background photo current and the substrate current in the current signal, and integrate the heartbeat current in the current signal by the integration circuit to exclude the background photo current and the base current to the heartbeat.
  • the effect of current which in turn improves detection performance.
  • the conversion circuit further utilizes a noise suppression capacitor to suppress noise, achieving low power consumption and low noise.

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Abstract

本发明部分实施例提供了一种转换电路，用来将流经感测组件的电流信号转换成第一输出电压信号，包含：第一电流消除电路，用来消除电流信号中的第一电流，第一电流消除电路包含：电流采样保持电路；电流驱动电路，耦接于感测组件与电流采样保持电路之间；第二电流消除电路，耦接于感测组件，用来消除电流信号中的第二电流；积分电路，耦接于感测组件，用来对电流信号中的第三电流进行积分，在第一积分输出端和第二积分输出端之间输出第一输出电压信号。本发明部分实施例可消除电流信号中的背景光电流和基底电流，并利用积分电路对电流信号中的心跳电流进行积分，以排除背景光电流和基底电流对心跳电流的影响，进而提升检测效能。

Description

转换电路及检测电路 技术领域
本专利申请属于电子技术领域，尤其涉及一种可消除背景光电流的转换电路及检测电路。
背景技术
随着科技发展，穿戴式电子装置已具备心跳检测的功能，其是将发光二极管(Light-Emitting Diode，LED)朝人体内照射，利用光电二极管(Photo Diode)或光电晶体管(Photo Transistor)来感测穿透或反射自人体的光线，并利用心跳检测电路将光电二极管或光电晶体管所感测到的光信号(即光电流)转换成为电压信号。
现有技术中，心跳检测电路利用转阻放大器(Transimpedance Amplifier，TIA，转阻放大器又称为电流电压转换器(Current-to-Voltage Converter))将流经光电二极管或光电晶体管的光电流转换成为电压信号。然而，心跳信号的幅度相当微小，容易受到来自环境的背景光影响，而转阻放大器无法消除背景光电流，而影响对心跳信号判读的精准度。另外，转阻放大器的功耗较高，且较易受到噪声的影响。因此，现有技术实有改善的必要。
发明内容
本发明部分实施例所要解决的第一个技术问题在于提供一种转换电路，可消除背景光电流的影响。
本发明一个实施例提供了一种转换电路，用来将流经感测组件的电流信号转换成第一输出电压信号，所述转换电路包含有：
第一电流消除电路，用来消除所述电流信号中的第一电流，所述第一电流消除电路包含有：
电流采样保持电路；以及
电流驱动电路，耦接于所述感测组件与所述电流采样保持电路之间；
第二电流消除电路，耦接于所述感测组件，用来消除所述电流信号中的第二电流；
积分电路，耦接于所述感测组件，用来对所述电流信号中的第三电流进行积分，具有第一积分输出端和第二积分输出端，在所述第一积分输出端和所述第二积分输出端之间输出所述第一输出电压信号。
本发明部分实施例所要解决的第二个技术问题在于提供一种检测电路：包含有：
感光二极管，用来接收反射光并根据所述反射光产生电流信号；
如上所述的转换电路；
全差分放大电路，包含有：
第一输入端，耦接于所述转换电路的第一积分输出端；
第二输入端，耦接于所述转换电路的第二积分输出端；
第一输出端；以及
第二输出端。
本发明部分实施例的转换电路可消除电流信号中的背景光电流和基底电流，并利用积分电路对电流信号中的心跳电流进行积分，以排除背景光电流和基底电流对心跳电流的影响，进而提升检测效能。
附图说明
图1是本发明一个实施例提供的检测电路的示意图；
图2是本发明一个实施例提供的转换电路的示意图；
图3是本发明一个实施例提供的图2中反向放大器的示意图；
图4是本发明一个实施例提供的图2中另一反向放大器的示意图；
图5是本发明一个实施例提供的图1中缓冲器的示意图；
图6是本发明一个实施例提供的图1中全差分放大电路的示意图；
图7是本发明一个实施例提供的图1中模拟数字转换器的示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及部分实施例，对本发明进行进一步详细说明。应当理解，此处所描述的部分具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参考图1，图1为本发明一个实施例提供的检测电路10的示意图。检测电路10可用来检测人体的心跳，其包含驱动电路102、发光二极管LED、感光二极管PD、转换电路100、全差分放大电路104和模拟数字转换器ADC。
驱动电路102耦接于发光二极管LED，用来产生基底信号SIG以驱动发光二极管LED。发光二极管LED根据基底信号SIG产生入射光λ1，入射光λ1照射于人体的特定部位，如手指FG，而手指FG即可产生反射光λ2，感光二极管PD用来接收反射光λ2并根据反射光λ2产生电流信号IPD。转换电路100耦接于感光二极管PD，用来将电流信号IPD转换成输出电压VO1，并将输出电压VO1输出至全差分放大电路104，全差分放大电路104将输出电压VO1放大而成为电压VO2并将电压VO2输出至模拟数字转换器ADC，模拟数字转换器ADC将模拟电压VO2转换成数字信号VO3，并将数字信号VO3输出至后端运作电路以进行后续运算及处理。在一个实施例中，检测电路10可包含开关S1、S2和缓冲器BF1、BF2，开关S1、S2和缓冲器BF1、BF2耦接于转换电路100与全差分放大电路104之间，例如，开关S1和缓冲器BF1串接于转换电路100的第一输出端和全差分放大电路104的第一输入端之间，而开关S2和缓冲器BF2串接于100的第二输出端和104的第二输入端之间。
需注意的是，发光二极管LED所产生的入射光λ1为调制光，人体的心跳 信号调制于基底信号SIG上而产生反射光λ2，而感光二极管PD根据反射光λ2产生电流信号IPD。因此，电流信号IPD包含有背景光电流IBG、基底电流ISIG和心跳电流IHB(即IPD＝IBG+ISIG+IHB)，其中，背景光电流IBG为来自环境的背景光且经由感光二极管PD所造成的电流，基底电流ISIG为与信号SIG相关的调制基底电流，而心跳电流IHB才是反应出人体心跳的有用信号。然而，心跳电流IHB相对于背景光电流IBG和基底电流ISIG显得相当微小，在此情形下，转换电路100可从电流信号IPD将心跳电流IHB撷取出来，即将心跳电流IHB与背景光电流IBG及基底电流ISIG区分。换句话说，转换电路100可消除电流信号IPD中的背景光电流IBG和基底电流ISIG，并对电流信号IPD的心跳电流IHB进行积分，如此一来，输出电压VO1即可真实反应出人体心跳。
具体来说，请参考图2，图2为本发明一个实施例提供的转换电路100的示意图。转换电路100包含有电流消除电路120(对应第一电流消除电路)、电流消除电路122(对应第二电流消除电路)、抑噪电容CAN1(对应第一抑噪电容)、CAN2(对应第二抑噪电容)和积分电路124。电流消除电路120、电流消除电路122和积分电路124皆耦接于感光二极管PD，电流消除电路120用来消除电流信号IPD中的背景光电流IBG(对应第一电流)，电流消除电路122用来消除电流信号IPD中的基底电流ISIG(对应第二电流)，积分电路124用来对电流信号IPD中的心跳电流IHB(对应第三电流)进行积分，产生输出电压VO1(对应第一输出电压)并将输出电压VO1输出至积分电路124的积分输出端N1、N2之间，而检测电路10透过开关S1、S2和缓冲器BF1、BF2将输出电压VO1传递至全差分放大电路104。另外，抑噪电容CAN1、CAN2分别耦接于积分输出端N1、N2，抑噪电容CAN1、CAN2用来缩减转换电路100整体的带宽，进而减低位于积分输出端N1、N2之间噪声的能量，而达到抑制噪声的效果。
详细来说，积分电路124包含反向放大器INV、积分电容Cint1、Cint2、积分开关Sint1、Sint2以及开关S3、S4。反向放大器INV具有输入端和输出端，如图2所示，积分电容Cint1、Cint2分别耦接于反向放大器INV的输入端与积分输 出端N1、N2之间，开关S3、S4亦分别耦接于反向放大器INV的输入端与积分输出端N1、N2之间，而积分开关Sint1、Sint2分别耦接于积分输出端N1、N2与反向放大器INV的输出端之间。积分开关Sint1、Sint2分别受控于信号Phi、Phi’，其中信号Phi、Phi’为不相互重叠的频率信号。在此情形下，在第一时间中，积分开关Sint1关闭且积分开关Sint2打开，积分电路124利用积分电容Cint1对电流信号IPD中的心跳电流IHB进行积分，同时抑噪电容CAN1抑制积分电容Cint1的噪声；而在第二时间中，积分开关Sint2关闭且积分开关Sint1打开，积分电路124利用积分电容Cint2对电流信号IPD中的心跳电流IHB进行积分，同时抑噪电容CAN2抑制积分电容Cint2的噪声。
需注意的是，随着积分时间的拉长，积分输出端N1、N2两端点的电压差(即输出电压VO1)将会逐渐拉大，且抑噪电容CAN1、CAN2已分别耦接于积分输出端N1、N2，抑噪电容CAN1、CAN2不会产生过大的阶跃响应(Step Response)而可降低反向放大器INV的功耗，因此检测电路10利用耦接于积分输出端N1、N2的抑噪电容CAN1、CAN2实现低功耗和低噪声的效能。
另外，电流消除电路122可由N型场效应晶体管来实现，电流消除电路122可受控于信号Phi’，换句话说，电流消除电路122可于第二时间中，产生电流以抵销电流信号IPD中的基底电流ISIG。
电流消除电路120包含有电流采样保持(Current Sample and Hold)电路140和电流驱动电路142。电流采样保持电路140包含晶体管M7、采样保持电容CSH和采样保持开关SSH1。晶体管M7可为P型场效应晶体管(P-Type Field Effect Transistor)，采样保持电容CSH耦接于晶体管M7的源极(Source)与栅极(Gate)之间，采样保持开关SSH1耦接于晶体管M7的栅极与漏极(Drain)之间。电流驱动电路142耦接于电流采样保持电路140与感光二极管PD之间，电流驱动电路142包含有晶体管M8、M9、M10和采样保持开关SSH2。其中晶体管M9可为P型场效应晶体管，而晶体管M8、M10可为N型场效应晶体管(N-Type Field Effect Transistor)。晶体管M9耦接于晶体管M7的源极与晶体管M8的 栅极之间，晶体管M8的漏极耦接于晶体管M7的漏极，晶体管M8的源极和晶体管M10的栅极皆耦接于感光二极管PD。采样保持开关SSH2的一端耦接于晶体管M8的栅极和晶体管M9的漏极，而另一端耦接于晶体管M10的漏极。当采样保持开关SSH1、SSH2同时关闭时，电流消除电路120迅速地产生电流，以消除电流信号IPD中的背景光电流IBG。整体来说，电流消除电路120为一种快速电流采样保持电路，除了可消除电流信号IPD中的背景光电流IBG外，还可以对感光二极管PD内部的等效电容迅速地充电，以加速转换电路100所需的初始化时间，进而减小功耗。
由上述可知，转换电路100利用电流消除电路120来消除电流信号IPD中的背景光电流IBG，利用电流消除电路122来消除电流信号IPD中的基底电流ISIG，利用积分电路124对电流信号IPD中的心跳电流IHB进行积分，进而提升检测效能。更进一步地，转换电路100利用耦接于积分输出端N1、N2的抑噪电容CAN1、CAN2来抑制噪声，达到低功耗和低噪声的功效。
需注意的是，前述实施例是用以说明本发明部分实施例的概念，本领域技术人员当可据以做不同之修饰，而不限于此。例如，积分电路124中反向放大器INV的实现方式不限于特定架构，举例来说，请参考图3，图3为反向放大器30的示意图。反向放大器30可用来实现反向放大器INV，反向放大器30包含晶体管M31、M32，晶体管M31为P型场效应晶体管，而晶体管M32为N型场效应晶体管。晶体管M31的栅极和漏极分别耦接于晶体管M32的栅极和漏极，晶体管M31和晶体管M32的栅极形成反向放大器30的输入端，晶体管M31和晶体管M32的漏极形成反向放大器30的输出端。
另一方面，请参考图4，图4为本发明一个实施例另一反向放大器40的示意图，反向放大器40也可用来实现反向放大器INV，反向放大器40包含晶体管M41～M44和偏置电路400。偏置电路400包含晶体管M45、M46和电阻R1、R2。其中，晶体管M41、M43、M45为P型场效应晶体管，晶体管M42、M44、M46为N型场效应晶体管。
如图4所示，晶体管M41的栅极耦接于晶体管M42的栅极而形成反向放大器40的输入端，晶体管M43的漏极耦接于晶体管M44的漏极而形成反向放大器40的输出端。晶体管M41的漏极耦接于晶体管M43的源极，晶体管M42的漏极耦接于晶体管M44的源极，晶体管M43的栅极耦接于晶体管M46的漏极，晶体管M44的栅极耦接于晶体管M45的漏极，晶体管M45的栅极耦接于晶体管M46的栅极，电阻R1耦接于晶体管M45的栅极与漏极之间，电阻R2耦接于晶体管M46的栅极与漏极之间。
需注意的是，晶体管M41、M42与晶体管M43、M44形成共源共栅结构(Cascode)，能进一步提升反向放大器的直流增益，进而减少积分电路124在第一时间与第二时间之间信号的耦合程度，提高积分电路124的线性度和信噪比。另一方面，偏置电路400的晶体管M45、M46分别与晶体管M41、M42相互呈镜像关系，当晶体管M41～M44的电压变动时，偏置电路400的电压会适应性的随之变动，即偏置电路400可增加反向放大器40的动态范围。另外，电阻R1、R2可将晶体管M43的栅极电压拉低并将晶体管M44的栅极电压拉高，以防止晶体管M41、M42进入线性区。
另外，缓冲器BF1、BF2的实现方式不限于特定架构，举例来说，请参考图5，图5为本发明一个实施例提供的缓冲器50的示意图，缓冲器50可用来实现缓冲器BF1和BF2中的任一个。缓冲器50包含开关501、503、504、电容502和晶体管505、506。在第三时间时，开关501、503关闭而开关504打开，电容502对积分电路124的输出电压进行采样；而在第四时间时，开关504关闭而开关501、503打开，缓冲器50将积分电路124的输出电压保持并输出至全差分放大电路104。
另外，全差分放大电路104的实现方式不限于特定架构，举例来说，请参考图6，图6为本发明一个实施例提供的全差分放大电路60的示意图，全差分放大电路60可用来实现全差分放大电路104。全差分放大电路60包含全差分运算放大器610、电容603、606、607、603’、606’、607’以及开关601、602、 604、605、608、609、601’、602’、604’、605’、608’、609’。开关602、605、609、602’、605’、609’受控于信号Phi，而开关601、604、608、601’、604’、608’受控于信号Phi’。在第二时间中，开关601、604、608、601’、604’、608’关闭且开关602、605、609、602’、605’、609’打开，电容603、603’对来自缓冲器BF1、BF2的输出电压进行采样；在第一时间中，开关602、605、609、602’、605’、609’关闭且开关601、604、608、601’、604’、608’打开，全差分放大电路104将电容603、603’中所储存的电荷转移至电容606、606’中。透过信号Phi、Phi’控制开关，全差分放大电路60的电路架构可完全消除偏移电压(Offset)、有限增益和闪烁噪声(Flicker Noise)所带来的影响，进而增进全差分放大电路的效能。
另外，模拟数字转换器ADC的实现方式不限于特定架构，举例来说，请参考图7，图7为模拟数字转换器70的示意图，模拟数字转换器70可用来实现模拟数字转换器ADC。模拟数字转换器70包含第一相关数组701、第二相关数组702、电容数组703、比较器704和逻辑模块705。第一相关数组701和第二相关数组702均包含开关B1～BN，且第一相关数组701和第二相关数组702均耦接于电容数组703，电容数组703包含电容C、2C～2NC，逻辑模块705根据比较器704的输出结果控制第一相关数组701和第二相关数组702中开关B1～BN的导通状态，将模拟电压VO2转换成数字信号VO3。模拟数字转换器70其余操作细节为本领域技术人员所熟知，故不在此赘述。
综上所述，本发明部分实施例的转换电路可消除电流信号中的背景光电流和基底电流，并利用积分电路对电流信号中的心跳电流进行积分，以排除背景光电流和基底电流对心跳电流的影响，进而提升检测效能。另外，转换电路进一步利用抑噪电容来抑制噪声，达到低功耗和低噪声的功效。
以上仅为本发明的部分较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (19)

  1. 一种转换电路，用来将流经感测组件的电流信号转换成第一输出电压信号，所述转换电路包括：
    第一电流消除电路，用来消除所述电流信号中的第一电流，所述第一电流消除电路包括：
    电流采样保持电路；以及
    电流驱动电路，耦接于所述感测组件与所述电流采样保持电路之间；
    第二电流消除电路，耦接于所述感测组件，用来消除所述电流信号中的第二电流；
    积分电路，耦接于所述感测组件，用来对所述电流信号中的第三电流进行积分，所述积分电路具有第一积分输出端和第二积分输出端，其中所述第一积分输出端和所述第二积分输出端用于输出所述第一输出电压信号。
  2. 如权利要求1所述的转换电路，其中，所述积分电路包括：
    反向放大器，包括输入端和输出端；
    第一积分电容，耦接于所述反向放大器的输入端与所述第一积分输出端之间；以及
    第二积分电容，耦接于所述反向放大器的输入端与所述第二积分输出端之间。
  3. 如权利要求2所述的转换电路，其中，所述积分电路还包括：
    第一积分开关，耦接于所述反向放大器的输出端与所述第一积分输出端之间；以及
    第二积分开关，耦接于所述反向放大器的输出端与所述第二积分输出端之间。
  4. 如权利要求2或3所述的转换电路，其中，所述反向放大器包括：
    第一晶体管，包括第一端、第二端和第三端；以及
    第二晶体管，包括：
    第一端，电性连接于所述第一晶体管的第一端；
    第二端，耦接于所述第一晶体管的第二端；以及
    第三端；
    其中，所述第一晶体管的第一端和所述第二晶体管的第一端为所述反向放大器的输入端。
  5. 如权利要求4所述的转换电路，其特征在于，所述第一晶体管的第二端和所述第二晶体管的第二端为所述反向放大器的输出端。
  6. 如权利要求4或5所述的转换电路，其中，所述反向放大器还包括：
    第三晶体管，包括：
    第一端；
    第二端；以及
    第三端，耦接于所述第一晶体管的第二端；以及
    第四晶体管，包括：
    第一端；
    第二端，耦接于所述第三晶体管的第二端；以及
    第三端，耦接于所述第二晶体管的第二端。
  7. 如权利要求6所述的转换电路，其中，所述第三晶体管的第二端和所述第四晶体管的第二端为所述反向放大器的输出端。
  8. 如权利要求6或7所述的转换电路，其中，所述第三晶体管的第一端和所述第四晶体管的第一端耦接于偏置电路。
  9. 如权利要求8所述的转换电路，其中，所述偏置电路包含有：
    第五晶体管，包括：
    第一端；
    第二端，耦接于所述第四晶体管的第一端；以及
    第三端；
    第六晶体管，包括：
    第一端，耦接于所述第五晶体管的第一端；
    第二端，耦接于所述第三晶体管的第一端；以及
    第三端；
    第一电阻，耦接于所述第五晶体管的第一端与第二端之间；以及
    第二电阻，耦接于所述第六晶体管的第一端与第二端之间。
  10. 如权利要求1到9任一项所述的转换电路，其中，所述电流采样保持电路包含有：
    第七晶体管，包括第一端、第二端及第三端；
    采样保持电容，耦接于所述第七晶体管的第一端与第三端之间；以及
    第一采样保持开关，耦接于所述第七晶体管的第一端与第二端之间。
  11. 如权利要求10所述的转换电路，其中，所述电流驱动电路包括：
    第八晶体管，包括：
    第一端；
    第二端，耦接于所述第七晶体管的第二端；以及
    第三端，耦接于所述感测组件；以及
    第九晶体管，包括：
    第一端；
    第二端，耦接于所述第八晶体管的第一端；以及
    第三端；
    第二采样保持开关，耦接于所述第八晶体管的第一端；以及
    第十晶体管，包括：
    第一端，耦接于所述感测组件；
    第二端，耦接于所述第二采样保持开关；以及
    第三端。
  12. 如权利要求1到11任一项所述的转换电路，其中，所述第二电流消除电路包括晶体管，所述晶体管受控于频率信号。
  13. 如权利要求1到12任一项所述的转换电路，其中，所述感测组件为感光二极管。
  14. 如权利要求1所述的转换电路，其中，还包括：
    第一抑噪电容，耦接于所述第一积分输出端；以及
    第二抑噪电容，耦接于所述第二积分输出端。
  15. 一种检测电路，包括：
    感光二极管，用来接收反射光并根据所述反射光产生电流信号；
    如权利要求1～14任一项所述的转换电路；
    全差分放大电路，包括：
    第一输入端，耦接于所述转换电路的第一积分输出端；
    第二输入端，耦接于所述转换电路的第二积分输出端；
    第一输出端；以及
    第二输出端。
  16. 如权利要求15所述的检测电路，其中，还包括模拟数字转换器，耦接于所述全差分放大电路的第一输出端与第二输出端之间。
  17. 如权利要求15或16所述的检测电路，其中，还包括：
    第一开关，耦接于所述转换电路的第一积分输出端与所述全差分放大电路的第一输入端之间；以及
    第二开关，耦接于所述转换电路的第二积分输出端与所述全差分放大电路的第二输入端之间。
  18. 如权利要求15，16或17所述的检测电路，其中，还包括：
    第一缓冲器，耦接于所述转换电路的第一积分输出端与所述全差分放大电路的第一输入端之间；以及
    第二缓冲器，耦接于所述转换电路的第二积分输出端与所述全差分放大电路的第二输入端之间。
  19. 如权利要求15到18任一项所述的检测电路，其中，还包括：
    发光二极管，用来产生入射光至人体，所述人体产生所述反射光；以及
    驱动电路，耦接于所述发光二极管。
PCT/CN2016/090468 2015-12-29 2016-07-19 转换电路及检测电路 Ceased WO2017113758A1 (zh)

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