WO2017113846A1 - 同面电极光电二极管阵列及其制作方法 - Google Patents

同面电极光电二极管阵列及其制作方法 Download PDF

Info

Publication number
WO2017113846A1
WO2017113846A1 PCT/CN2016/097517 CN2016097517W WO2017113846A1 WO 2017113846 A1 WO2017113846 A1 WO 2017113846A1 CN 2016097517 W CN2016097517 W CN 2016097517W WO 2017113846 A1 WO2017113846 A1 WO 2017113846A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
heavily doped
conductivity type
type heavily
semiconductor region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/097517
Other languages
English (en)
French (fr)
Inventor
张岚
李元景
刘以农
胡海帆
李军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nuctech Co Ltd
Original Assignee
Nuctech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nuctech Co Ltd filed Critical Nuctech Co Ltd
Priority to US15/580,848 priority Critical patent/US10411051B2/en
Priority to JP2017562301A priority patent/JP6577601B2/ja
Priority to EP16880639.6A priority patent/EP3399552B1/en
Publication of WO2017113846A1 publication Critical patent/WO2017113846A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/107—Integrated devices having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/103—Integrated devices the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/189—X-ray, gamma-ray or corpuscular radiation imagers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/147—Shapes of bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes

Definitions

  • Embodiments of the present invention relate to photodiodes, and more particularly to a coplanar electrode photodiode array structure and a method of fabricating the same.
  • the semiconductor photodiode array generates visible light rays in the scintillator by direct incident light or X-rays, and ionizes with atoms in the semiconductor to generate unbalanced carriers to detect incident light.
  • Key parameters for measuring the performance of a photodiode array include resolution, signal-to-noise ratio, readout speed, and crosstalk between pixels.
  • the uniformity of charge collection in dark current and single-pixel internal light collection active regions is also important.
  • an isotropic electrode photodiode array comprising a plurality of coplanar electrode photodiodes, each coplanar electrode photodiode comprising: a first conductivity type heavily doped semiconductor substrate; a first conductive type lightly doped semiconductor layer formed on the conductive type heavily doped semiconductor substrate; a second conductive type heavily doped semiconductor region formed on an upper portion of the first conductive type lightly doped semiconductor layer, wherein a second conductivity type heavily doped semiconductor region and the first conductivity type lightly doped semiconductor layer form a PN junction diode, and a second electrode is drawn from the second conductivity type heavily doped semiconductor layer on a light incident side; a first conductive type heavily doped semiconductor region of the second conductive type heavily doped semiconductor region, and a first electrode is drawn from the first conductive type heavily doped semiconductor region on a light incident side; and is disposed at the second A trench structure between the conductive heavily doped semiconductor region and the first conductive type heavily doped semiconductor region.
  • the trench structure is formed by filling a trench with an insulating material or a plurality of composite insulating materials, or a light reflecting material.
  • the trench structure is formed by filling a trench with a heavily doped single crystal semiconductor or polycrystalline semiconductor material of a first conductivity type.
  • the trench structure includes and forms a heavily doped region of a first conductivity type around the trench.
  • the trench structure comprises an unfilled trench and is covered with an insulating layer, a multilayer composite insulating layer or a light reflecting material at the bottom and sidewalls of the trench.
  • a heavily doped region of a first conductivity type is formed around the trench, and an insulating layer, a multilayer composite insulating layer, or a light reflecting material is overlaid on the bottom and sidewalls of the trench.
  • the trench structure comprises a trench, and the bottom and sidewalls of the trench are covered with an insulating material, or a plurality of composite insulating materials, or light reflecting materials, and then by a single crystal semiconductor material or a polycrystalline semiconductor. The material fills the trench.
  • the single crystal semiconductor material or polycrystalline semiconductor material filling the trench is connected to a high potential with respect to the second electrode.
  • a thinner first conductive type heavily doped region or a second conductive type lightly doped region is formed on an upper portion of the second conductive type heavily doped semiconductor region, and the periphery is heavily doped by the second conductive type Surrounded by miscellaneous areas.
  • a continuous first conductive type heavily doped region is formed under the second conductive type heavily doped region, or a first conductive type heavily doped region is disposed only under the second conductive type heavily doped region.
  • a continuous region of insulating material is formed under the second conductivity type heavily doped region, or a section of insulating material is disposed only under the second conductive type heavily doped region.
  • the first conductive type heavily doped region is formed as a trench structure extending down to and connected to the first conductive type heavily doped region or insulating material region.
  • a conductive structure with a continuous insulating layer is formed, or only a conductive structure with an insulating layer is disposed under the second conductive type heavily doped region,
  • the conductive structure is composed of an insulating material or a semiconductor material.
  • the first conductive type heavily doped region is a trench structure that extends down to and is connected to a region of semiconductor material in a conductive structure with an insulating layer.
  • a method of fabricating a coplanar electrode photodiode comprising the steps of: forming a first conductivity type lightly doped semiconductor layer on a first conductivity type heavily doped semiconductor substrate; The upper portion of the first conductive type lightly doped semiconductor layer forms a second conductive type heavily doped semiconductor region, wherein the second conductive type heavily doped semiconductor region and the first conductive type lightly doped semiconductor layer form a PN junction diode And a second electrode is drawn from the second conductive type heavily doped semiconductor layer on the light incident side; a first conductive type heavily doped semiconductor region is formed around the second conductive type heavily doped semiconductor region, and the first electrode Extracting from the first conductivity type heavily doped semiconductor region on the light incident side; and at the second conductive A trench structure is disposed between the heavily doped semiconductor region and the first conductive type heavily doped semiconductor region.
  • FIG. 1A is a top plan view of a photodiode illustrating an embodiment of the present invention
  • Figure 1B is a schematic view for explaining a cross-sectional A-A' structure of a photodiode in question
  • FIG. 2 is a schematic view for explaining a configuration of a photodiode according to the first and second embodiments
  • FIG. 3 is a schematic view for explaining a configuration of a photodiode according to a third embodiment
  • FIG. 4 is a schematic view for explaining a configuration of a photodiode according to a fourth embodiment
  • FIG. 5 is a schematic view for explaining a configuration of a photodiode according to a fifth embodiment
  • FIG. 6 is a schematic view for explaining a configuration of a photodiode according to a sixth embodiment
  • FIG. 7 is a schematic diagram for explaining the photo-response of the edge portion of the photodiode light collecting active region involved;
  • FIG. 8 is a schematic diagram for explaining the collection efficiency of the edge portion of the photodiode light collecting active region involved.
  • FIG. 9 is a schematic view for explaining a configuration of a photodiode according to a seventh embodiment.
  • FIG. 10 is a schematic view for explaining a configuration of a photodiode according to an eighth embodiment.
  • FIG. 11 is a schematic view for explaining a configuration of a photodiode according to a ninth embodiment
  • FIG. 12 is a schematic view for explaining a configuration of a photodiode according to a tenth embodiment
  • FIG. 13 is a schematic view for explaining a configuration of a photodiode according to the eleventh embodiment
  • N+ type semiconductor layer 2. N-type semiconductor layer, 3. N+ type semiconductor region, 4. P+ type semiconductor region, 5. an insulating layer, a multilayer composite insulating layer or a light reflecting material, 6. Space charge Area, 7. an insulating layer, a multilayer composite insulating layer or a light reflecting material, or a P+ type semiconductor material, 8. a void region, a 10.N+ or P+ doped single crystal semiconductor material or a polycrystalline semiconductor material, 11. Thinner N+ type semiconductor region or P-type semiconductor region, 12.N+ type semiconductor region or insulating material region such as silicon dioxide or silicon nitride, 13.N-type semiconductor layer, 14, silicon dioxide, silicon nitride, etc. Insulating material, 15.
  • the photodetecting channel corresponding to the pixel is formed in the epitaxial silicon wafer of the first conductivity type.
  • the epitaxial wafer is a low resistivity substrate, a high resistivity epitaxial type epitaxial wafer.
  • the method includes: ion implantation of a first conductivity type, forming a heavily doped region on a surface of the silicon epitaxial wafer, having a majority carrier generated by incident of the detected light to perform a collection region; and a second conductivity type ion implantation in the silicon Forming a heavily doped region on the surface of the epitaxial wafer, forming a PN junction with the epitaxial wafer of the first conductivity type, and setting its corresponding injection position in the manner of the photodetection channel, having minority carriers generated by the incidence of the detected light A collection area is performed, which is a light collecting active area.
  • the two types of conductive type heavily doped regions cannot be placed adjacent to prevent a tunneling effect, and in the meantime are high resistance epitaxial materials of the semiconductor substrate.
  • the PN junction of the photodiode array can operate in a reverse bias mode, forming a wider space charge region under reverse bias conditions in the vicinity of the light collecting active region in the pixel; the PN junction of the photodiode array can also operate in a zero bias mode. A narrower built-in space charge region under zero bias conditions is formed near the light collecting active region in the pixel.
  • the silicon semiconductor Light enters the silicon semiconductor through the incident window, and collides with silicon atoms in the light collecting active region to generate electron hole pairs.
  • the electrons will be in the built-in electric field or an external bias electric field to the first conductivity type.
  • the heavily doped region drifts or diffuses and is eventually collected; and the holes drift or diffuse into the heavily doped region of the second conductivity type under the built-in electric field or the applied bias electric field, and are finally collected, thereby reading out the electrical signal.
  • the doping distance between the first conductivity type and the second conductivity type may be large, and the carriers excited at the edge positions of the pixel active regions are easily collected by adjacent pixels in the photodiode array; Captured by traps or defects in the silicon body.
  • the coplanar electrode photodiode array includes a plurality of coplanar electrode photodiodes, each coplanar electrode photodiode comprising: a first conductivity type heavily doped semiconductor substrate; and a first conductivity type heavily doped semiconductor a first conductive type lightly doped semiconductor layer formed on the substrate; a second conductive type heavily doped semiconductor region formed on an upper portion of the first conductive type lightly doped semiconductor layer, wherein the second conductive type heavily doped semiconductor Forming a PN junction diode with the first conductivity type lightly doped semiconductor layer, and extracting a second electrode from the second conductivity type heavily doped semiconductor layer on a light incident side; heavily doping around the second conductivity type a first conductive type heavily doped semiconductor region of the semiconductor region, and a first electrode is drawn from the first conductive type heavily doped semiconductor region on a light incident side; and is disposed in the second conductive type heavily doped semiconductor region and a trench structure between the first conductive type heavily doped semiconductor regions.
  • FIG. 1A and 1B show a single cell structure of a photodiode array in question, wherein FIG. 1A shows a top view and FIG. 1B shows a cross-sectional view taken along line AA' of FIG. 1A.
  • the photodiode structure is fabricated on an N-type epitaxial wafer comprising an N+ type semiconductor substrate region 1 and an N-type epitaxial semiconductor substrate region 2.
  • the thickness of the N+ type semiconductor substrate region is in the range of about 300 to 575 ⁇ m
  • the specific resistance is 0.002 to 0.005 ⁇ cm
  • the thickness of the N-type epitaxial semiconductor region is in the range of about 20 to 100 ⁇ m
  • the specific resistance is about 1 k ⁇ cm.
  • the term "high impurity concentration (heavily doped)” means, for example, an impurity concentration of about 1 ⁇ 10 17 cm -3 or more, and a "+” is added to the conductivity type.
  • the “low impurity concentration (lightly doped)” means, for example, an impurity concentration of about 1 ⁇ 10 17 cm -3 or less, and a "-" is added to the conductivity type.
  • Phosphorus (P) or arsenic (As) or the like is present as the N-type impurity, and boron (B) or the like is present as the P-type impurity.
  • N + -type semiconductor region 3 and a P + -type semiconductor region 4 are formed on the upper side of the N-type epitaxial semiconductor region 2.
  • the P + -type semiconductor region 4 and the N-type epitaxial semiconductor region 2 form a PN junction.
  • the thickness of the N+ type semiconductor region 3 is about 0.5 to 3 ⁇ m
  • the thickness of the P+ type semiconductor region 4 is about 0.2 to 1 ⁇ m
  • the pitch of the N+ type semiconductor region 3 and the P + type semiconductor region 4 is about 10 to 100 ⁇ m.
  • a trench 7 is formed by etching and filling between the N + -type semiconductor region 3 and the P + -type semiconductor region 4, and the trench depth is about 4 to 20 ⁇ m.
  • An insulating layer, a multi-layer composite insulating layer or a light-reflecting material 5 is deposited on the surface of the photodiode, and has a thickness ranging from about 50 to 200 nm, for isolating external impurities into the silicon semiconductor substrate and, in addition, as a metal electrode insulator. In addition, depending on the optical and insulating properties, it can also be designed as a light-reflecting antireflection film.
  • the N+ type semiconductor region 3 is taken out by the metal electrode 21, and the P+ type semiconductor region 4 is taken out through the metal electrode 22.
  • the PN junction position of the internal pixel of the photodiode will form the space charge region 6. Since the impurity concentration of the P+ type semiconductor region is much larger than that of the N-type epitaxial semiconductor region 2, the space is The charge region mainly expands into the N-type epitaxial semiconductor region 2, and the expanded width increases as the reverse bias voltage increases.
  • FIG. 2 is a view showing the configuration of a photodiode according to the first embodiment.
  • Photodiode array The light collecting active region is only the space charge region 6 formed directly under the P+ type semiconductor region 4, and the region between the N+ type semiconductor region 3 and the P+ type semiconductor region 4 is an excessive region of charge collection, not charge collection. Active area.
  • the metal electrode 21 on the N+ type semiconductor region 3 is taken out to block the incidence of light, and thus is not an active region for charge collection.
  • the P+ type semiconductor region 4 that is, the light collecting active region, a large number of electron hole pairs are excited in the N-type epitaxial semiconductor region 2 and the P+ type semiconductor region 4, since the light wavelength ranges from 200 to 600 nm.
  • the absorption depth in the N-type epitaxial semiconductor region 2 is shallow.
  • the electron carriers drift toward the N+ type semiconductor region 3 by the built-in electric field or the applied electric field, and are finally collected by the metal electrode 21.
  • the hole carriers drift toward the P+ type semiconductor region 4 by the built-in electric field and the applied electric field, and are finally collected by the metal electrode 22 and output as a signal.
  • the hole carrier lifetime is small and some of the hole carriers are trapped by the trap.
  • Hole carriers generated near the center of the active region are more easily collected by the P+ type semiconductor region 4, and hole carriers generated in the vicinity of the active region edge and in the non-active region may also be collected by adjacent pixels. Or captured by traps in adjacent pixels.
  • a trench structure is formed on the high-resistance semiconductor epitaxial material between the two types of heavily doped regions of the conductive type, and silicon oxide, silicon nitride, or the like, an insulating material. , or a variety of composite insulation materials, or light reflective materials.
  • the trench 7 is formed, and silicon oxide, silicon nitride, or the like, an insulating material, or a plurality of composite insulating materials, or Light reflective material is filled.
  • silicon oxide, silicon nitride, or the like, an insulating material, or a plurality of composite insulating materials, or Light reflective material is filled.
  • the hole carrier range control is formed, the partial hole carrier signal loss is effectively prevented, and the hole carrier is increased.
  • the probability of collecting the active region increases the photoresponse and collection efficiency of the edge of the active region, thereby balancing the charge collection consistency at different locations in the active region of the pixel.
  • a trench structure is formed on the high resistance semiconductor epitaxial material between the two conductivity type heavily doped regions, and the single conductivity type may be heavily doped with the single crystal semiconductor or Crystal semiconductor filling.
  • the heavily doped region of the first conductivity type facilitates the diffusion of hole carriers arriving here in the opposite direction (ie, the direction of the active region), thereby improving the photoresponse and collection efficiency of the edge position of the active region.
  • a trench 7 is formed by etching and filling between the N+ type semiconductor region 3 and the P+ type semiconductor region 4, and the trench 7 can be filled with an N+ type single crystal semiconductor or a polycrystalline semiconductor.
  • the P+ type single crystal semiconductor or the polycrystalline semiconductor filled in the trench has no electrode extraction, and is equivalent to a floating state in the structure, and is isolated in the physical structure when the hole carriers diffuse or drift to the edge of the P+ type semiconductor structure. Under the driving of the energy band, the hole carriers arriving here are pushed to diffuse in the opposite direction (ie, the active region direction), thereby improving the photoresponse and collection efficiency of the edge position of the active region.
  • FIG. 3 is a schematic view for explaining a configuration of a photodiode according to a third embodiment.
  • a trench structure is formed on the high-resistance semiconductor epitaxial material between the two types of heavily doped regions, which may be made of silicon oxide, silicon nitride, or the like, an insulating material. , or a plurality of composite insulating materials, or light reflecting materials, and forming a heavily doped region of the same type as the epitaxial wafer doping around the trench.
  • the heavily doped region of the first conductivity type facilitates pushing the hole carriers arriving in the opposite direction (ie, the active region). Diffusion, thereby improving the photoresponse and collection efficiency of the edge position of the active region.
  • a trench 7 is formed by etching and filling between the N+ type semiconductor region 3 and the P+ type semiconductor region 4, and then N+ ion implantation is performed to form an N+ type semiconductor at the bottom and sidewalls of the trench.
  • the N+ type semiconductor region 31 has a thickness of about 0.1 to 1 ⁇ m. It is then filled with silicon oxide, silicon nitride, or the like, an insulating material, or a plurality of composite insulating materials, or a light reflecting material.
  • the hole carriers diffuse or drift to the edge of the N+ type semiconductor structure 31, the hole carriers arriving here are pushed in the opposite direction (ie, the active area direction) under the driving of the physical structure isolation and the energy band of the trench. Diffusion, which in turn increases the photoresponse and collection efficiency at the edge of the active region.
  • a trench structure is formed on the high-resistance semiconductor epitaxial material between the two types of heavily doped regions, and may be formed by a void structure and covered at the bottom of the gap and the sidewall A layer of insulating layer, a multilayer composite insulating layer or a light reflecting material.
  • a void structure is formed on the high-resistance semiconductor epitaxial material between the two types of heavily doped regions, and may be formed by a void structure and covered at the bottom of the gap and the sidewall A layer of insulating layer, a multilayer composite insulating layer or a light reflecting material.
  • a trench is formed between the N+ type semiconductor region 3 and the P+ type semiconductor region 4 by etching and filling, and then silicon oxide, silicon nitride, etc. are grown at the bottom and sidewalls of the trench, an insulating layer. Material, or a variety of composite insulating materials, or light reflecting materials 5.
  • the trench is a void structure 8.
  • An insulating material such as silicon oxide or silicon nitride, a plurality of composite insulating materials or light reflecting materials 5 having a thickness ranging from 0.1 to 1 ⁇ m about.
  • the trench void structure can well limit the range of movement of hole carriers in the epitaxial layer 2 of the semiconductor substrate, effectively prevent the loss of partial hole carrier signals, and increase the probability that hole carriers are collected by the active region.
  • the optical response and collection efficiency of the edge position of the active region are improved, thereby balancing the charge collection consistency at different positions of the active region of the pixel.
  • FIG. 5 is a schematic view for explaining a configuration of a photodiode according to the fifth embodiment.
  • a trench structure is formed on the high-resistance semiconductor epitaxial material between the two types of heavily doped regions of the conductive type, and may be composed of a void structure, covering the bottom of the gap and the sidewall A layer of insulating layer, or a plurality of layers of composite insulating layer, or a light-reflecting material, and forming a heavily doped region of the same type as the epitaxial wafer doping around the trench.
  • the physical isolation can effectively block the diffusion of hole carriers to the non-active region.
  • the heavily doped region of the second conductivity type increases the hole energy band of the trench region, which is favorable for driving the hole carrier to reach here.
  • the carriers diffuse in the opposite direction (ie, in the direction of the active region).
  • a trench is formed between the N+ type semiconductor region 3 and the P+ type semiconductor region 4 by etching and filling, and then N+ ion implantation is performed to form an N+ type semiconductor region at the bottom and sidewalls of the trench. 32.
  • the N+ type semiconductor region 32 has a thickness of about 0.1 to 1 ⁇ m.
  • an insulating material such as silicon oxide or silicon nitride, a plurality of composite insulating materials or light reflecting materials 32 are grown on the bottom and sidewalls of the trench.
  • the trench is a void structure 8.
  • the hole carriers diffuse or drift to the edge of the N+ type semiconductor structure 32, the hole carriers arriving here are pushed in the opposite direction (ie, the active region) under the physical structure isolation of the trench gap and the driving of the energy band. Dim) diffusion, which in turn increases the photoresponse and collection efficiency at the edge of the active region.
  • FIG. 6 is a schematic view for explaining a configuration of a photodiode according to a sixth embodiment.
  • a trench structure is formed on the high-resistance semiconductor epitaxial material between the two types of heavily doped regions, and an insulating layer may be covered on the bottom and sidewalls of the trench.
  • a multilayer composite insulating layer, or a light reflecting material and then filling the trenches with a single crystal semiconductor material or a polycrystalline semiconductor material.
  • hole carriers can be effectively blocked from diffusing into the non-active region, and further, the single crystal semiconductor material or the polycrystalline semiconductor material is opposite to the second conductive electrode (light-doped region extraction electrode corresponding to light collection) It can be connected to the zero point, the floating state, or the high potential. By introducing an applied electric field, it is beneficial to push the hole carriers arriving here to diffuse in the opposite direction (ie, the active region), thereby increasing the edge position of the active region. Light response and collection efficiency.
  • a trench is formed between the N+ type semiconductor region 3 and the P+ type semiconductor region 4 by etching and filling, and then silicon oxide, silicon nitride, etc. are grown at the bottom and sidewalls of the trench, an insulating layer. Material, or a plurality of composite insulating materials, or light reflecting materials 34.
  • the trench void may be filled by the N+ or P+ type single crystal semiconductor or the polycrystalline semiconductor 10, and the N+ or P+ type single crystal or polycrystalline semiconductor 10 will have an applied potential Control can be zero-biased, floating, or forward-biased.
  • the N+ or P+ type single crystal or polycrystalline semiconductor 10 When the N+ or P+ type single crystal or polycrystalline semiconductor 10 is forward biased, an electric field is generated in the semiconductor interior from the N+ or P+ type single crystal or polycrystalline semiconductor 10 to the P+ type semiconductor region 4, thereby forming a hole.
  • a carrier diffuses or drifts to silicon oxide, silicon nitride, etc., an insulating material, or a plurality of composite insulating materials, or the edge of the light reflecting material 34, it is driven by the physical structure isolation of the trench void and the electric field.
  • the hole carriers arriving here diffuse in the opposite direction (ie, the direction of the active region), thereby improving the photoresponse and collection efficiency at the edge position of the active region.
  • FIG. 7 and 8 show the corresponding photoresponse and photo-collection efficiency of light in a photodiode device having a trench (first embodiment) and a trench-free structure at different incident positions of the edge of the active region of the pixel. It can be seen from the comparison results that the trench isolation structure can improve the collection probability of hole carriers at the edge of the active region of the pixel, improve the light response and collection efficiency of the edge position of the active region, and thereby balance the charge collection consistency of different positions of the pixel.
  • FIG. 9 is a schematic view for explaining a configuration of a photodiode according to a seventh embodiment.
  • a thinner first conductive type heavily doped region or a second conductive type lightly doped region is formed on the top layer of the light collecting active region. Since defects such as defects or ions are easily introduced into the surface of the device during processing, these defects form a trapping center and reduce the amount of charge collected by the electrodes.
  • a thinner first doped region of the first conductivity type is formed on the top layer of the heavily doped region of the second conductivity type, and when the pixel is biased or reverse biased, the upper limit of the boundary of the internal space charge region does not reach the semiconductor surface, and the hole is reduced.
  • the probability that a charge is trapped by a structural defect The formation of a thinner second conductivity type lightly doped region on the top layer of the second conductivity type heavily doped region can suppress the diffusion of holes to the device surface, thereby reducing the probability of hole charges being trapped by structural defects.
  • a thin N+ type semiconductor region 11 is formed by ion implantation, which region is surrounded by the P+ type semiconductor region 4.
  • the N+ type semiconductor region 11, the P+ type semiconductor region 4, and the N-type semiconductor substrate epitaxial layer 2 constitute an N+/P+/N- structure, and the inside of the P+ semiconductor region 4 is formed regardless of the pixel structure at zero or reverse bias.
  • the upper boundary of the space charge region is confined below the surface of the pixel device, reducing the probability of hole charge being trapped by the device surface defect.
  • a thin P-type semiconductor region 11 which is surrounded by the P + -type semiconductor region 4 can be formed on the top layer of the P + -type semiconductor region 4 by controlling the ion implantation energy.
  • the P-type semiconductor region 11, the P+ type semiconductor region 4 and the N-type semiconductor substrate epitaxial layer 2 constitute a P-/P+/N- structure regardless of whether the pixel structure is zero-biased or reverse-biased, and the built-in electric field can be The hole diffusion is suppressed from drifting to the surface of the device, thereby reducing the probability that hole charges are trapped by structural defects.
  • FIG. 10 is a schematic view for explaining a configuration of a photodiode according to the eighth embodiment.
  • a first conductive type heavily doped region is disposed under the second conductive type heavily doped region and the first conductive type heavily doped region, or only in the second conductive type heavy
  • a first conductivity type heavily doped region is disposed under the doped region.
  • the first conductive type heavily doped region may be a semiconductor such as single crystal silicon, polycrystalline silicon or germanium.
  • the structure can thin the charge sensitive region and reduce the hole charge trapped by the trap of the underlying first conductive type lightly doped region.
  • a heavily doped first conductivity type heavily doped region will push the hole charge to drift toward the second conductivity type heavily doped region, reducing charge collection time.
  • the thinned first conductivity type lightly doped region increases the effective resistance between the two electrodes, further reducing dark current.
  • the first conductive type heavily doped region in the pixel may be a trench structure extending to the first conductive type heavily doped region of the layer, completely isolating the inter-pixel structure, further reducing the charge crosstalk effect between pixels.
  • the first conductive type heavily doped region of the layer may be replaced by an insulating material such as silicon dioxide or silicon nitride.
  • the substrate 1 of the semiconductor substrate may be an N+ type region or an N-type region.
  • a layer of the N+ type semiconductor region 12 is provided at a position of 5 to 20 ⁇ m below the N + -type semiconductor region 3 and the P + -type semiconductor region 4 of the pixel, and may be a semiconductor material such as single crystal silicon, polycrystalline silicon or germanium.
  • the N + -type semiconductor region 3 and the N + -type semiconductor region 12 in such a pixel have potentials equivalent.
  • the electron holes excited by the photon in the N-type semiconductor region 13 are driven by the built-in electric field or the applied electric field, respectively, to the N+ type semiconductor region 3 and the P+ type semiconductor region 4, respectively.
  • the N+ type semiconductor region 12, the N-type semiconductor region 13, and the P+ type semiconductor region 4 constitute an N+/N-/P+ structure, and the N+ type semiconductor region 12 pushes the hole carriers toward the P+ type semiconductor region 4 in the upward direction (ie, The active region is diffused, which in turn reduces the hole charge collection time. Further, the N+ type semiconductor region 12 restricts diffusion of the excited charges into the N-type semiconductor region 2 in the N-type semiconductor region 13, reducing the probability that charges are trapped by traps in the N-type semiconductor region 2.
  • the N+ type semiconductor region 12 thins the effective charge collection region to the N-type semiconductor region 13, and the electrode N+ type semiconductor region 3 and the P+ type semiconductor region 4 have a lateral structure, the structure is equivalent to an increase of the N+ type.
  • the effective resistance between the semiconductor region 3 and the P+ type semiconductor region 4 further reduces the dark current of the pixel.
  • the N+ type semiconductor region 12 may be a monolithic continuous structure, or may be disposed only under the P+ type semiconductor region 4, and the specific size may be designed and adjusted as needed.
  • the substrate 1 of the semiconductor substrate may be an N+ type region or an N-type region (that is, a high resistance semiconductor wafer in which the regions 1 and 2 are the same type region).
  • an insulating material 12 such as silicon dioxide or silicon nitride is provided at a position 5 to 15 ⁇ m below the N + -type semiconductor region 3 and the P + -type semiconductor region 4 of the pixel, so that the entire semiconductor can be silicon-on-insulator (SOI). ) Wafer.
  • the insulating material 12 such as silicon dioxide or silicon nitride limits the charge in the N-type semiconductor region 13 Diffusion into the N-type semiconductor region 2 reduces the probability that charges are trapped by traps in the N-type semiconductor region 2.
  • the insulating material 12 such as silicon dioxide or silicon nitride thins the effective charge collection region to the N-type semiconductor region 13, and the electrode N+ type semiconductor region 3 and the P + type semiconductor region 4 have a lateral structure, the structure is equivalent.
  • the effective resistance between the N+ type semiconductor region 3 and the P+ type semiconductor region 4 is increased, thereby further reducing the dark current of the pixel.
  • the insulating material 12 such as silicon oxide or silicon nitride may be a monolithic continuous structure, or may be disposed only under the P+ type semiconductor region 4, and the specific size may be designed and adjusted as needed.
  • FIG. 11 is a schematic view for explaining a configuration of a photodiode according to a ninth embodiment.
  • a conductive structure with an insulating layer is disposed under the second conductive type heavily doped region and the first conductive type heavily doped region, or is only heavily doped in the second conductive type.
  • a conductive structure with an insulating layer is placed under the area.
  • the conductive structure with an insulating layer may be made of an insulating material such as silicon dioxide or silicon nitride, heavily doped with a semiconductor material such as single crystal silicon or polysilicon or germanium, and an insulating material such as silicon dioxide or silicon nitride.
  • the conduction structure potential of the insulating layer can be independently controlled.
  • the conductive structure with the insulating layer can thin the charge sensitive region and reduce the hole charge trapped by the trap of the light-doped region of the first conductive type below.
  • the first conductive type heavily doped region and the conductive layer structure having the same potential push the hole charge to drift toward the second conductive type heavily doped region, reducing the charge collection time.
  • the thinned first conductivity type lightly doped region increases the effective resistance between the two electrodes, further reducing dark current.
  • the first conductive type heavily doped region in the pixel may be a trench structure extending to a heavily doped single crystal silicon or a semiconductor material such as polysilicon or germanium in a conductive structure with an insulating layer, completely isolating the inter-pixel structure and reducing Charge crosstalk effect between pixels.
  • the substrate 1 of the semiconductor substrate may be an N+ type region.
  • a layer of the N+ type semiconductor region 12 is provided at a position of 5 to 15 ⁇ m below the N + -type semiconductor region 3 and the P + -type semiconductor region 4 of the pixel, and may be a semiconductor material such as single crystal silicon, polycrystalline silicon or germanium.
  • the N + -type semiconductor region 3 has a trench structure and extends to the N + -type semiconductor region 12 such that the N + -type semiconductor region 3 and the N + -type semiconductor region 12 in the pixel have the same potential distribution.
  • the electron holes excited by the photon in the N-type semiconductor region 13 are driven by the built-in electric field or the applied electric field, respectively, to the N+ type semiconductor region 3 and the P+ type semiconductor region 4, respectively. drift.
  • the N+ type semiconductor region 12, the N-type semiconductor region 13, and the P+ type semiconductor region 4 constitute an N+/N-/P+ structure, and the N+ type semiconductor region 12 pushes the hole carriers to the P+ type semiconductor region 4 direction on the upper side ( That is, the active region is diffused, thereby reducing the hole charge collection time.
  • the N+ type semiconductor region 3 of the trench structure and the insulating material 12 such as silicon dioxide or silicon nitride completely isolate the pixel and the pixel structure, further suppressing the charge string between the pixels. Disturbance effect. Further, the N+ type semiconductor region 12 restricts diffusion of the excited charges into the N-type semiconductor region 2 in the N-type semiconductor region 13, reducing the probability that charges are trapped by traps in the N-type semiconductor region 2. In addition, since the N+ type semiconductor region 12 thins the effective charge collection region to the N-type semiconductor region 13, and the electrode N+ type semiconductor region 3 and the P+ type semiconductor region 4 have a lateral structure, the structure is equivalent to an increase of the N+ type.
  • the N+ type semiconductor region 12 may be a monolithic continuous structure, or may be disposed only under the P+ type semiconductor region 4, and the specific size may be designed and adjusted as needed.
  • the substrate 1 of the semiconductor substrate may be an N+ type region or an N-type region (that is, a high resistance semiconductor wafer in which regions 1 and 2 are the same type region).
  • an insulating material 12 such as silicon dioxide or silicon nitride is provided at a position 5 to 15 ⁇ m below the N + -type semiconductor region 3 and the P + -type semiconductor region 4 of the pixel, so that the entire semiconductor can be silicon-on-insulator (SOI). ) Wafer.
  • the N+ type semiconductor region 3 is a trench structure extending to an insulating material 12 such as silicon dioxide or silicon nitride, the N+ type semiconductor region 3 of the trench structure, and the insulating material 12 such as silicon dioxide or silicon nitride to be pixels and pixels.
  • the structure is completely isolated, further suppressing the charge crosstalk effect between pixels.
  • the insulating material 12 such as silicon dioxide or silicon nitride limits the diffusion of the excited charges into the N-type semiconductor region 2 in the N-type semiconductor region 13, reducing the probability that charges are trapped by traps in the N-type semiconductor region 2.
  • the insulating material 12 such as silicon dioxide or silicon nitride thins the effective charge collection region to the N-type semiconductor region 13, and the electrode N+ type semiconductor region 3 and the P + type semiconductor region 4 have a lateral structure, the structure is equivalent.
  • the effective resistance between the N+ type semiconductor region 3 and the P+ type semiconductor region 4 is increased, thereby further reducing the dark current of the pixel.
  • the insulating material 12 such as silicon oxide or silicon nitride may be a monolithic continuous structure, or may be disposed only under the P+ type semiconductor region 4, and the specific size may be designed and adjusted as needed.
  • Fig. 12 shows a tenth embodiment.
  • the substrate 1 of the semiconductor substrate may be an N+ type region or an N-type region.
  • a conductive structure with an insulating layer is provided at a position of 5 to 15 ⁇ m below the N+ type semiconductor region 3 and the P+ type semiconductor region 4 of the pixel, respectively, which is a silicon dioxide or silicon nitride insulating layer 14, and a heavy A semiconductor material 15 such as single crystal silicon or polysilicon or germanium, or a silicon dioxide or silicon nitride insulating layer 16 is doped.
  • This is a two-layer silicon-on-insulator (DSOI) wafer structure.
  • DSOI silicon-on-insulator
  • the semiconductor material 15 such as heavily doped monocrystalline silicon or polycrystalline silicon or germanium can be independently controlled to modulate the electric field distribution in the N-type semiconductor region 13.
  • the electron holes excited by the photon in the N-type semiconductor region 13 are driven by the built-in electric field or the applied electric field, respectively, to the N+ type semiconductor region 3 and the P+ type semiconductor region 4, respectively. drift.
  • Heavy-doped single crystal silicon or polysilicon or germanium semiconductor material 15 will push the hole carriers to the P+ type semiconductor region 4 on the upper side (ie, Diffusion in the source region direction, thereby reducing the hole charge collection time.
  • the conductive structure with the insulating layer limits the diffusion of the excited charges into the N-type semiconductor region 2 in the N-type semiconductor region 13, reducing the probability that charges are trapped by the traps in the N-type semiconductor region 2.
  • the conductive structure with the insulating layer thins the effective charge collection region to the N-type semiconductor region 13, and the electrode N+ type semiconductor region 3 and the P + type semiconductor region 4 have a lateral structure, the structure is equivalent to an increase.
  • the effective resistance between the N+ type semiconductor region 3 and the P+ type semiconductor region 4 further reduces the dark current of the pixel.
  • the conductive structures 14, 15 and 16 with the insulating layer in this embodiment may be a unitary continuous structure or may be disposed only under the P+ type semiconductor region 4, and the specific dimensions may be designed and adjusted as needed.
  • Fig. 13 shows an eleventh embodiment.
  • the substrate 1 of the semiconductor substrate may be an N+ type region or an N-type region.
  • a conductive structure with an insulating layer is provided at a position of 5 to 15 ⁇ m below the N+ type semiconductor region 3 and the P+ type semiconductor region 4 of the pixel, respectively, which is a silicon dioxide or silicon nitride insulating layer 14, and a heavy A semiconductor material 15 such as single crystal silicon or polysilicon or germanium, or a silicon dioxide or silicon nitride insulating layer 16 is doped.
  • This is a two-layer silicon-on-insulator (DSOI) wafer structure.
  • DSOI silicon-on-insulator
  • the N+ type semiconductor region 3 is a trench structure extending to a semiconductor material 15 such as heavily doped single crystal silicon or polysilicon or germanium, the N+ type semiconductor region 3 of the trench structure and the conductive structure with an insulating layer will have a pixel and a pixel structure Complete isolation further suppresses charge crosstalk effects between pixels.
  • the semiconductor material 15 such as heavily doped single crystal silicon or polycrystalline silicon or germanium and the N + -type semiconductor region 3 have the same potential, and the electric field distribution in the N-type semiconductor region 13 can be modulated by the potential control of the N + -type semiconductor region 3.
  • the electron holes excited by the photon in the N-type semiconductor region 13 are driven by the built-in electric field or the applied electric field, respectively, to the N+ type semiconductor region 3 and the P+ type semiconductor region 4, respectively. drift.
  • the semiconductor material 15 such as heavily doped single crystal silicon or polycrystalline silicon or germanium promotes the diffusion of hole carriers toward the P+ type semiconductor region 4 in the upper direction (ie, the direction of the active region), thereby reducing the hole charge collection time.
  • the conductive structure with the insulating layer limits the diffusion of the excited charges into the N-type semiconductor region 2 in the N-type semiconductor region 13, reducing the probability that charges are trapped by the traps in the N-type semiconductor region 2.
  • the conductive structure with the insulating layer thins the effective charge collection region to the N-type semiconductor region 13, and the electrode N+ type semiconductor region 3 and the P + type semiconductor region 4 have a lateral structure, the structure is equivalent to an increase.
  • the effective resistance between the N+ type semiconductor region 3 and the P+ type semiconductor region 4 further reduces the dark current of the pixel.
  • the conductive structures 14, 15 and 16 with the insulating layer in this embodiment may be a unitary continuous structure or may be disposed only under the P+ type semiconductor region 4, and the specific dimensions may be designed and adjusted as needed.
  • the photodiode array of the above embodiment of the present invention is mainly applied to a wavelength of 200 to 600 nm and an X-ray detector (a light of about 550 nm is emitted by a scintillator such as CsI), and is mainly used in a silicon epitaxial wafer.
  • the surface is absorbed within a depth of 5 microns, so the depth of the trench isolation structure, the first conductive heavily doped layer, the insulating material layer, and the conductive structure with the insulating layer can be controlled to be between 5 and 20 ⁇ m. In this case, as described above, the effect of the groove structure can be ensured.
  • the photodiode array according to the embodiment of the invention operates in the wavelength range of 200 to 600 nm, and the light absorption in the active region of the pixel has good consistency, reduces the dark current of the pixel, and accelerates the pixel charge collection rate.

Landscapes

  • Light Receiving Elements (AREA)

Abstract

一种同面电极光电二极管阵列及其制作方法，在低电阻率衬底，高电阻率外延类型的外延硅片的顶侧，形成第一导电类型重掺杂区域和第二导电类型掺杂区域，分别为光电二极管的阴极和阳极。结构还包括在阳极和阴极之间形成的沟槽结构，沟槽结构可由空隙、绝缘材料、传导结构、反射材料和离子注入构成；也可以包括在阳极和阴极下方形成第一导电类型重掺杂区域、绝缘隔离层或带绝缘层的传导结构。

Description

同面电极光电二极管阵列及其制作方法 技术领域
本发明的实施例涉及光电二极管，具体涉及一种同面电极光电二极管阵列结构及其制作方法。
背景技术
半导体光电二极管阵列通过直接入射光线或者X射线在闪烁体中产生可见光线，与半导体中原子发生电离反应，从而产生非平衡载流子来检测入射光的。衡量光电二极管阵列性能的关键参数包括分辨率、信噪比、读出速度以及像素间电荷串扰等。此外，暗电流和单像素内部光线收集有源区的电荷收集均匀性也尤为重要。
发明内容
鉴于现有技术中的一个或多个问题，提出了同面电极光电二极管阵列及其制作方法。
在本发明的一个方面，提出了一种同面电极光电二极管阵列，包括多个同面电极光电二极管，每个同面电极光电二极管包括：第一导电型重掺杂半导体衬底；在第一导电型重掺杂半导体衬底上形成的第一导电型轻掺杂半导体层；在所述第一导电型轻掺杂半导体层的上部形成的第二导电型重掺杂半导体区域，其中所述第二导电型重掺杂半导体区域与所述第一导电型轻掺杂半导体层形成PN结二极管，并且第二电极从所述第二导电型重掺杂半导体层在光线入射侧引出；围绕所述第二导电型重掺杂半导体区域的第一导电型重掺杂半导体区域，并且第一电极从所述第一导电型重掺杂半导体区域在光线入射侧引出；以及设置在所述第二导电型重掺杂半导体区域和所述第一导电型重掺杂半导体区域之间的沟槽结构。
根据一些实施例，所述沟槽结构是由一种绝缘材料或多种复合绝缘材料，或光线反射材料填充沟槽而形成的。
根据一些实施例，所述沟槽结构是由与第一导电类型的重掺杂单晶半导体或多晶半导体材料填充沟槽而形成的。
根据一些实施例，所述沟槽结构包括且在所述沟槽周围形成第一导电型的重掺杂区域。
根据一些实施例，所述沟槽结构包括未填充的沟槽，且在沟槽底部及侧壁覆盖一层绝缘层、多层复合绝缘层或光线反射材料。
根据一些实施例，在沟槽周围形成第一导电型的重掺杂区域，在沟槽底部及侧壁覆盖一层绝缘层、多层复合绝缘层或光线反射材料。
根据一些实施例，所述沟槽结构包括沟槽，且在沟槽底部及侧壁覆盖一种绝缘材料，或多种复合绝缘材料，或光线反射材料，然后由单晶半导体材料或多晶半导体材料填充沟槽。
根据一些实施例，填充沟槽的单晶半导体材料或多晶半导体材料，相对于第二电极连接到高电位。
根据一些实施例，在第二导电型重掺杂半导体区域的上部形成较薄的第一导电型重掺杂区域或第二导电型轻掺杂区域，且四周被所述第二导电型重掺杂区域包围。
根据一些实施例，在所述第二导电型重掺杂区域下部形成连续第一导电类型重掺杂区域，或仅在第二导电类型重掺杂区域下方设置一段第一导电类型重掺杂区域。
根据一些实施例，在所述第二导电型重掺杂区域下面，形成连续的绝缘材料区域，或仅在所述第二导电型重掺杂区域下方设置一段绝缘材料区域。
根据一些实施例，所述第一导电型重掺杂区域形成为沟槽结构，向下延伸至所述第一导电型重掺杂区域或绝缘材料区域，并与之连接。
根据一些实施例，在所述第二导电型重掺杂区域下面，形成连续带绝缘层的传导结构，或仅在所述第二导电型重掺杂区域下方设置一段带绝缘层的传导结构，该传导结构由绝缘材料或半导体材料构成。
根据一些实施例，所述第一导电型重掺杂区域为沟槽结构，向下延伸至带绝缘层的传导结构中的半导体材料区域，并与之连接。
在本发明的另一方面，提出了一种制作同面电极光电二极管的方法，包括步骤：在第一导电型重掺杂半导体衬底上形成第一导电型轻掺杂半导体层；在所述第一导电型轻掺杂半导体层的上部形成第二导电型重掺杂半导体区域，其中所述第二导电型重掺杂半导体区域与所述第一导电型轻掺杂半导体层形成PN结二极管，并且第二电极从所述第二导电型重掺杂半导体层在光线入射侧引出；围绕所述第二导电型重掺杂半导体区域形成第一导电型重掺杂半导体区域，并且第一电极从所述第一导电型重掺杂半导体区域在光线入射侧引出；以及在所述第二导电 型重掺杂半导体区域和所述第一导电型重掺杂半导体区域之间设置沟槽结构。
利用上述实施例的方案，能够在探测X射线时有效阻挡空穴载流子向非有源区扩散，提高有源区边缘位置的光响应及收集效率。
附图说明
根据以下结合附图的详细描述，本发明的以上及其其他目标、特征和优点将更明显，附图中：
图1A是描述本发明实施例的光电二极管的俯视图；
图1B是用以对所涉及的光电二极管的剖面A-A’结构进行说明的示意图；
图2是用以对第1、2实施方式所涉及的光电二极管的结构进行说明的示意图；
图3是用以对第3实施方式所涉及的光电二极管的结构进行说明的示意图；
图4是用以对第4实施方式所涉及的光电二极管的结构进行说明的示意图；
图5是用以对第5实施方式所涉及的光电二极管的结构进行说明的示意图；
图6是用以对第6实施方式所涉及的光电二极管的结构进行说明的示意图；
图7是用以对所涉及的光电二极管光线收集有源区边缘部分光响应进行说明的示意图；
图8是用以对所涉及的光电二极管光线收集有源区边缘部分收集效率进行说明的示意图。
图9是用以对第7实施方式所涉及的光电二极管的结构进行说明的示意图；
图10是用以对第8实施方式所涉及的光电二极管的结构进行说明的示意图；
图11是用以对第9实施方式所涉及的光电二极管的结构进行说明的示意图；
图12是用以对第10实施方式所涉及的光电二极管的结构进行说明的示意图；
图13是用以对第11实施方式所涉及的光电二极管的结构进行说明的示意图；
符号的说明
1.N+型半导体层，2.N-型半导体层，3.N+型半导体区域，4.P+型半导体区域，5.一层绝缘层、多层复合绝缘层或光线反射材料，6.空间电荷区，7.一层绝缘层、多层复合绝缘层或光线反射材料，或P+型半导体材料，8.空隙区域，10.N+或P+掺杂的单晶半导体材料或多晶半导体材料，11.较薄N+型半导体区域或P-型半导体区域，12.N+型半导体区域或二氧化硅、氮化硅等绝缘材料区域，13.N-型半导体层，14，二氧化硅、氮化硅等绝缘材料，15.单晶硅、多晶硅或 锗等重掺杂半导体材料，16，二氧化硅、氮化硅等绝缘材料，21.N+型半导体区域引出电极，22.P+型半导体区域引出电极，31.N+型半导体区域，32.N+型半导体区域，34.一层绝缘层、多层复合绝缘层或光线反射材料。
具体实施方式
下面，将参考附图描述本发明的示范性实施例。如果对公知的功能或结构的描述使得本发明的主题不简洁，则将其省略。而且，为了清楚地说明的目的，附图中实处的部分被简化或放大。此处，特点层或区域的位置可以表示相对位置，但实际情况不一定与示意图中比例相同。参照图1～图13对实施方式所涉及的光电二极管结构特点进行说明。
本发明实施例的光电二极管阵列中，像素对应的光检测通道形成于第一导电类型的外延硅片中。该外延硅片为低电阻率衬底，高电阻率外延类型的外延硅片。包括：第一导电类型的离子注入，在硅外延片表面形成重掺杂区域，具有使通过被检测光的入射而产生的多数载流子进行收集区域；第二导电类型的离子注入，在硅外延片表面形成重掺杂区域，与第一导电类型的外延片形成PN结，并且按照光检测通道的方式设置其对应的注入位置，具有使通过被检测光的入射而产生的少数载流子进行收集区域，该区域为光线收集有源区。该两种导电类型重掺杂区域不能够相邻放置，以防止发生遂穿效应，而其间则为半导体基板的高阻外延材料。该光电二极管阵列的PN结可以工作在反偏模式，在像素中的光线收集有源区附近形成反偏条件下较宽的空间电荷区；光电二极管阵列的PN结也可以工作在零偏模式，在像素中的光线收集有源区附近形成零偏条件下较窄的内建空间电荷区。
光线通过入射窗口进入到硅半导体中，在光线收集有源区中同硅原子发生碰撞电离，从而产生电子空穴对，电子会在内建电场或外加偏置电场条件下，向第一导电类型重掺杂区域漂移或扩散，最终被收集；而空穴会在内建电场或外加偏置电场条件下，向第二导电类型重掺杂区域漂移或扩散，最终被收集，从而读出电信号。考虑到PN结电容效应，第一导电类型和第二导电类型掺杂区域间距可能较大，像素有源区边缘位置激发的载流子很容易被光电二极管阵列中的临近像素收集；此外也可能被硅体中陷阱或缺陷所捕获。
例如，同面电极光电二极管阵列包括多个同面电极光电二极管，每个同面电极光电二极管包括：第一导电型重掺杂半导体衬底；在第一导电型重掺杂半导体 衬底上形成的第一导电型轻掺杂半导体层；在第一导电型轻掺杂半导体层的上部形成的第二导电型重掺杂半导体区域，其中所述第二导电型重掺杂半导体区域与所述第一导电型轻掺杂半导体层形成PN结二极管，并且第二电极从所述第二导电型重掺杂半导体层在光线入射侧引出；围绕所述第二导电型重掺杂半导体区域的第一导电型重掺杂半导体区域，并且第一电极从所述第一导电型重掺杂半导体区域在光线入射侧引出；以及设置在所述第二导电型重掺杂半导体区域和所述第一导电型重掺杂半导体区域之间的沟槽结构。
图1A和1B给出了所涉及的光电二极管阵列的单个元胞结构，其中图1A示出了俯视图，图1B示出了沿着图1A的剖面线A-A’得到的剖面图。该光电二极管结构制作在N型外延片上，该N型外延片包含N+型半导体衬底区域1及N-型外延半导体衬底区域2。这里N+型半导体衬底区域厚度范围是300～575μm左右，电阻率为0.002～0.005Ω.cm，N-型外延半导体区域厚度范围是20～100μm左右，电阻率为1kΩ.cm左右。本公开方案中，所谓“高杂质浓度(重掺杂)”，例如是指杂质浓度为1×1017cm-3左右以上，且对导电类型附加“+”表示。所谓“低杂质浓度(轻掺杂)”，例如是指杂质浓度为1×1017cm-3左右以下，且对导电类型附加“-”表示。作为N型杂质，存在磷(P)或砷(As)等，作为P型杂质，存在硼(B)等。
在N-型外延半导体区域2上侧形成N+型半导体区域3，和P+型半导体区域4。这样P+型半导体区域4和N-型外延半导体区域2形成了PN结。N+型半导体区域3厚度范围是0.5～3μm左右，P+型半导体区域4厚度范围是0.2～1μm左右，N+型半导体区域3与P+型半导体区域4间距约10～100μm左右。在N+型半导体区域3和P+型半导体区域4之间通过刻蚀与填充，形成沟槽7，沟槽深度在4～20μm左右。在光电二极管表面淀积一层绝缘层、多层复合绝缘层或光线反射材料5，厚度范围在50～200nm左右，用以隔离外界杂质进入硅半导体基板，此外，可作为金属电极绝缘物。此外，根据光学及绝缘物特性，还可设计为抗光线反射增透膜。N+型半导体区域3通过金属电极21引出，P+型半导体区域4过金属电极22引出。在光电二极管处于零偏置或反向偏置条件下，光电二极管内部像素的PN结位置会形成空间电荷区6，由于P+型半导体区域的杂质浓度远大于N-型外延半导体区域2，因此空间电荷区主要向N-型外延半导体区域2中扩展，且扩展宽度随反偏电压的增大而增大。
图2给出了第1实施方式所涉及的光电二极管的结构图。光电二极管阵列的 光线收集有源区仅为P+型半导体区域4的正下方所形成的空间电荷区6，而，N+型半导体区域3与P+型半导体区域4间距区域则为电荷收集的过度区域，并非电荷收集的有源区。而N+型半导体区域3上的金属电极21引出则阻挡光线的入射，因此也不是电荷收集的有源区。当光线入射到P+型半导体区域4中，即光线收集有源区中，会在N-型外延半导体区域2及P+型半导体区域4中激发大量电子空穴对，由于光线波长范围在200～600nm，所以在N-型外延半导体区域2中的吸收深度较浅。电子载流子在内建电场或外加电场的作用下，向N+型半导体区域3方向漂移，最终被金属电极21收集。空穴载流子在内建电场和外加电场的作用下，向P+型半导体区域4方向漂移，最终被金属电极22收集，并作为信号输出。但由于N-型外延半导体区域2中存在陷阱，因此空穴载流子寿命较小，部分空穴载流子会被陷阱所捕获。有源区中心附近产生的空穴载流子更容易被P+型半导体区域4所收集，而在有源区边缘附近和非有源区中产生的空穴载流子，还可能被临近像素收集或临近像素中的陷阱所捕获。
在第1实施例的光电二极管阵列中，在该两种导电类型重掺杂区域之间的高阻半导体外延材料上，形成沟槽结构，且以氧化硅、氮化硅等，一种绝缘材料，或多种复合绝缘材料，或光线反射材料填充。当光线入射到有源区边缘位置时，激发的部分空穴载流子会向非有源区扩散和移动，离被收集的有源区距离增大，增加了被硅体陷阱捕获的概率。通过物理隔离，可以有效阻挡空穴载流子向非有源区扩散，提高有源区边缘位置的光响应及收集效率，进而平衡像素有源区不同位置的电荷收集一致性。
例如，在N+型半导体区域3和P+型半导体区域4之间通过刻蚀与填充，形成沟槽7，且以氧化硅、氮化硅等，一种绝缘材料，或多种复合绝缘材料，或光线反射材料填充。当光线入射到有源区边缘或非有源区位置时，激发产生的部分空穴载流子会向非有源区扩散和移动，离P+型半导体区域4的距离增大。增加了被硅体陷阱捕获的概率。通过在N+型半导体区域3和P+型半导体区域4之间形成沟槽结构，构成了对空穴载流子范围控制，有效阻止部分空穴载流子信号的丢失，增大空穴载流子被有源区收集的概率，提高有源区边缘位置的光响应及收集效率，进而平衡像素有源区不同位置的电荷收集一致性。
在第2实施例的光电二极管阵列中，在该两种导电类型重掺杂区域之间的高阻半导体外延材料上，形成沟槽结构，可以由第一导电类型重掺杂单晶半导体或多晶半导体填充。通过物理隔离，可以有效阻挡空穴载流子向非有源区扩散，此 外，第一导电类型重掺杂区域有利于推动到达此处的空穴载流子向相反方向(即有源区方向)扩散，从而提高有源区边缘位置的光响应及收集效率。
如图2所示，在N+型半导体区域3和P+型半导体区域4之间通过刻蚀与填充，形成沟槽7，可以由N+型单晶半导体或多晶半导体填充沟槽7。这里，填充到沟槽中的P+型单晶半导体或多晶半导体没有电极引出，在结构中相当于悬浮状态，当空穴载流子扩散或漂移到P+型半导体结构边缘时，会在物理结构隔离及能带的驱动下，推动到达此处的空穴载流子向相反方向(即有源区方向)扩散，从而提高有源区边缘位置的光响应及收集效率。
图3是用以对第3实施方式所涉及的光电二极管的结构进行说明的示意图。在第3实施例的光电二极管阵列中，在该两种导电类型重掺杂区域之间的高阻半导体外延材料上，形成沟槽结构，可以由氧化硅、氮化硅等，一种绝缘材料，或多种复合绝缘材料，或光线反射材料填充，且在沟槽周围形成与外延片掺杂类型相同的重掺杂区域。通过物理隔离，可以有效阻挡空穴载流子向非有源区扩散，此外，第一导电类型重掺杂区域有利于推动到达此处的空穴载流子向相反方向(即有源区方向)扩散，从而提高有源区边缘位置的光响应及收集效率。
如图3所示，在N+型半导体区域3和P+型半导体区域4之间通过刻蚀与填充，形成沟槽7，然后进行N+离子注入，在沟槽底部及侧壁形成一层N+型半导体区域31。该N+型半导体区域31厚度在0.1～1μm左右。然后以氧化硅、氮化硅等，一种绝缘材料，或多种复合绝缘材料，或光线反射材料填充。当空穴载流子扩散或漂移到N+型半导体结构31边缘时，会在沟槽物理结构隔离及能带的驱动下，推动到达此处的空穴载流子向相反方向(即有源区方向)扩散，进而提高有源区边缘位置的光响应及收集效率。
图4是用以对第4实施方式所涉及的光电二极管的结构进行说明的示意图。在第4实施例的光电二极管阵列，在该两种导电类型重掺杂区域之间的高阻半导体外延材料上，形成沟槽结构，可以由空隙结构构成，且在空隙底部及侧壁覆盖一层绝缘层、多层复合绝缘层或光线反射材料。通过物理隔离，可以有效阻挡空穴载流子向非有源区扩散，从而提高有源区边缘位置的光响应及收集效率。
如图4所示，在N+型半导体区域3和P+型半导体区域4之间通过刻蚀与填充，形成沟槽，然后在沟槽底部及侧壁生长氧化硅、氮化硅等，一种绝缘材料，或多种复合绝缘材料，或光线反射材料5。而沟槽则为空隙结构8。氧化硅、氮化硅等一种绝缘材料、多种复合绝缘材料或光线反射材料5厚度范围在0.1～1μm 左右。沟槽空隙结构可以很好地限制空穴载流子在半导体基板外延层2中的活动范围，有效阻止部分空穴载流子信号的丢失，增大空穴载流子被有源区收集的概率，提高有源区边缘位置的光响应及收集效率，进而平衡像素有源区不同位置的电荷收集一致性。
图5是用以对第5实施方式所涉及的光电二极管的结构进行说明的示意图。在第5实施例的光电二极管阵列中，在该两种导电类型重掺杂区域之间的高阻半导体外延材料上，形成沟槽结构，可以由空隙结构构成，在空隙底部及侧壁覆盖一层绝缘层，或多层复合绝缘层，或光线反射材料，且在沟槽周围形成与外延片掺杂类型相同的重掺杂区域。通过物理隔离，可以有效阻挡空穴载流子向非有源区扩散，此外，第二导电类型重掺杂区域提高了沟槽区域的空穴能带，有利于推动到达此处的空穴载流子向相反方向(即有源区方向)扩散。
如图5所示，在N+型半导体区域3和P+型半导体区域4之间通过刻蚀与填充，形成沟槽，然后进行N+离子注入，在沟槽底部及侧壁形成一层N+型半导体区域32。该N+型半导体区域32厚度在0.1～1μm左右。然后在沟槽底部及侧壁生长氧化硅、氮化硅等一种绝缘材料、多种复合绝缘材料或光线反射材料32。而沟槽则为空隙结构8。当空穴载流子扩散或漂移到N+型半导体结构32边缘时，会在沟槽空隙物理结构隔离及能带的驱动下，推动到达此处的空穴载流子向相反方向(即有源区方向)扩散，进而提高有源区边缘位置的光响应及收集效率。
图6是用以对第6实施方式所涉及的光电二极管的结构进行说明的示意图。在第6实施例的光电二极管阵列中，在该两种导电类型重掺杂区域之间的高阻半导体外延材料上，形成沟槽结构，可以在沟槽底部及侧壁覆盖一层绝缘层，或多层复合绝缘层，或光线反射材料，然后由单晶半导体材料或多晶半导体材料填充沟槽。通过物理隔离，可以有效阻挡空穴载流子向非有源区扩散，此外，该单晶半导体材料或多晶半导体材料，相对于第二导电电极(光线收集对应的重掺杂区域引出电极)可以连接到零点位，悬浮态，或高电位，通过引入外加电场，有利于推动到达此处的空穴载流子向相反方向(即有源区方向)扩散，从而提高有源区边缘位置的光响应及收集效率。
如图6所示，在N+型半导体区域3和P+型半导体区域4之间通过刻蚀与填充，形成沟槽，然后在沟槽底部及侧壁生长氧化硅、氮化硅等，一种绝缘材料，或多种复合绝缘材料，或光线反射材料34。可以由N+或P+型单晶半导体或多晶半导体10填充沟槽空隙，且该N+或P+型单晶或多晶半导体10将有外加电位 控制，可以为零偏，悬浮态，或者正向偏置。当该N+或P+型单晶或多晶半导体10为正向偏置时，会在半导体内部由N+或P+型单晶或多晶半导体10到P+型半导体区域4方向，产生电场，从而当空穴载流子扩散或漂移到氧化硅、氮化硅等，一种绝缘材料，或多种复合绝缘材料，或光线反射材料34边缘时，会在沟槽空隙物理结构隔离及电场的驱动下，推动到达此处的空穴载流子向相反方向(即有源区方向)扩散，进而提高有源区边缘位置的光响应及收集效率。
图7和图8给出了有沟槽(第1实施方式)和无沟槽结构的光电二极管器件中，光线在像素有源区边缘不同入射位置时对应的光响应及光电收集效率。由对比结果可见，沟槽隔离结构可以改善像素有源区边缘位置空穴载流子的收集概率，提高有源区边缘位置的光响应及收集效率，进而平衡像素不同位置的电荷收集一致性。
图9是用以对第7实施方式所涉及的光电二极管的结构进行说明的示意图。在第7实施例的光电二极管阵列中，在光线收集有源区顶层生成较薄的第一导电类型重掺杂区域，或者为第二导电类型轻掺杂区域。由于在工艺加工过程中，器件表面容易引入缺陷或者离子等杂质，而这些缺陷会形成捕获中心，降低电极对电荷的收集量。在第二导电类型重掺杂区域的顶层生成较薄的第一导电类型重掺杂区域，可以控制像素零偏或反偏时，内部空间电荷区边界的上限不会达到半导体表面，降低空穴电荷被结构缺陷捕获的概率。在第二导电类型重掺杂区域的顶层生成较薄的第二导电类型轻掺杂区域，可以抑制空穴扩漂移到器件表面，从而降低空穴电荷被结构缺陷捕获的概率。
如图9所示，在P+型半导体区域4的顶层，通过离子注入形成较薄的N+型半导体区域11，该区域被P+型半导体区域4所包围。这样N+型半导体区域11、P+型半导体区域4和N-型半导体基板外延层2，构成了N+/P+/N-结构，且无论像素结构在零偏或反偏时，P+半导体区域4内侧形成的空间电荷区上边界，被限制在像素器件表面以下，降低空穴电荷被器件表面缺陷捕获的概率。此外，可以通过控制离子注入能量的方式，在P+型半导体区域4的顶层，形成较薄P-型半导体区域11，该区域被P+型半导体区域4所包围。这样无论像素结构在零偏或反偏时，这样P-型半导体区域11、P+型半导体区域4和N-型半导体基板外延层2，构成了P-/P+/N-结构，内建电场可以抑制空穴扩漂移到器件表面，从而降低空穴电荷被结构缺陷捕获的概率。
图10是用以对第8实施方式所涉及的光电二极管的结构进行说明的示意图。 在第10实施例的光电二极管阵列中，在第二导电类型重掺杂区域和第一导电类型重掺杂区域下方设置一层第一导电类型重掺杂区域，或仅在第二导电类型重掺杂区域下方设置一段第一导电类型重掺杂区域。该第一导电类型重掺杂区域可以为单晶硅、多晶硅或者锗等半导体。该结构可以减薄电荷敏感区，降低空穴电荷被下方的第一导电类型轻掺杂区域的陷阱捕获。电位相当的第一导电类型重掺杂区域会推动空穴电荷向第二导电类型重掺杂区域漂移，降低电荷收集时间。此外，减薄的第一导电类型轻掺杂区域增大了两电极间的有效电阻，进一步降低暗电流。另外，像素中的第一导电类型重掺杂区域可以为沟槽结构，延伸到该层第一导电类型重掺杂区域，完全隔离像素间结构，进一步降低像素间电荷串扰效应。这里，该层第一导电类型重掺杂区域可以更替为二氧化硅或氮化硅等绝缘材料。
如图10所示，半导体基板的衬底1可以为N+型区域，也可以为N-型区域。该实施方式在像素的N+型半导体区域3和P+型半导体区域4的下方5～20μm的位置，设置一层N+型半导体区域12，可以为单晶硅、多晶硅或者锗等半导体材料。这样像素中的N+型半导体区域3和N+型半导体区域12电势相当。当像素处于零偏或者反偏时，光子在N-型半导体区域13内激发的电子空穴对在内建电场或外加电场的驱动作用下，分别向N+型半导体区域3和P+型半导体区域4漂移。N+型半导体区域12、N-型半导体区域13和P+型半导体区域4构成N+/N-/P+结构，N+型半导体区域12会推动空穴载流子向上侧的P+型半导体区域4方向(即有源区方向)扩散，进而降低空穴电荷收集时间。此外，N+型半导体区域12限制了N-型半导体区域13内激发电荷向N-型半导体区域2中扩散，降低了电荷被N-型半导体区域2中陷阱捕获的概率。另外，由于N+型半导体区域12将有效电荷收集区域减薄到N-型半导体区域13，而电极N+型半导体区域3和P+型半导体区域4为横向结构，因此该结构相当于增大了N+型半导体区域3和P+型半导体区域4间有效电阻，从而进一步降低像素的暗电流。该实施方案中N+型半导体区域12可以为整体连续结构，也可以只在P+型半导体区域4下方设置，具体尺寸可根据需要设计调整。
在第8实施方式中，半导体基板的衬底1可以为N+型区域，也可以为N-型区域(即1和2区域为同一类型区域的高阻半导体晶圆片)。该实施方式在像素的N+型半导体区域3和P+型半导体区域4的下方5～15μm的位置，设置一层二氧化硅或氮化硅等绝缘材料12，这样整个半导体可以为绝缘体上硅(SOI)晶圆片。二氧化硅或氮化硅等绝缘材料12限制了N-型半导体区域13内激发电荷 向N-型半导体区域2中扩散，降低了电荷被N-型半导体区域2中陷阱捕获的概率。另外，由于二氧化硅或氮化硅等绝缘材料12将有效电荷收集区域减薄到N-型半导体区域13，而电极N+型半导体区域3和P+型半导体区域4为横向结构，因此该结构相当于增大了N+型半导体区域3和P+型半导体区域4间有效电阻，从而进一步降低像素的暗电流。该实施方案中氧化硅或氮化硅等绝缘材料12可以为整体连续结构，也可以只在P+型半导体区域4下方设置，具体尺寸可根据需要设计调整。
图11是用以对第9实施方式所涉及的光电二极管的结构进行说明的示意图。在第10实施例的光电二极管阵列中，在第二导电类型重掺杂区域和第一导电类型重掺杂区域下方设置一层带绝缘层的传导结构，或仅在第二导电类型重掺杂区域下方设置一段带绝缘层的传导结构。该带绝缘层的传导结构可以由二氧化硅或氮化硅等绝缘材料，重掺杂单晶硅或多晶硅或者锗等半导体材料，和二氧化硅或氮化硅等绝缘材料构成。该带绝缘层的传导结构电位可以独立控制。该带绝缘层的传导结构可以减薄电荷敏感区，降低空穴电荷被下方的第一导电类型轻掺杂区域的陷阱捕获。电位相同的第一导电类型重掺杂区和传导层结构会推动空穴电荷向第二导电类型重掺杂区域漂移，降低电荷收集时间。此外，减薄的第一导电类型轻掺杂区域增大了两电极间的有效电阻，进一步降低暗电流。另外，像素中的第一导电类型重掺杂区域可以为沟槽结构，延伸到带绝缘层的传导结构中的重掺杂单晶硅或多晶硅或者锗等半导体材料，完全隔离像素间结构，降低像素间电荷串扰效应。
如图11所示，半导体基板的衬底1可以为N+型区域。该实施方式在像素的N+型半导体区域3和P+型半导体区域4的下方5～15μm的位置，设置一层N+型半导体区域12，可以为单晶硅、多晶硅或者锗等半导体材料。且N+型半导体区域3为沟槽结构，延伸到N+型半导体区域12，这样像素中的N+型半导体区域3和N+型半导体区域12电势分布相同。当像素处于零偏或者反偏时，光子在N-型半导体区域13内激发的电子空穴对在内建电场或外加电场的驱动作用下，分别向N+型半导体区域3和P+型半导体区域4漂移。此外N+型半导体区域12、N-型半导体区域13和P+型半导体区域4构成N+/N-/P+结构，N+型半导体区域12会推动空穴载流子向上侧的P+型半导体区域4方向(即有源区方向)扩散，进而降低空穴电荷收集时间。并且沟槽结构的N+型半导体区域3和二氧化硅或氮化硅等绝缘材料12将像素和像素结构完全隔离，进一步抑制像素间的电荷串 扰效应。此外，N+型半导体区域12限制了N-型半导体区域13内激发电荷向N-型半导体区域2中扩散，降低了电荷被N-型半导体区域2中陷阱捕获的概率。另外，由于N+型半导体区域12将有效电荷收集区域减薄到N-型半导体区域13，而电极N+型半导体区域3和P+型半导体区域4为横向结构，因此该结构相当于增大了N+型半导体区域3和P+型半导体区域4间有效电阻，从而降低像素的暗电流。该实施方案中N+型半导体区域12可以为整体连续结构，也可以只在P+型半导体区域4下方设置，具体尺寸可根据需要设计调整。
在第9实施方式中，半导体基板的衬底1可以为N+型区域，也可以为N-型区域(即1和2区域为同一类型区域的高阻半导体晶圆片)。该实施方式在像素的N+型半导体区域3和P+型半导体区域4的下方5～15μm的位置，设置一层二氧化硅或氮化硅等绝缘材料12，这样整个半导体可以为绝缘体上硅(SOI)晶圆片。且N+型半导体区域3为沟槽结构，延伸到二氧化硅或氮化硅等绝缘材料12，沟槽结构的N+型半导体区域3和二氧化硅或氮化硅等绝缘材料12将像素和像素结构完全隔离，进一步抑制像素间的电荷串扰效应。二氧化硅或氮化硅等绝缘材料12限制了N-型半导体区域13内激发电荷向N-型半导体区域2中扩散，降低了电荷被N-型半导体区域2中陷阱捕获的概率。另外，由于二氧化硅或氮化硅等绝缘材料12将有效电荷收集区域减薄到N-型半导体区域13，而电极N+型半导体区域3和P+型半导体区域4为横向结构，因此该结构相当于增大了N+型半导体区域3和P+型半导体区域4间有效电阻，从而进一步降低像素的暗电流。该实施方案中氧化硅或氮化硅等绝缘材料12可以为整体连续结构，也可以只在P+型半导体区域4下方设置，具体尺寸可根据需要设计调整。
图12给出了第10实施方式。第10实施方式中，半导体基板的衬底1可以为N+型区域，也可以为N-型区域。该实施方式在像素的N+型半导体区域3和P+型半导体区域4的下方5～15μm的位置，设置一层带有绝缘层的传导结构，分别为二氧化硅或氮化硅绝缘层14、重掺杂单晶硅或多晶硅或者锗等半导体材料15、二氧化硅或氮化硅绝缘层16。这样整体为双层绝缘体上硅(DSOI)晶圆片结构。这样重掺杂单晶硅或多晶硅或者锗等半导体材料15可以独立电位控制，调制N-型半导体区域13内的电场分布。当像素处于零偏或者反偏时，光子在N-型半导体区域13内激发的电子空穴对在内建电场或外加电场的驱动作用下，分别向N+型半导体区域3和P+型半导体区域4漂移。重掺杂单晶硅或多晶硅或者锗等半导体材料15会推动空穴载流子向上侧的P+型半导体区域4方向(即有 源区方向)扩散，进而降低空穴电荷收集时间。此外，带有绝缘层的传导结构限制了N-型半导体区域13内激发电荷向N-型半导体区域2中扩散，降低了电荷被N-型半导体区域2中陷阱捕获的概率。另外，由于带有绝缘层的传导结构将有效电荷收集区域减薄到N-型半导体区域13，而电极N+型半导体区域3和P+型半导体区域4为横向结构，因此该结构相当于增大了N+型半导体区域3和P+型半导体区域4间有效电阻，从而进一步降低像素的暗电流。该实施方案中带有绝缘层的传导结构14、15和16可以为整体连续结构，也可以只在P+型半导体区域4下方设置，具体尺寸可根据需要设计调整。
图13给出了第11实施方式。第11实施方式中，半导体基板的衬底1可以为N+型区域，也可以为N-型区域。该实施方式在像素的N+型半导体区域3和P+型半导体区域4的下方5～15μm的位置，设置一层带有绝缘层的传导结构，分别为二氧化硅或氮化硅绝缘层14、重掺杂单晶硅或多晶硅或者锗等半导体材料15、二氧化硅或氮化硅绝缘层16。这样整体为双层绝缘体上硅(DSOI)晶圆片结构。且N+型半导体区域3为沟槽结构，延伸到重掺杂单晶硅或多晶硅或者锗等半导体材料15，沟槽结构的N+型半导体区域3和带有绝缘层的传导结构将像素和像素结构完全隔离，进一步抑制像素间的电荷串扰效应。这样重掺杂单晶硅或多晶硅或者锗等半导体材料15和N+型半导体区域3电位相同，可以通过电位控制N+型半导体区域3，调制N-型半导体区域13内的电场分布。当像素处于零偏或者反偏时，光子在N-型半导体区域13内激发的电子空穴对在内建电场或外加电场的驱动作用下，分别向N+型半导体区域3和P+型半导体区域4漂移。重掺杂单晶硅或多晶硅或者锗等半导体材料15会推动空穴载流子向上侧的P+型半导体区域4方向(即有源区方向)扩散，进而降低空穴电荷收集时间。此外，带有绝缘层的传导结构限制了N-型半导体区域13内激发电荷向N-型半导体区域2中扩散，降低了电荷被N-型半导体区域2中陷阱捕获的概率。另外，由于带有绝缘层的传导结构将有效电荷收集区域减薄到N-型半导体区域13，而电极N+型半导体区域3和P+型半导体区域4为横向结构，因此该结构相当于增大了N+型半导体区域3和P+型半导体区域4间有效电阻，从而进一步降低像素的暗电流。该实施方案中带有绝缘层的传导结构14、15和16可以为整体连续结构，也可以只在P+型半导体区域4下方设置，具体尺寸可根据需要设计调整。
本发明上述实施例的光电二极管阵列，主要应用在200～600nm波长、X射线探测器中(通过CsI等闪烁体而放射550nm左右波长光)，且主要在硅外延片 表面5微米深度以内吸收，因此沟槽隔离结构，第一导电重掺杂层，绝缘材料层，和带绝缘层的传导结构的深度可控制在5～20μm之间。在该情况下，如上所述，可确保沟槽结构的作用效果。
此外，根据本发明实施例的光电二极管阵列工作在200～600nm波长范围内，像素有源区的光线吸收有较好的一致性，降低像素暗电流，加快像素电荷收集速率。
尽管为了说明的目的已经描述了本发明的示范性实施例，但本领域的技术人员应该了解的是，可以进行各种修改、组合、添加和替换，而不是脱离权利要求书所公开的本发明的范围和精神。

Claims (15)

  1. 一种同面电极光电二极管阵列，包括多个同面电极光电二极管，每个同面电极光电二极管包括：
    第一导电型重掺杂半导体衬底；
    在第一导电型重掺杂半导体衬底上形成的第一导电型轻掺杂半导体层；
    在所述第一导电型轻掺杂半导体层的上部形成的第二导电型重掺杂半导体区域，其中所述第二导电型重掺杂半导体区域与所述第一导电型轻掺杂半导体层形成PN结二极管，并且第二电极从所述第二导电型重掺杂半导体层在光线入射侧引出；
    围绕所述第二导电型重掺杂半导体区域的第一导电型重掺杂半导体区域，并且第一电极从所述第一导电型重掺杂半导体区域在光线入射侧引出；以及
    设置在所述第二导电型重掺杂半导体区域和所述第一导电型重掺杂半导体区域之间的沟槽结构。
  2. 如权利要求1所述的同面电极光电二极管阵列，其中所述沟槽结构是由一种绝缘材料或多种复合绝缘材料，或光线反射材料填充沟槽而形成的。
  3. 如权利要求1所述的同面电极光电二极管阵列，其中所述沟槽结构是由与第一导电类型的重掺杂单晶半导体或多晶半导体材料填充沟槽而形成的。
  4. 如权利要求2所述的同面电极光电二极管阵列，其中所述沟槽结构包括且在所述沟槽周围形成第一导电型的重掺杂区域。
  5. 如权利要求1所述的同面电极光电二极管阵列，其中所述沟槽结构包括未填充的沟槽，且在沟槽底部及侧壁覆盖一层绝缘层、多层复合绝缘层或光线反射材料。
  6. 如权利要求5所述的同面电极光电二极管阵列，其中在沟槽周围形成第一导电型的重掺杂区域，在沟槽底部及侧壁覆盖一层绝缘层、多层复合绝缘层或光线反射材料。
  7. 如权利要求1所述的同面电极光电二极管阵列，其中所述沟槽结构包括沟槽，且在沟槽底部及侧壁覆盖一种绝缘材料，或多种复合绝缘材料，或光线反射材料，然后由单晶半导体材料或多晶半导体材料填充沟槽。
  8. 如权利要求7所述的同面电极光电二极管阵列，其中填充沟槽的单晶半导体材料或多晶半导体材料，相对于第二电极连接到高电位。
  9. 如权利要求1所述的同面电极光电二极管阵列，其中在第二导电型重掺杂半导体区域的上部形成较薄的第一导电型重掺杂区域或第二导电型轻掺杂区域，且四周被所述第二导电型重掺杂区域包围。
  10. 如权利要求1所述的同面电极光电二极管阵列，其中在所述第二导电型重掺杂区域下部形成连续第一导电类型重掺杂区域，或仅在第二导电类型重掺杂区域下方设置一段第一导电类型重掺杂区域。
  11. 如权利要求1所述的同面电极光电二极管阵列，其中在所述第二导电型重掺杂区域下面，形成连续的绝缘材料区域，或仅在所述第二导电型重掺杂区域下方设置一段绝缘材料区域。
  12. 如权利要求10或11所述的同面电极光电二极管阵列，其中所述第一导电型重掺杂区域形成为沟槽结构，向下延伸至所述第一导电型重掺杂区域或绝缘材料区域，并与之连接。
  13. 如权利要求1所述的同面电极光电二极管阵列，其中在所述第二导电型重掺杂区域下面，形成连续带绝缘层的传导结构，或仅在所述第二导电型重掺杂区域下方设置一段带绝缘层的传导结构，该传导结构由绝缘材料或半导体材料构成。
  14. 如权利要求13所述的同面电极光电二极管，其中所述第一导电型重掺杂区域为沟槽结构，向下延伸至带绝缘层的传导结构中的半导体材料区域，并与之连接。
  15. 一种制作同面电极光电二极管的方法，包括步骤：
    在第一导电型重掺杂半导体衬底上形成第一导电型轻掺杂半导体层；
    在所述第一导电型轻掺杂半导体层的上部形成第二导电型重掺杂半导体区域，其中所述第二导电型重掺杂半导体区域与所述第一导电型轻掺杂半导体层形成PN结二极管，并且第二电极从所述第二导电型重掺杂半导体层在光线入射侧引出；
    围绕所述第二导电型重掺杂半导体区域形成第一导电型重掺杂半导体区域，并且第一电极从所述第一导电型重掺杂半导体区域在光线入射侧引出；以及
    在所述第二导电型重掺杂半导体区域和所述第一导电型重掺杂半导体区域之间设置沟槽结构。
PCT/CN2016/097517 2015-12-29 2016-08-31 同面电极光电二极管阵列及其制作方法 Ceased WO2017113846A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/580,848 US10411051B2 (en) 2015-12-29 2016-08-31 Coplanar electrode photodiode array and manufacturing method thereof
JP2017562301A JP6577601B2 (ja) 2015-12-29 2016-08-31 同一面電極のフォトダイオードアレイ及びその製造方法
EP16880639.6A EP3399552B1 (en) 2015-12-29 2016-08-31 Coplanar electrode photodiode array and manufacturing method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201511010038.8A CN105448945B (zh) 2015-12-29 2015-12-29 同面电极光电二极管阵列及其制作方法
CN201511010038.8 2015-12-29

Publications (1)

Publication Number Publication Date
WO2017113846A1 true WO2017113846A1 (zh) 2017-07-06

Family

ID=55558955

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/097517 Ceased WO2017113846A1 (zh) 2015-12-29 2016-08-31 同面电极光电二极管阵列及其制作方法

Country Status (5)

Country Link
US (1) US10411051B2 (zh)
EP (1) EP3399552B1 (zh)
JP (1) JP6577601B2 (zh)
CN (1) CN105448945B (zh)
WO (1) WO2017113846A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116154022A (zh) * 2023-03-14 2023-05-23 江南大学 一种双层SiO2隔离的光电二极管结构、阵列及制造方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448945B (zh) 2015-12-29 2019-07-05 同方威视技术股份有限公司 同面电极光电二极管阵列及其制作方法
CN106784071B (zh) 2016-12-07 2018-09-28 同方威视技术股份有限公司 光电二极管器件、光电二极管探测器及其制造方法
CN107195723B (zh) * 2017-06-30 2020-05-15 上海集成电路研发中心有限公司 一种雪崩光敏器件及其制备方法
CN108562762B (zh) * 2018-01-26 2020-03-27 中国科学院大气物理研究所 一种基于双线阵的海洋飞沫测量装置及方法
US11828905B2 (en) 2018-01-26 2023-11-28 Institute Of Atmospheric Physics, Chinese Academy Of Sciences Dual line diode array device and measurement method and measurement device for particle velocity
CN108414786B (zh) * 2018-01-26 2020-03-27 中国科学院大气物理研究所 一种双线光电二极管阵列器件及粒子速度测量方法
CN110504278A (zh) * 2019-08-28 2019-11-26 无锡中微晶园电子有限公司 一种防串流光敏二极管芯片及其制造方法
CN112825339B (zh) * 2019-11-20 2025-08-26 深圳市灵明光子科技有限公司 光电探测单元、光电探测结构和光电探测器及其制备方法
US11329087B2 (en) * 2020-03-25 2022-05-10 Globalfoundries U.S. Inc. Photodetectors with adjacent anode-cathode pairs
CN114335198B (zh) * 2020-09-30 2025-02-07 思特威(上海)电子科技股份有限公司 光电二极管及tof测距装置
CN113299786B (zh) * 2021-05-21 2023-05-23 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
CN119364876A (zh) * 2024-10-12 2025-01-24 清华大学 前照式光电二极管结构及制备方法、x射线探测器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1447445A (zh) * 2002-03-22 2003-10-08 富士通株式会社 在杂质扩散区之间具有减小的寄生电容的半导体器件
CN105185796A (zh) * 2015-09-30 2015-12-23 南京邮电大学 一种高探测效率的单光子雪崩二极管探测器阵列单元
CN105448945A (zh) * 2015-12-29 2016-03-30 同方威视技术股份有限公司 同面电极光电二极管阵列及其制作方法
CN205319156U (zh) * 2015-12-29 2016-06-15 同方威视技术股份有限公司 同面电极光电二极管阵列

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310987A (en) 1976-07-16 1978-01-31 Sony Corp Photoelectric transducing semiconductor device
JPH0760887B2 (ja) * 1984-10-01 1995-06-28 オリンパス光学工業株式会社 半導体光電変換装置
US5549762A (en) * 1995-01-13 1996-08-27 International Rectifier Corporation Photovoltaic generator with dielectric isolation and bonded, insulated wafer layers
JP2000312021A (ja) 1999-04-26 2000-11-07 Sony Corp 半導体装置とその製造方法
JP2002353431A (ja) * 2001-05-22 2002-12-06 Canon Inc 光電変換装置及びその製造方法
JP4841249B2 (ja) * 2003-06-30 2011-12-21 ローム株式会社 イメージセンサおよびフォトダイオードの分離構造の形成方法
JP2005045125A (ja) * 2003-07-24 2005-02-17 Hamamatsu Photonics Kk 光検出素子の製造方法
US7492027B2 (en) * 2004-02-20 2009-02-17 Micron Technology, Inc. Reduced crosstalk sensor and method of formation
WO2008011617A2 (en) * 2006-07-21 2008-01-24 The Regents Of The University Of California Shallow-trench-isolation (sti)-bounded single-photon avalanche photodetectors
JP2008066446A (ja) 2006-09-06 2008-03-21 Sony Corp 半導体積層構造および半導体素子
JP2010278045A (ja) * 2009-05-26 2010-12-09 Panasonic Corp 光半導体装置
JP5726005B2 (ja) * 2010-08-02 2015-05-27 アイメックＩｍｅｃ Ｃｍｏｓ撮像装置アレイの製造方法
US9160949B2 (en) 2013-04-01 2015-10-13 Omnivision Technologies, Inc. Enhanced photon detection device with biased deep trench isolation
CN103594468B (zh) * 2013-11-29 2016-08-31 电子科技大学 一种快速光电探测器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1447445A (zh) * 2002-03-22 2003-10-08 富士通株式会社 在杂质扩散区之间具有减小的寄生电容的半导体器件
CN105185796A (zh) * 2015-09-30 2015-12-23 南京邮电大学 一种高探测效率的单光子雪崩二极管探测器阵列单元
CN105448945A (zh) * 2015-12-29 2016-03-30 同方威视技术股份有限公司 同面电极光电二极管阵列及其制作方法
CN205319156U (zh) * 2015-12-29 2016-06-15 同方威视技术股份有限公司 同面电极光电二极管阵列

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116154022A (zh) * 2023-03-14 2023-05-23 江南大学 一种双层SiO2隔离的光电二极管结构、阵列及制造方法
CN116154022B (zh) * 2023-03-14 2024-03-22 江南大学 一种双层SiO2隔离的光电二极管结构、阵列及制造方法

Also Published As

Publication number Publication date
EP3399552B1 (en) 2021-06-30
CN105448945A (zh) 2016-03-30
JP2018518838A (ja) 2018-07-12
JP6577601B2 (ja) 2019-09-18
CN105448945B (zh) 2019-07-05
US20180342542A1 (en) 2018-11-29
EP3399552A1 (en) 2018-11-07
EP3399552A4 (en) 2019-08-07
US10411051B2 (en) 2019-09-10

Similar Documents

Publication Publication Date Title
CN105448945B (zh) 同面电极光电二极管阵列及其制作方法
CN109690792B (zh) Spad光电二极管
US7667400B1 (en) Back-illuminated Si photomultipliers: structure and fabrication methods
US11387379B2 (en) Single photon avalanche gate sensor device
US20180269236A1 (en) Photodetection element
EP3544064B1 (en) Photodetector and light detection and ranging
CN112951857B (zh) 包括spad光电二极管的图像传感器
US11189741B2 (en) Photodiode device, photodiode detector and methods of fabricating the same
CN114361284B (zh) 二极管装置及形成二极管装置的方法
CN106847958B (zh) 光电二极管器件及光电二极管探测器
US12336306B2 (en) SPAD structure
WO2011071483A1 (en) Back-illuminated si photomultipliers: structure and fabrication methods
CN205319156U (zh) 同面电极光电二极管阵列
CN120018598A (zh) 光电转换器件、装置及其制造方法
CN206412371U (zh) 光电二极管器件及光电二极管探测器
JP7421233B2 (ja) アバランシェ光検出器（変形形態）およびこれを製造するための方法（変形形態）
CN120344001A (zh) 一种传感器结构及其制造方法
KR20210137455A (ko) 눈사태형 광검출기(변형물) 및 그 제조 방법(변형)
KR20150063882A (ko) 실리콘 광증배관 소자 및 그 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16880639

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017562301

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 15580848

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE