WO2017135604A1 - Procédé de commande de planéité de tranche épitaxiale - Google Patents

Procédé de commande de planéité de tranche épitaxiale Download PDF

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Publication number
WO2017135604A1
WO2017135604A1 PCT/KR2017/000724 KR2017000724W WO2017135604A1 WO 2017135604 A1 WO2017135604 A1 WO 2017135604A1 KR 2017000724 W KR2017000724 W KR 2017000724W WO 2017135604 A1 WO2017135604 A1 WO 2017135604A1
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epitaxial
zdd
delta
flatness
obtaining
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English (en)
Korean (ko)
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장규일
강동호
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SK Siltron Co Ltd
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LG Siltron Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Definitions

  • Embodiments relate to a method for controlling flatness of an epitaxial wafer.
  • Silicon epitaxial wafers in which a dopant such as boron is doped and a relatively low dopant is grown on a silicon wafer having a low resistivity to grow a silicon epitaxial layer having a high resistivity have high gathering capability and low latch-up characteristics. And it has a strong characteristic against slip defects at high temperatures.
  • the quality items required for such an epitaxial wafer include flatness and degree of particle contamination, and the items for the epitaxial layer itself include thickness uniformity, resistivity, metal contamination, stacking defects, slip dislocations, and the like. Etc.
  • the thickness of the wafer may be measured, and the flatness of the edge of the wafer may be measured using the measured thickness of the wafer.
  • the embodiment provides a method for controlling the flatness of an epitaxial wafer, which can be managed in a process such that a defect rate is reduced regardless of the shape or flatness level of the base substrate.
  • a method of controlling flatness of an epitaxial wafer including obtaining a flatness defect rate graph of epitaxial wafers produced by retained epitaxial reactors; Obtaining a correlation graph of Delta Z-axis Double Derivative (Delta ZDD) of the epitaxial wafer for correlation with growth conditions of the epitaxial layer; Acquiring Delta ZDD of at least one sample epitaxial wafer produced by a first epitaxial reactor of the retained epitaxial reactors under a first growth condition; And adjusting the first growth condition based on the correlation graph.
  • Delta ZDD Delta Z-axis Double Derivative
  • the method of controlling the flatness of the epitaxial wafer may further include calculating a correction value based on the Delta ZDD and the flatness defect rate graph of the at least one sample epitaxial wafer, wherein the correction value and the correlation Based on the graph, the first growth condition may be adjusted.
  • the obtaining of the flatness failure rate graph may include obtaining edge sector site frontside reference site least square plane (QF) derivation (ZF), and Z-axis double derivative (ZDD) of substrate substrates; Obtaining Delta ZDD and edge sector site frontside reference (SQ) range of epitaxial wafers based on the base substrates; Determining a defect in the flatness of the epitaxial wafers based on the ESFQR of the epitaxial wafers; And obtaining a flatness defect rate graph of the epitaxial wafer, based on the ESFQD of the base substrates and Delta ZDD of the epitaxial wafers.
  • QF edge sector site frontside reference site least square plane
  • ZDD Z-axis double derivative
  • Acquiring Delta ZDD and ESFQR of the epitaxial wafers comprises acquiring ZDD and ESFQR of the epitaxial wafers; And acquiring Delta ZDD for each of the epitaxial wafers by using a difference between ZDDs of the base substrates and ZDD of the epitaxial wafers.
  • the calculating of the correction value may include setting a target section based on a defective rate of the flatness defective rate graph; And calculating the correction value based on the Delta ZDD and the target section of the at least one sample epitaxial wafer.
  • the determining of the defectiveness of the epitaxial wafers may be determined based on a result of comparing the ESFQR of the epitaxial wafers with a predetermined reference value.
  • the preset reference value may be 100 nm to 120 nm.
  • the X axis of the flatness defective rate graph of the epitaxial wafer represents ESFQD of the substrate substrates
  • the Y axis represents Delta ZDD of the epitaxial wafers
  • the defective rate of epitaxial wafers may be divided into a plurality of regions.
  • the obtaining of the correlation graph may include obtaining Delta ZDDs of correlation epitaxial wafers produced under different growth conditions, and using the growth conditions and Delta ZDDs of the obtained correlation epitaxial wafers.
  • the correlation graph may be obtained.
  • the growth condition and the first growth condition in the obtaining of the correlation graph may be a flow rate of H 2 gas, a flow rate of TCS, or a growth temperature.
  • the setting of the target section may be a section in which the flatness defective rate is less than a predetermined reference value for the entire range of the ESFQDs of the substrate substrates.
  • the preset reference value may be 0.1% to 15%.
  • the correction value may be a difference between a predetermined target value belonging to the target section and a delta ZDD of the at least one sample epitaxial wafer.
  • the predetermined target value may be a lower limit, an upper limit, or an intermediate value of the target section.
  • the first growth condition may be adjusted to a second growth condition corresponding to a value obtained by adding the correction value to Delta ZDD in the first growth condition of the first epitaxial reactor.
  • a method of controlling flatness of an epitaxial wafer may include obtaining ESFQDs and first ZDDs of first substrate substrates; Obtaining an ESFQR and a second ZDD of first epitaxial wafers based on the first substrate substrates; Obtaining a first Delta ZDD of the first epitaxial wafers; Determining a flatness failure of the first epitaxial wafers based on an ESFQR of the first epitaxial wafers, and obtaining a flatness failure rate graph; Obtaining a correlation graph between epitaxial layer growth conditions of a second epitaxial wafer and Delta ZDD of the second epitaxial wafer; Obtaining a second Delta ZDD of at least one third epitaxial wafer produced under first growth conditions; Calculating a correction value based on the second Delta ZDD and the flatness defective rate graph; And adjusting the first growth condition to a second growth condition based on the correction value and the correlation graph.
  • the method of controlling the flatness of the epitaxial wafer may further include producing an epitaxial wafer under the second growth condition.
  • the obtaining of the correlation graph may include: growing the epitaxial layer on the second substrate substrates under different growth conditions of the same growth condition item to produce the second epitaxial wafers; Acquiring Delta ZDD of the produced second epitaxial wafers; And obtaining the correlation graph by using the different growth conditions and the delta ZDD of the second epitaxial wafers.
  • Acquiring the second Delta ZDD may include: growing an epitaxial layer on a plurality of third substrate substrates under the first growth condition to produce a plurality of third epitaxial wafers; And obtaining Delta ZDD of the plurality of third epitaxial wafers and setting an average of the obtained Delta ZDD of the plurality of third epitaxial wafers to the second Delta ZDD.
  • the calculating of the correction value may include setting a target section in which the flatness defective rate is smaller than a preset reference value in the flatness defective rate graph; And calculating the correction value such that the second Delta ZDD belongs to the target section.
  • the adjusting of the first growth condition to the second growth condition may change the first growth condition by a growth condition corresponding to the correction value.
  • the process control may be performed so that the defective rate is small regardless of the shape or flatness level of the base substrate.
  • FIG. 1 is a flowchart illustrating a method of controlling flatness of an epitaxial wafer according to an embodiment.
  • FIG. 2 is a flowchart illustrating a step of obtaining a defective rate graph shown in FIG. 1.
  • FIG. 3 is a flowchart illustrating an embodiment of the delta ZDD1 acquisition and ESFQR1 acquisition steps shown in FIG. 2.
  • step S240 shows a defective rate graph obtained in step S240.
  • 5a shows the correlation between the flow rate of H 2 gas supplied for Delta ZDD and epitaxial layer growth.
  • 5B shows the correlation between Delta ZDD and epitaxial layer growth temperature.
  • Figure 5c shows the correlation between the flow rate of Delta ZDD and TCS supplied for epitaxial layer growth.
  • FIG. 6 illustrates an embodiment of calculating a correction value of FIG. 1.
  • FIG. 7B is a sectional view taken along ab direction of the schematic diagram of FIG. 7A.
  • each layer (region), region, pattern, or structure is “on” or “under” the substrate, each layer (film), region, pad, or pattern.
  • “up” and “under” include both “directly” or “indirectly” formed through another layer. do.
  • the criteria for up / down or down / down each layer will be described with reference to the drawings.
  • Like reference numerals denote like elements throughout the description of the drawings.
  • FIG. 1 is a flowchart illustrating a method of controlling flatness of an epitaxial wafer according to an embodiment.
  • the method of controlling the flatness of the epitaxial wafer may include obtaining a flatness defect rate graph (S110), obtaining a correlation graph between a growth condition and Delta ZDD (S120), Acquiring Delta ZDD2 (S130), calculating a correction value based on the delta ZDD2 and the flatness defective rate graph (S140), adjusting the growth conditions based on the correction value and the correlation graph (S150), and Producing under controlled growth conditions (S160).
  • a flatness defect rate graph may be obtained based on edge sector site frontside reference Q (Derivation of Site least square plane) Q of test substrate substrates and delta ZDD of test epitaxial wafers (S110).
  • FIG. 2 is a flowchart illustrating an embodiment of obtaining a defective rate graph shown in FIG. 1 (S110).
  • obtaining a defective rate graph may include obtaining ESFQDs and ZDDs (hereinafter referred to as “ZDD1”) of test substrate substrates (S210), and obtaining Delta ZDD1 (S220). Determining the flatness failure of the test epitaxial wafer (S230), and obtaining a failure rate graph (S240).
  • ESFQD and ZDD1 are acquired (S210).
  • ESFQD is an abbreviation of edge sector site frontside reference Q (Site least square plane) derivation, and may have a + value or a-value.
  • FIG. 7A is a schematic diagram for explaining ESFQD and ESFQR
  • FIG. 7B is a cross-sectional view taken along ab direction of the schematic diagram of FIG. 7A.
  • the section 401 is a section from the first point P1 to the second point P2 of the equalized site (eg, S1), and the first point P1 is located at the edge E1 of the wafer W1.
  • the second point P2 is a point spaced apart by a predetermined distance (eg, 1 mm or 2 mm), and the second point P2 is a point spaced by a certain distance (eg, 10 mm) in a direction from the first point toward the center C of the wafer W1.
  • the ESFQD may be a value obtained by integrating an average value of the wafer thicknesses of the section 401, for example, the thickness of the wafer W1 in the section 401.
  • ESFQR edge sector site frontside reference Q (Site least square plane) range, and is a method of indicating flatness of a wafer.
  • the ESFQR is defined as the difference MAX-MIN between the maximum value MAX and the minimum value MIN of the thickness of the wafer W1 measured in the section 401.
  • ZDD stands for Z-axis Double Derivative and is a parameter indicating the degree of roll-off of the edge surface of the wafer, and represents the curvature of the edge surface of the wafer.
  • the z-axis direction may be a thickness direction of the wafer.
  • the profile of the thickness of the front and back sides of the wafer can be expressed as a “function of Z”.
  • an average radial profile of the entire wafer with respect to Z can be obtained, and the obtained average radial profile ZDD can be found by differentiating.
  • ZDD may be defined as in Equation 1.
  • ESFQD and ZDD1 of the test substrate substrates may be obtained or calculated in the same manner as described above.
  • ESFQD and ZDD1 of the test substrate substrates may be values already known at the time of purchase.
  • delta ZDD hereinafter referred to as “delta ZDD1”
  • ESFQR hereinafter referred to as “ESFQR1”
  • FIG. 3 is a flowchart illustrating an embodiment of acquiring Delta ZDD1 and ESFQR1 (S220) shown in FIG. 2.
  • an epitaxial layer is grown on test substrates to produce test epitaxial wafers (S310).
  • M epitaxial wafers can be produced by growing epitaxial layers on M (N> 1 natural water) epitaxial reactors on M (N> 1 natural water) test substrate substrates. have.
  • Each of the N epitaxial reactors may grow an epitaxial layer on substrate substrates randomly selected from among M (natural number M> 1) test substrate substrates.
  • test substrate substrates are divided into a plurality of groups according to the number of N epitaxial reactors, and each of the N epitaxial reactors grows an epitaxial layer on substrate substrates belonging to a corresponding one of the plurality of groups. Can be.
  • each of the epitaxial reactors grows an epitaxial layer on 3,000 randomly selected substrate substrates, and 30,000 Test epitaxial wafers can be produced.
  • ZDD2 ZDD2
  • ESFQR1 ESFQR1 of each of the test epitaxial wafers produced
  • ESFQR1 may be the same as described above with reference to FIGS. 7A and 7B, and the method of obtaining ZDD2 may be the same as described with reference to ZDD1.
  • Delta ZDD (hereinafter referred to as “Delta ZDD1”) for each test epitaxial wafer is obtained (S330).
  • Delta ZDD may be defined as the difference between the ZDD of the epitaxial wafer and the ZDD of the base substrate itself of the epitaxial wafer.
  • Delta ZDD1 may be defined as shown in Equation 2.
  • a defect in the flatness of the test epitaxial wafers may be determined based on a result of comparing the ESFQR1 of the test epitaxial wafers with a predetermined reference value.
  • the preset reference value may be 100 nm to 120 nm.
  • the preset reference value may be 110 nm.
  • the ESFQR1 of the test epitaxial wafers exceeds a predetermined reference value, it may be determined to be a defect, and when the ESFQR1 of the test epitaxial wafers is less than or equal to the predetermined reference value, it may be determined that the defect is not defective.
  • step S240 shows a defective rate graph obtained in step S240.
  • the X axis represents ESFQDs of the test substrate substrates, and may be divided by a predetermined interval (eg, 25 nm) around 0, and the unit may be nm.
  • the Y axis represents Delta ZDD1 of the epitaxial wafers for test, and may be divided by a predetermined interval (for example, 5 or 10) around zero.
  • the defective rate of the epitaxial wafers for testing may be divided into a plurality of regions, for example, the first to twentieth regions 1 to 20.
  • the defective rate of each of the first to twentieth regions 1 to 20 may be a ratio of the number of test epitaxial wafers included in each region to the number of test epitaxial wafers determined as defective in operation S230.
  • a failure rate of zero in the first region 1 means that all the test epitaxial wafers included in the first region 1 are not defective.
  • a correlation or correlation graph between the growth conditions of the epitaxial layer and Delta ZDD of the epitaxial wafer for correlation is obtained (S120).
  • the order of steps S110 and S120 may be reversed.
  • steps S110 and S120 may be performed at the same time.
  • the epitaxial wafers may be produced by growing the epitaxial layer on the correlated substrate substrates with different growth conditions for the same growth condition items.
  • the growth condition item may include the flow rate of the TCS, the H 2 gas, and the growth temperature.
  • Delta ZDDs of correlated epitaxial wafers produced by different growth conditions of the same growth condition item are obtained.
  • Correlation graphs may be obtained using Delta ZDD of epitaxial wafers for correlation with different growth conditions.
  • the correlation graph may be used to obtain an equation regarding correlation (eg, a linear equation).
  • the correlation substrate substrates may be separate or different substrate substrates from the test substrate substrates.
  • FIG. 5A shows a correlation and correlation graph between Delta ZDD of correlated epitaxial wafers and a flow rate of H 2 gas supplied for epitaxial layer growth
  • FIG. 5B shows correlated epitaxial wafers. Correlation and correlation graphs between Delta ZDD and epitaxial layer growth temperature are shown. Indicates.
  • 5A to 5C show an experimental result of obtaining Delta ZDD of correlated epitaxial wafers while changing growth conditions (flow rate of TCS, H 2 gas, and growth temperature).
  • 5A to 5C show Delta ZDDs of correlated epitaxial wafers produced under a plurality of different growth conditions (eg, five).
  • Delta ZDD of correlated epitaxial wafers may be an average value of Delta ZDD of correlated epitaxial wafers of a predetermined number (eg, 10) in each of a plurality of different growth conditions.
  • Delta ZDD2 a current Delta ZDD for the epitaxial reactor to be used is obtained (S130).
  • the method of obtaining Delta ZDD2 may be equally applicable to the description of Delta ZDD1.
  • an epitaxial layer is grown on at least one sample substrate substrate under a first growth condition using an epitaxial reactor currently used among N retained epitaxial reactors to produce at least one sample epitaxial wafer.
  • the delta ZDD of at least one sample epitaxial wafer produced may be delta ZDD2.
  • a plurality of sample epitaxial wafers are produced by growing an epitaxial layer on a plurality of (eg, five) sample base substrates under a first growth condition using a first epitaxial reactor that is desired to be used.
  • Delta ZDD of the four sample epitaxial wafers may be obtained, and an average of the obtained Delta ZDD of the plurality of sample epitaxial wafers may be Delta ZDD2.
  • the first growth condition may coincide with the item of the growth condition in the correlation graph acquisition step.
  • the growth conditions in the correlation graph acquisition step with the first growth conditions may include the flow rate of the TCS, the flow rate of the H 2 gas, or the growth temperature described with reference to FIGS. 5A to 5C.
  • the embodiment illustrates three first growth conditions, but is not limited thereto.
  • other growth conditions that have a linear correlation with Delta ZDD of the epitaxial wafer may also be included in the first growth conditions of the first epitaxial reactor.
  • FIG. 6 illustrates an embodiment of calculating a correction value S140 of FIG. 1.
  • the correction value calculating step S140 may include a target section setting step S410 and a correction value calculating step S420.
  • a target section of the Delta ZDD may be set (S410).
  • the target section of Delta ZDD may be a section in which the flatness defective rate is smaller than a predetermined reference value for the entire range (eg, ⁇ 75 to 25) of the ESFQDs of the test substrate substrates in the flatness defective rate graph.
  • the preset reference value may be 0.1% to 15%.
  • the third, eighth, thirteenth, and eighteenth regions are included in the target section of the Delta ZDD. (3,8,13,18) may be included, and the Delta ZDD of the target section of the Delta ZDD may be 0 to -5 nm. In the region where Delta ZDD is 0 to -5 nm, the flatness defect rate is less than 4% for the entire range of ESFQD of the substrate substrates.
  • the target section of the Delta ZDD may be set in consideration of the ESFQDs of the base substrates. For example, if the range of ESFQDs of the substrate substrates introduced into the first epitaxial reactor is limited to 0 nm to -50 nm, the target section of the Delta ZDD may be set according to a predetermined reference value. For example, when the predetermined reference value is 0.5%, the target section of the Delta ZDD may include regions 8 and 13.
  • a correction value is calculated based on the Delta ZDD2 of the current sample epitaxial wafer and the target section for the first epitaxial reactor to be used (S420). This is to correct the Delta ZDD2 using the correction value so that the current Delta ZDD2 belongs to the target section.
  • the correction value may be a difference between the preset target value belonging to the target section and the Delta ZDD2.
  • the predetermined target value belonging to the target section may be a lower limit, an upper limit, or an intermediate value of the target section.
  • the correction value is at the preset target value (eg -2.5).
  • the value may be minus Delta ZDD2 (eg, 7).
  • the growth conditions of the first epitaxial reactor are adjusted based on the correction value and the correlation graph (S150).
  • the current first growth condition of the first epitaxial reactor may be changed by the growth condition corresponding to the correction value.
  • the first growth condition may be adjusted to a second growth condition corresponding to a value obtained by adding a correction value to Delta ZDD in the first growth condition of the first epitaxial reactor.
  • the flow rate of the H 2 gas in the first epitaxial reactor may be adjusted from 90 [slm] to 72.352 [slm].
  • the correction value is -9.5 and the current temperature of the first epitaxial reactor is 1130 ° C.
  • the Delta ZDD at the current temperature (1130 ° C.) is 12.094, and the temperature of the first epitaxial reactor is from 1130 ° C. to about 1123 ° C. for correction. Can be adjusted.
  • the TCS flow rate of the first epitaxial reactor may be adjusted for correction by using the graph of FIG. 5C with respect to the flow rate of the TCS gas.
  • the epitaxial wafer is produced under controlled growth conditions in the first epitaxial reactor (S160).
  • the defect rate falls within a range to be managed regardless of which ESFQD value the substrate substrate has. Due to this, process control can be performed so that the defect rate is low.
  • the value of ZDD varies depending on the level of flatness of the base substrate, but Delta ZDD may have a characteristic of being kept constant regardless of the level of flatness of the base substrate.
  • the embodiment may be used in the method of controlling the flatness of the epitaxial wafer, which can be managed to reduce the defect rate regardless of the shape or flatness level of the base substrate.

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Abstract

Un mode de réalisation comprend les étapes consistant à : acquérir un graphique de taux de défaut de planéité de tranches épitaxiales produites par des chambres de réaction épitaxiales en possession ; acquérir un graphique de corrélation de ZDD delta de tranches épitaxiales pour une corrélation avec des conditions de croissance de couches épitaxiales ; acquérir ZDD delta d'au moins un échantillon de tranche épitaxiale obtenue dans une première condition de croissance par une première chambre de réaction épitaxiale parmi les chambres de réaction épitaxiales en possession ; et commander la première condition de croissance sur la base du graphique de corrélation.
PCT/KR2017/000724 2016-02-02 2017-01-20 Procédé de commande de planéité de tranche épitaxiale Ceased WO2017135604A1 (fr)

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KR1020160012849A KR101810643B1 (ko) 2016-02-02 2016-02-02 에피텍셜 웨이퍼의 평탄도 제어 방법

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EP3957776A1 (fr) 2020-08-17 2022-02-23 Siltronic AG Procédé de dépôt d'une couche épitaxiée sur une tranche de substrat
EP3996130A1 (fr) 2020-11-09 2022-05-11 Siltronic AG Procédé de dépôt d'une couche épitaxiée sur une tranche de substrat
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CN110852021A (zh) * 2018-07-26 2020-02-28 上海新昇半导体科技有限公司 基于模拟方式获得外延平坦度的方法
CN110852021B (zh) * 2018-07-26 2024-02-06 上海新昇半导体科技有限公司 基于模拟方式获得外延平坦度的方法
EP3957776A1 (fr) 2020-08-17 2022-02-23 Siltronic AG Procédé de dépôt d'une couche épitaxiée sur une tranche de substrat
WO2022037889A1 (fr) 2020-08-17 2022-02-24 Siltronic Ag Procédé de dépôt d'une couche épitaxiale sur une plaquette de substrat
US12331424B2 (en) 2020-08-17 2025-06-17 Siltronic Ag Method for depositing an epitaxial layer on a substrate wafer
EP3996130A1 (fr) 2020-11-09 2022-05-11 Siltronic AG Procédé de dépôt d'une couche épitaxiée sur une tranche de substrat
WO2022096332A1 (fr) 2020-11-09 2022-05-12 Siltronic Ag Procédé de dépôt de couche épitaxiale sur une tranche de substrat
US12532700B2 (en) 2020-11-09 2026-01-20 Siltronic Ag Method for depositing an epitaxial layer on a substrate wafer
CN115821234A (zh) * 2022-12-13 2023-03-21 杭州富芯半导体有限公司 改善薄膜表面平坦度的方法

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