WO2017152181A1 - Onduleur multiniveau à cellules en u encapsulées en cascade - Google Patents

Onduleur multiniveau à cellules en u encapsulées en cascade Download PDF

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Publication number
WO2017152181A1
WO2017152181A1 PCT/US2017/020967 US2017020967W WO2017152181A1 WO 2017152181 A1 WO2017152181 A1 WO 2017152181A1 US 2017020967 W US2017020967 W US 2017020967W WO 2017152181 A1 WO2017152181 A1 WO 2017152181A1
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Prior art keywords
packed
multilevel inverter
cell
cascaded
cell multilevel
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Mohd. TARIQ
Atif IQBAL
Mohammad MERAJ
Lazhar BENBRAHIM
Rashid AL-AMMARI
Haitham ABU-RUB
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Qatar University
Qatar Foundation
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Qatar University
Qatar Foundation
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for AC mains or AC distribution networks
    • H02J3/38—Arrangements for feeding a single network from two or more generators or sources in parallel; Arrangements for feeding already energised networks from additional generators or sources in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for AC mains or AC distribution networks
    • H02J3/38—Arrangements for feeding a single network from two or more generators or sources in parallel; Arrangements for feeding already energised networks from additional generators or sources in parallel
    • H02J3/381—Dispersed generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for AC mains or AC distribution networks
    • H02J3/38—Arrangements for feeding a single network from two or more generators or sources in parallel; Arrangements for feeding already energised networks from additional generators or sources in parallel
    • H02J3/46—Controlling the sharing of generated power between the generators, sources or networks
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2101/00—Supply or distribution of decentralised, dispersed or local electric power generation
    • H02J2101/20—Dispersed power generation using renewable energy sources
    • H02J2101/22—Solar energy
    • H02J2101/24—Photovoltaics
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for AC mains or AC distribution networks
    • H02J3/38—Arrangements for feeding a single network from two or more generators or sources in parallel; Arrangements for feeding already energised networks from additional generators or sources in parallel
    • H02J3/40—Synchronisation of generators for connection to a network or to another generator
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4833—Capacitor voltage balancing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Definitions

  • the present invention relates to power converters, and particularly to a power converter for transforming direct current (DC) power to alternating current (AC) power with variable voltage magnitude and variable frequency output using a cascade of packed U-cell (PUC) multilevel inverters.
  • DC direct current
  • AC alternating current
  • PUC packed U-cell
  • Multilevel inverters are commonly used as an interface in renewable energy generation systems, such as solar photovoltaic (PV) applications. Multilevel inverters are also commonly used in medium voltage and high power motor drive systems, such as those found in electric and hybrid vehicles.
  • the wide usage of multilevel inverters is due to a number of desirable properties, such as reduced voltage stress on power semiconductor switches, reduced voltage harmonics, reduced reduced electromagnetic interference, and a comparatively higher efficiency.
  • the switching frequency and device ratings of conventional multilevel inverters are limited.
  • NPC neutral point clamped
  • FLC flying capacitor
  • CHB cascaded H-bridge
  • the cascaded packed U-cell multilevel inverter is a power converter for transforming direct current (DC) power to alternating current (AC) power with variable voltage magnitude and variable frequency output.
  • the cascaded packed U-cell multilevel inverter includes a first packed U-cell (PUC) multilevel inverter and at least one sequential packed U-cell multilevel inverter connected in cascade to the first packed U-cell multilevel inverter; i.e., the cascaded packed U-cell multilevel inverter is formed by cascading two or more PUC multilevel inverter units.
  • each PUC multilevel inverter is a 7-level inverter including a DC link capacitor adapted for connection to a separate independent DC power source and a flying capacitor clamping the multilevel inverter to one-third of the voltage of the corresponding power source.
  • the voltage developed over the DC link capacitors for the first packed U-cell multilevel inverter and the second packed U-cell multilevel inverter(s) may have a voltage ratio of 4:1, such that thirty-one output voltage levels are selectively obtained.
  • the voltage developed over the DC link capacitors for the first PUC multilevel inverter and the second PUC multilevel inverter(s) may have a voltage ratio of 7: 1, such that forty-nine output voltage levels are selectively obtained.
  • FIG. 1 is a block diagram illustrating a cascaded packed U-cell multilevel inverter according to the present invention.
  • Fig. 2 is a schematic diagram of a single packed U-cell (PUC) multilevel inverter used in the cascaded packed U-cell multilevel inverter according to the present invention.
  • PUC packed U-cell
  • Fig. 3 illustrates the eight distinct switching states available for the single packed U- cell (PUC) multilevel inverter of Fig. 2.
  • PUC single packed U- cell
  • Fig. 4 is a schematic diagram illustrating the cascaded packed U-cell multilevel inverter according to the present invention.
  • Fig. 5A illustrates the switching pattern for a first packed U-cell multilevel inverter of the cascaded packed U-cell multilevel inverter.
  • Fig. 5B illustrates the switching pattern for a second packed U-cell multilevel inverter of the cascaded packed U-cell multilevel inverter.
  • Fig. 6 is a block diagram illustrating the cascaded packed U-cell multilevel inverter integrated into an exemplary solar photovoltaic (PV)/direct current (DC) power system.
  • PV solar photovoltaic
  • DC direct current
  • Fig. 7 is a schematic diagram illustrating the cascaded packed U-cell multilevel inverter with an associated control system.
  • Fig. 8 schematically illustrates a conventional prior art 31 -level inverter.
  • Fig. 9A shows load voltage, load current and inverter terminal voltage for a simulated cascaded packed U-cell multilevel inverter according to the present invention.
  • Fig. 9B compares simulated voltage output for a first packed U-cell multilevel inverter of the cascaded packed U-cell multilevel inverter against simulated voltage output for a second packed U-cell multilevel inverter of the cascaded packed U-cell multilevel inverter and simulated overall terminal voltage for the cascaded packed U-cell multilevel inverter according to the present invention.
  • Fig. 9C is a graph showing DC bus voltages and flying capacitor voltages for the simulated cascaded packed U-cell multilevel inverter.
  • Fig. 9D is a graph showing the carrier signal and modulation signal for the simulated cascaded packed U-cell multilevel inverter.
  • Fig. 10A is a graph showing voltage output of the cascaded packed U-cell multilevel inverter with a 31 -level output.
  • Fig. 1 OB is a graph showing voltage output of the cascaded packed U-cell multilevel inverter with a 25 -level output.
  • Fig. IOC is a graph showing voltage output of the cascaded packed U-cell multilevel inverter with a 19-level output.
  • Fig. 10D is a graph showing voltage output of the cascaded packed U-cell multilevel inverter with a 13 -level output.
  • Fig. 10E shows the results of a harmonic analysis on the terminal voltage of the cascaded packed U-cell multilevel inverter according to the present invention.
  • Fig. 11 A shows the results of measured DC supply and flying capacitor voltages for the cascaded packed U-cell multilevel inverter according to the present invention.
  • Fig. 1 IB shows the results of the measured load voltage for the cascaded packed U- cell multilevel inverter according to the present invention.
  • Fig. 11C shows the results of the measured cross-resistor current and terminal voltage for the cascaded packed U-cell multilevel inverter according to the present invention.
  • Fig. 1 ID compares the outputs of a first packed U-cell multilevel inverter and a second packed U-cell multilevel inverter of the cascaded packed U-cell multilevel inverter, and further compared against overall output of the cascaded packed U-cell multilevel inverter.
  • Fig. 1 IE shows the results of measured voltages across switch pairs of the first packed
  • Fig. 1 IF shows the results of measured voltages across switch pairs of the second packed U-cell multilevel inverter of the cascaded packed U-cell multilevel inverter.
  • Fig. 12A shows experimental results of the measured spectrum of load voltage of the cascaded packed U-cell multilevel inverter.
  • Fig. 12B shows experimental results of the measured spectrum of load current of the cascaded packed U-cell multilevel inverter.
  • Fig. 13A shows the results of measured output voltages of the cascaded packed U-cell multilevel inverter for 31 -level output.
  • Fig. 13B shows the results of measured output voltages of the cascaded packed U-cell multilevel inverter for 25 -level output.
  • Fig. 13C shows the results of measured output voltages of the cascaded packed U-cell multilevel inverter for 19-level output.
  • Fig. 13D shows the results of measured output voltages of the cascaded packed U-cell multilevel inverter for 13 -level output.
  • Fig. 14A shows the results of measured DC supply and flying capacitor voltages of an alternative cascaded packed U-cell multilevel inverter with a 49-level output.
  • Figs. 14B and 14C show the results of measured load voltage and current across a resistor, as well as terminal voltage, for the alternative cascaded packed U-cell multilevel inverter with a 49-level output.
  • Fig. 14D shows the results of the measured output of first and second cascaded packed U-cell multilevel inverters, as well as the overall output of the alternative cascaded packed U-cell multilevel inverter with a 49-level output.
  • Fig. 14E shows the results of the measured voltages across the switches of the first packed U-cell multilevel inverter of the alternative cascaded packed U-cell multilevel inverter with a 49-level output.
  • Fig. 14F shows the results of the measured voltages across the switches of the second packed U-cell multilevel inverter of the alternative cascaded packed U-cell multilevel inverter with a 49-level output.
  • Fig. 14G shows the results of the measured terminal voltage and grid/load voltage of the alternative cascaded packed U-cell multilevel inverter with a 49-level output.
  • Fig. 15A shows the results of a harmonic analysis of the load current of the alternative cascaded packed U-cell multilevel inverter with a 49-level output.
  • Fig. 15B shows the results of a harmonic analysis of the terminal voltage of the alternative cascaded packed U-cell multilevel inverter with a 49-level output.
  • Fig. 16A shows the measured output voltages for the alternative cascaded packed U- cell multilevel inverter with a 49-level output.
  • Fig. 16B shows a magnified view of the output's positive cycle from the output of Fig. 16A.
  • Fig. 16C shows the output voltages for a further alternative cascaded packed U-cell multilevel inverter with a 43 -level output.
  • Fig. 16D shows the output voltages for another alternative cascaded packed U-cell multilevel inverter with a 37-level output.
  • the cascaded packed U-cell multilevel inverter 10 is a power converter for transforming direct current (DC) power to alternating current (AC) power with variable voltage magnitude and variable frequency output.
  • the cascaded packed U-cell multilevel inverter 10 includes a first asymmetrical flying capacitor (AFLC) or packed U-cell (PUC) multilevel inverter (AFLC/PUC- 1) 12 and at least one asymmetrical flying capacitor (AFLC) or packed U-cell (PUC) multilevel inverter 14 connected in cascade to the first packed U-cell multilevel inverter 12, i.e., the cascaded packed U-cell multilevel inverter 10 is formed by cascading two or more PUC multilevel inverter units.
  • AFLC/PUC- n represents the n-th asymmetrical flying capacitor (AFLC) or packed U-cell (PUC) multilevel inverter 14 in a cascade of n AFLC/PUCs.
  • each PUC multilevel inverter 16 is, preferably, a 7-level inverter including six power switching devices, a DC link capacitor adapted for connection to a separate independent DC power source and a flying capacitor clamping the multilevel inverter to one-third of the voltage of the corresponding power source.
  • the DC link can be obtained from a solar photovoltaic module, a standard AC/DC converter or the like.
  • PUC multilevel inverter 16 is shown as having six power switching devices SI, S2, S3, SI ', S2' and S3' .
  • the clamping capacitor or flying capacitor voltage Vi is one-third of the DC link voltage V 2 .
  • the switches SI, S2, S3, SI' , S2' and S3' may be MOSFETs, IGBTs or the like. Switch pairs SI, SI' ; S2, S2' ; and S3, S3' are complimentary in operation.
  • V DC (State 1) V DC (State 2), 0 (State 3), ⁇ ⁇ v D c (State 4), - V DC (State 5), i
  • the voltage developed over the DC link capacitors for the first packed U-cell multilevel inverter 12 and a second packed U-cell multilevel inverter 14, with the two units each generating 7-level output, may have a voltage ratio of 4: 1 (or 1 :4), such that thirty-one output voltage levels are selectively obtained.
  • the thirty-one overall output phase voltage levels are achieved when the two PUC inverters 12, 14 are supplied from two isolated DC sources 22, 24, respectively.
  • the two cascaded units 12, 14 can be supplied from two isolated supplies, such as, for example, two solar photovoltaic (PV) arrays with a voltage ratio of 1:4 or 4: 1. If the ratio of the two isolated DC supplies 22, 24 is changed then the number of output voltage levels is also changed.
  • PV solar photovoltaic
  • the two PUC inverters 12, 14 can be controlled using level or phase-shifted multicarrier pulse width modulation techniques.
  • a higher number of voltage levels gives rise to lower lower electromagnetic interference, lower switching losses and higher conversion efficiency. This remains true for any number of output phases, such as, for example, three-phase or five -phase outputs, which can be achieved by cascading identical PUC inverter units.
  • the cascaded packed U-cell multilevel inverter 10 may be used in a wide variety of applications, such as solar PV for supplying power to a utility grid, variable speed drives, electric vehicles, HVDC, in power systems, etc.
  • the cascaded packed U-cell multilevel inverter 10 produces output voltage in several steps, depending upon the number of levels. For example, a five level output requires five steps. As the number of steps grows, the waveform grows closer to being sinusoidal. The ideal waveform is a pure sine wave, which is not realistically possible when generated using power electronic devices.
  • a neutral point clamped (NPC) 7-level inverter uses a single DC power source, ten power switches, six DC link capacitors and eight clamping diodes.
  • the NPC 7-level inverter includes a total of 25 separate components with a very high level of control complexity.
  • a flying capacitor converter (FLC) 7-level inverter also uses a single DC power source, ten power switches, six DC link capacitors and four clamping capacitors.
  • the FLC 7-level inverter includes a total of 21 separate components, also with a very high level of control complexity.
  • the cascaded H-bridge (CHB) 7-level inverter uses two DC power sources, twelve power switches, and three DC link capacitors.
  • the CHB 7-level inverter includes a total of 17 separate components, with a low level of control complexity.
  • the present cascaded packed U-cell multilevel inverter 10 uses a single DC power source, only six power switches, only one DC link capacitor and only one clamping capacitor.
  • the cascaded packed U-cell multilevel inverter 10 includes a total of only nine separate components with a moderate level of control complexity.
  • V DC1 Considering one DC link voltage, V DC1 , and a second DC link voltage, V DC2 , then a 1: 1 ratio of V DC1 : V DC2 yields 13 output voltage levels. Similarly, a V DC1 : V DC2 ratio of 1 :2 yields 19 output voltage levels.
  • the number of voltage levels that can be achieved is 7. As noted above, the seven levels are V DC , in the positive half-cycle, and in the negative
  • This single stage PUC will switch at a relatively high switching frequency (about 2 to 10 kHz).
  • two cascaded PUC inverters will include one switching at high frequency (about 2 to 10 kHz) and the other switching at a lower frequency.
  • the second cascaded PUC stage will produce all of its seven levels with low frequency switching.
  • the inverter which operates at the higher frequency, should operate at low voltages and repeat all of its four levels on every step of the low frequency inverter unit.
  • 31-levels can be achieved in two cascaded PUC inverters. Further, if three PUC modules are cascaded, then two modules at low voltage will switch at a high
  • the third PUC inverter (16V DC ) will be at a low frequency.
  • the number of voltage levels that can be achieved is increased to 127 in this case.
  • the required DC bus voltages follow the progression
  • L 2 X 4 n - 1.
  • the number of output voltage level can be increased to 49.
  • the inverter operating at high frequency should then operate at low voltages and repeat all seven levels on every step of the low
  • the ratio of V DC1 and V DC2 is increased further, the number of levels can be further increased, however, the step size of the level will not be uniform. Thus, it is preferred to keep the ratio to 1 :4 or 4: 1, where the output number of levels is 31 (in the case of two units of cascading PUC inverters).
  • Fig. 4 shows two such PUC inverters 12, 14 cascaded and connected across the common load.
  • Fig. 4 do not switch in half of the switching period, while the middle two switches make seven switching transitions (i.e., on and off), and the bottom two switches make 14 switching transitions in the same half switching period.
  • Fig. 5B it can be seen that the switching frequency of switches S5, S5' is twice the switching frequency of switches S4, S4' .
  • the switching frequency of switches S6, S6' is three times that of switches S4, S4' .
  • the top two switches (S4, S4') do not switch in the half cycle, the middle switches (S5, S5') switch only once, and the bottom switches (S6, S6') switch three times.
  • inverter 2 When comparing the switching of the two cascaded inverters, it can be seen that the total number of switches in one switching period of inverter 1 is 44, while inverter 2 only switches 13 times in one switching period. It is important to note that the switching frequency of inverter 2 is significantly lower than that of inverter 1. This is a notable advantage since, for high power applications, inverter 2 can use gate turn-off thyristors (GTOs) or thyristors and, similarly, the top switches of inverter 1 can also be GTOs or thyristor.
  • GTOs gate turn-off thyristors
  • thyristors thyristors
  • the PUC inverter with the higher DC link voltage will be switched at the lower frequency in order to keep the switching losses to a minimum.
  • Each of the PUC inverters can be controlled using simple multicarrier level shifted and/or phase shifted pulse width modulation (PWM) techniques.
  • PWM pulse width modulation
  • Standard available multicarrier PWM techniques can be employed, such as phase disposed (PD) PWM, alternative phase opposed disposed (APOD) PWM, or phase opposed disposed (POD) PWM.
  • a closed-loop control is adopted.
  • the voltage sensors sense the two DC link voltages and the two flying capacitor voltages across the capacitors.
  • One AC voltage sensor is used to sense the magnitude and frequency of the grid/load voltage in order to synchronize the generated voltage.
  • a current sensor is used to sense the load current used in the current control loop.
  • the control code can be operated on a control platform, such as a digital signal processor (DSP), a microcontroller, exemplary field-programmable gate array (FPGA) 36 or the like.
  • DSP digital signal processor
  • FPGA field-programmable gate array
  • the FPGA 36 or the like may be linked to a hosting computer, such as personal computer 30 or the like, allowing the control code to be written in an appropriate coding language, such as C/C++, Matlab/Simulink, VHSIC hardware description language (VHDL) or the like.
  • FPGA 36 generates appropriate gating signals that are fed to a gate driver circuit 38.
  • the gate drive circuit 38 then switches the power converters 12, 14 accordingly.
  • A/D analog-digital
  • the power converter 10 has to control the power injection such as, for example, reactive control and real power control.
  • the converter is modeled in the dq-plane, and then a suitable controller is designed for tracking the reference.
  • the control objectives are balancing the flying capacitor voltage (i.e., holding at one-third of the DC link, as indicated at 60 and 62 in Fig. 7) and controlling load or grid current to be sinusoidal.
  • the controller compensates the flying capacitor voltage with the inverter current. This is achieved by proportional integral (PI) controllers 64, 66, which minimize the constant error between the reference and the actual signals. Since there are two cascaded AFLC/PUC modules, both flying capacitor voltages will charge and discharge with the same load or grid current. Thus, the error signals of both modules are added to get the desired current reference error signal. To have control over the reactive and real power, control is required for the phase angle between the output voltage and current. This is performed by first sensing the voltage signal and generating a unit synchronizing vector (performed by unit synchronizer 68 in Fig. 7), and then, for a lagging reactive power delay, the unit synchronizing vector is set between 0° and 90°.
  • PI proportional integral
  • the unit synchronizing vector is set between 180° and 270°. However, here, only unity power is selected, leading to the current reference error signal being further multiplied by the unit synchronizing vector to get the actual current reference (shown at 70 in Fig. 7). This is compared with the actual sensed signal (at 72 in Fig. 7) and this final error is minimized by PI controller 74.
  • PI controller 74 is responsible for system dynamic response and stability in loaded conditions, since it directly affects load current.
  • K p and Kt the open loop transfer function of the system is first written and then the gain and phase margin conditions are applied (indicated at 76 in Fig. 7).
  • the transfer function of the system is given by:
  • C t is the capacitance of the flying capacitor of the first module 78
  • C 2 is the capacitance of the flying capacitor of the second module 80
  • R is the load resistance
  • L is the load inductance
  • Fig. 8 illustrates a prior art 31 -level PUC 200.
  • the prior art 31-level PUC 200 includes three U-cells 202, 204, 206 connected across load 220. As shown, two additional flying capacitors must be added to the 7-level PUC in order to achieve 31-levels.
  • the present cascaded packed U-cell multilevel inverter 10 utilizes four capacitors, two DC links, two flying capacitors, and the total number of power switching devices is twelve.
  • 31-level PUC 200 has a control which is highly complex when compared to that of cascaded packed U-cell multilevel inverter 10.
  • 31-level PUC 200 requires four PI controllers and their tuning will be relatively difficult. If any of the four PI controllers does not function properly, it will be extremely difficult to debug the control system. Further, the switching frequency will necessarily be much higher than that of the present cascaded packed U-cell multilevel inverter 10.
  • Cascaded packed U-cell multilevel inverter 10 was simulated using Matlab/Simulink.
  • the first link voltage was 60 V
  • the second link voltage was 240 V
  • the first DC link capacitor value was 4700 ⁇ F
  • the second DC link capacitor value was 4700 ⁇ F
  • the first flying capacitor value was 2200 ⁇ F
  • the second flying capacitor value was 2200 ⁇ F
  • the load parameters were 100 ⁇ and 200 ⁇
  • the switching frequency was 2 KHz.
  • the simulation results are presented in Figs. 9A-9D and Figs. 10A-10D. Successful cascading can be clearly seen with a 31-level voltage output. It can be further seen that one unit is operating at a higher switching frequency than the other.
  • the low switching frequency inverter is supplied with a higher DC link voltage, i.e., four times higher than the high frequency switched inverter unit.
  • the flying capacitor voltages are seen to be perfectly balanced at one-third of their respective DC link voltages.
  • the output voltages are also shown for different DC link voltage ratios, including 1: 1, 1:2 and 1 :3.
  • the harmonic spectrum of the output 31 -level voltage is shown in Fig. 10A, which is clearly shown to be a clean waveform without any harmonic components.
  • the first link voltage was 16 V
  • the second link voltage was 64 V
  • the first flying capacitor voltage was 5.33 V
  • the second flying capacitor voltage was 21.33 V
  • the first flying capacitor value was 2.2 mF
  • the second flying capacitor value was 2.2 mF
  • the load parameters were 10 ⁇ and 25 mH
  • the switching frequency was 2 KHz.
  • the experimental results are shown in Figs. 11A-11F, Figs. 12A and 12B, and Figs.l3A-13D. It can be clearly seen that the output voltage formed by cascading of the two PUC units achieves the desired 31 levels.
  • the flying capacitor DC voltages are fixed at one-third of their respective DC link voltages.
  • the load voltage and currents are perfectly sinusoidal.
  • the individual outputs of the two PUCs are shown with a higher switching frequency, while the other is shown at a very low switching frequency.
  • the voltage across each pair of IGBT switches is also shown. It is clearly seen that the six pairs of power switches have different switching frequencies.
  • the spectrum of load voltage and load current shown in Figs. 12A and 12B shows a very low total harmonic distortion (THD) recorded for both voltage and current.
  • TDD total harmonic distortion
  • An experimental cascaded packed U-cell multilevel inverter according to the present invention was also constructed for a 49 level output; i.e., a DC link voltage ratio of 1:7.
  • the first link voltage was 15 V
  • the second link voltage was 105 V
  • the first flying capacitor voltage was 5.0 V
  • the second flying capacitor voltage was 35.0 V
  • the first flying capacitor value was 2.2 mF
  • the second flying capacitor value was 2.2 mF
  • the load parameters were 10 ⁇ and 0.78 mH
  • the switching frequency was 1 KHz.
  • the experimental results are shown in Figs. 14A-14G, Figs. 15 A and 15B, and Figs.l6A-16D.
  • the output voltage is formed by cascading of the two units to achieve the 49 level output.
  • the capacitor DC voltages are fixed at one-third of their respective DC link voltages.
  • the load voltage and currents are perfectly sinusoidal.
  • the individual outputs of the two PUCs can be seen to have a higher switching frequency, while the other is at a very low switching frequency.
  • the voltage across each pair of IGBTs is also shown.
  • the six pairs of power switches have different switching frequencies.
  • the inverter terminal voltage and grid/load voltage illustrated in Fig. 14G it can be seen that the overall load of the cascaded packed U-cell multilevel inverter is relatively small.
  • the spectra of the load voltage and the load current are shown in Figs. 15A and 15B, respectively. A very low THD was recorded for both voltage and current, as shown.
  • Fig. 15A shows the results of the harmonic analysis of the load current with only a 0.8% THD
  • Fig. 15B shows the results of the harmonic analysis of the terminal voltage at only 2.4% THD
  • Fig. 16A shows the output voltages for a DC link voltage ratio of 1:7.
  • Fig. 16B shows a magnified view of the output's positive cycle for the 49 level output.
  • Fig. 16C shows the output voltages for a DC link voltage ratio of 1 :6 (i.e., a 43 level output)
  • Fig. 16D shows the output voltages for a DC link voltage ratio of 1:5 (i.e., a 37 level output).

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

La présente invention concerne un onduleur multiniveau à cellules en U encapsulées en cascade (10) qui est un transformateur électrique pour transformer une électricité à courant continu (CC) en électricité à courant alternatif (CA) ayant une amplitude de tension variable et une sortie de fréquence variable. L'onduleur multiniveau à cellules en U encapsulées en cascade (10) comprend un premier onduleur multiniveau à cellules en U encapsulées (PUC) (12) et au moins un onduleur multiniveau à cellules en U encapsulées séquentiel (14) connecté en cascade au premier onduleur multiniveau à cellules en U encapsulées (12), c'est-à-dire que l'onduleur multiniveau à cellules en U encapsulées en cascade (10) est formé par agencement en cascade de deux ou plus de deux unités d'onduleur multiniveau PUC (12, 14). De préférence, chaque onduleur multiniveau PUC est un onduleur à 7 niveaux comprenant un condensateur à liaison CC adapté pour connexion à une source d'alimentation CC indépendante séparée (22, 24) et un condensateur volant calant l'onduleur multiniveau à un tiers de la tension de la source d'électricité correspondante.
PCT/US2017/020967 2016-03-04 2017-03-06 Onduleur multiniveau à cellules en u encapsulées en cascade Ceased WO2017152181A1 (fr)

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CN109546877A (zh) * 2018-12-02 2019-03-29 常州天曼智能科技有限公司 一种静止同步补偿装置
CN109510488A (zh) * 2018-12-07 2019-03-22 常州天曼智能科技有限公司 一种三相双向电能变换装置及其控制方法
CN109510488B (zh) * 2018-12-07 2021-11-09 常州天曼智能科技有限公司 一种三相双向电能变换装置及其控制方法
US11005388B2 (en) 2019-02-28 2021-05-11 sonnen, Inc. Single-phase multi-level asymmetric inverter with AC-bypass and asymmetric modulation strategy
WO2020176274A1 (fr) * 2019-02-28 2020-09-03 sonnen, Inc. Onduleur asymétrique multiniveau à phase unique comportant une stratégie de modulation asymétrique et de dérivation en courant alternatif
WO2021159219A1 (fr) * 2020-02-14 2021-08-19 Ecole De Technologie Superieure Convertisseur d'énergie électrique multi-niveau triphasé
WO2021208141A1 (fr) * 2020-04-16 2021-10-21 华为技术有限公司 Système d'alimentation électrique
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CN112994090A (zh) * 2021-02-23 2021-06-18 浙江大学 适合模块间功率不平衡的光伏中压级联型变换器控制方法
CN112994090B (zh) * 2021-02-23 2022-06-21 浙江大学 适合模块间功率不平衡的光伏中压级联型变换器控制方法
EP4140427B1 (fr) * 2021-08-26 2024-07-24 Olympus Winter & Ibe GmbH Générateur d'électrochirurgie pourvu d'inverseur à dynamique améliorée
EP4424257A3 (fr) * 2021-08-26 2024-11-06 Olympus Winter & Ibe GmbH Générateur d'électrochirurgie pourvu d'inverseur à dynamique améliorée

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