WO2017157271A1 - Onduleurs multiniveau - Google Patents

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Publication number
WO2017157271A1
WO2017157271A1 PCT/CN2017/076559 CN2017076559W WO2017157271A1 WO 2017157271 A1 WO2017157271 A1 WO 2017157271A1 CN 2017076559 W CN2017076559 W CN 2017076559W WO 2017157271 A1 WO2017157271 A1 WO 2017157271A1
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Prior art keywords
inverter
switched capacitor
switch
voltage
full bridge
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PCT/CN2017/076559
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English (en)
Inventor
Ka Wai Eric Cheng
Raghu Raman SEKHAR
Yuanmao YE
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Hong Kong Polytechnic University HKPU
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Hong Kong Polytechnic University HKPU
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Publication of WO2017157271A1 publication Critical patent/WO2017157271A1/fr
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels

Definitions

  • a multilevel inverter In particular, a multilevel inverter with a switched-capacitor inverter and a full bridge inverter may be provided.
  • High frequency AC power distribution systems with frequencies above utility frequency (50 Hz or 60 Hz) are traditionally referred to as high frequency AC (alternating current) power distribution systems.
  • High frequency AC power distribution systems find application for example in aerospace, telecommunication, lighting, computer power supply, micro-grids and auxiliary power supply units for automotive.
  • High frequency AC power distribution systems offer significant advantages over conventional direct current (DC) power distribution systems and low frequency alternating current power distribution systems.
  • DC direct current
  • multilevel inverter may include: a switched capacitor inverter configured to output a unipolar sequence of DC voltages; and a full bridge inverter configured to receive the unipolar sequence of DC voltages and to output a bipolar sequence of DC voltages.
  • the unipolar sequence may include or may be a periodic sequence.
  • the unipolar sequence may include or may be a rising sub-sequence and a falling sub-sequence.
  • the bipolar sequence may include or may be a periodic sequence.
  • the bipolar sequence may include or may be a rising sub-sequence and a falling sub-sequence.
  • the switched capacitor inverter may include or may be a charge pump. According to various embodiments, the switched capacitor inverter may be configured to be connected to a single voltage source. According to various embodiments, the switched capacitor inverter may be configured to be connected to a plurality of voltage sources.
  • the full bridge inverter may be configured to selectively pass through the DC voltages of the unipolar sequence or to negate the DC voltages of the unipolar sequence.
  • the switched capacitor inverter may be configured to be connected to a first voltage source and to a second voltage source.
  • the switched capacitor inverter may include a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a first diode, a second diode and a capacitor.
  • the first switched capacitor inverter switch may be connected to the second voltage source, the second diode, and the second switched capacitor inverter switch; the second switched capacitor inverter switch may be connected to the first switched capacitor inverter switch, the second diode, the capacitor, and the third switched capacitor inverter switch; the third switched capacitor inverter switch may be connected to the first voltage source, the second voltage source, the second switched capacitor inverter switch, the capacitor, and the full bridge inverter; the first diode may be connected to the first voltage source and the second diode; the second diode may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the first diode, and the capacitor; and the capacitor may be connected to the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first diode, the second diode, and the full bridge inverter.
  • the unipolar sequence may include or may be DC voltages of four different levels corresponding to a zero voltage, a voltage of the first voltage source, a voltage of the second voltage source, and a sum of the voltage of the first voltage source and the voltage of the second voltage source.
  • the bipolar sequence may include or may be DC voltages of seven different levels corresponding to a zero voltage, the voltage of the first voltage source, the voltage of the second voltage source, the sum of the voltage of the first voltage source and the voltage of the second voltage source, an inverted voltage of the first voltage source, an inverted voltage of the second voltage source, and an inverted sum of the voltage of the first voltage source and the voltage of the second voltage source.
  • the switched capacitor inverter may be configured to output a voltage of the first voltage source to the full bridge inverter if the third switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an off state.
  • the switched capacitor inverter may be configured to output a voltage of the second voltage source to the full bridge inverter if the first switched capacitor inverter switch is in an on state and the second switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state.
  • the switched capacitor inverter may be configured to output a voltage corresponding to a sum of the voltage of the first voltage source and the voltage of the second voltage source to the full bridge inverter if the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an on state and the third switched capacitor inverter switch is in an off state.
  • the switched capacitor inverter may include or may be a voltage increaser configured to selectively increase a voltage of at least one of the first voltage source or the second voltage source.
  • the switched capacitor inverter may include or may be a voltage doubler configured to selectively double a voltage of at least one of the first voltage source or the second voltage source.
  • the switched capacitor inverter may include or may be a voltage reducer configured to selectively reduce a voltage of at least one of the first voltage source or the second voltage source.
  • the switched capacitor inverter may include or may be a voltage reducer configured to selectively half a voltage of at least one of the first voltage source or the second voltage source.
  • the unipolar sequence may include or may be DC voltages of five different levels; and the bipolar sequence may include or may be DC voltages of nine different levels.
  • the switched capacitor inverter may be configured to be connected to at least three voltage sources; and the switched capacitor inverter may be configured to selectively output voltages corresponding to combinations of voltages of the three voltage sources to the full bridge inverter.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a relay.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a bipolar junction transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be an insulated-gate bipolar transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.
  • the switched capacitor inverter may be configured to be connected to a single voltage source; and the switched capacitor inverter may include or may be a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a fourth switched capacitor inverter switch, a first diode, a second diode, a first capacitor, and a second capacitor.
  • the first switched capacitor inverter switch may be connected to the voltage source, the first diode, the first capacitor, the second switched capacitor inverter switch, and the fourth switched capacitor inverter switch;
  • the second switched capacitor inverter switch may be connected to the voltage source, to the first switched capacitor inverter switch, to the first capacitor, to the fourth switched capacitor inverter switch, and to the full bridge inverter;
  • the third switched capacitor inverter switch may be connected to the fourth switched capacitor inverter switch, the first diode, the second diode, the first capacitor, and the second capacitor;
  • the fourth switched capacitor inverter switch may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first capacitor, and the second capacitor;
  • the first diode may be connected to the voltage source, the first switched capacitor inverter switch, the third switched capacitor inverter switch, and the second diode;
  • the second diode may be connected to the third switched capacitor inverter switch, the first di
  • the unipolar sequence may include or may be DC voltages of four different levels corresponding to a zero voltage, a voltage of the voltage source, a doubled voltage of the voltage source, and a tripled voltage of the voltage source; and the bipolar sequence may include or may be DC voltages of seven different levels corresponding to a zero voltage, a voltage of the voltage source, a doubled voltage of the voltage source, and a tripled voltage of the voltage source, an inverted voltage of the voltage source, an inverted doubled voltage of the voltage source, and an inverted tripled voltage of the voltage source.
  • the switched capacitor inverter may be configured to output a voltage of the voltage source to the full bridge inverter if the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an on state and the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state.
  • the switched capacitor inverter may be configured to output a doubled voltage of the voltage source to the full bridge inverter if the first switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch are in an off state.
  • the switched capacitor inverter may be configured to output a tripled voltage of the voltage source to the full bridge inverter if the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an on state and the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an off state.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a relay.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a bipolar junction transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be an insulated-gate bipolar transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.
  • the switched capacitor inverter may be configured to be connected to a single voltage source; and the switched capacitor inverter may include or may be a plurality of voltage increasers configured to selectively increase a voltage of the voltage source.
  • the switched capacitor inverter may be configured to be connected to a single voltage source; and the switched capacitor inverter may include or may be a plurality of voltage doublers configured to selectively double a voltage of the voltage source.
  • the switched capacitor inverter may be configured to be connected to a single voltage source; and the switched capacitor inverter may include or may be a plurality of voltage reducers configured to selectively reduce a voltage of the voltage source.
  • the switched capacitor inverter may be configured to be connected to a single voltage source; and the switched capacitor inverter may include or may be a plurality of voltage reducers configured to selectively half a voltage of the voltage source.
  • the full bridge inverter may include a first full bridge inverter switch, a second full bridge inverter switch, a third full bridge inverter switch, and a fourth full bridge inverter switch.
  • the first full bridge inverter switch may be connected to the switched capacitor inverter the second full bridge inverter switch, the fourth full bridge inverter switch, and an output of the full bridge inverter;
  • the second full bridge inverter switch may be connected to the switched capacitor inverter, the first full bridge inverter switch, the third full bridge inverter switch, and the output;
  • the third full bridge inverter switch may be connected to the switched capacitor inverter, the second full bridge inverter switch, the fourth full bridge inverter switch, and the output;
  • the fourth full bridge inverter switch may be connected to the switched capacitor inverter, the first full bridge inverter switch, the third full bridge inverter switch, and the output.
  • the full bridge inverter may be configured to output a voltage received from the switched capacitor inverter if the first full bridge inverter switch and the third full bridge inverter switch are in an on state and the second full bridge inverter switch and the fourth full bridge inverter switch are in an off state.
  • the full bridge inverter may be configured to invert a voltage received from the switched capacitor inverter and output the inverted voltage if the second full bridge inverter switch and the fourth full bridge inverter switch are in an on state and the first full bridge inverter switch and the third full bridge inverter switch are in an off state.
  • the full bridge inverter may be configured to output a zero voltage after having output a positive voltage with the first full bridge inverter switch in an on state and the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch in an off state.
  • a body diode associated with the second full bridge inverter switch may be configured to provide freewheeling.
  • the full bridge inverter may be configured to output a zero voltage after having output a negative voltage with the fourth full bridge inverter switch in an on state and the first full bridge inverter switch, the second full bridge inverter switch, and the third full bridge inverter switch in an off state.
  • a body diode associated with the fourth full bridge inverter switch may be configured to provide freewheeling.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a relay.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a transistor.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a bipolar junction transistor.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be an insulated-gate bipolar transistor.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.
  • Figure 1 shows a multilevel inverter in accordance with an embodiment of the invention.
  • Figure 2 shows a topology of a high frequency multilevel inverter according to various embodiments.
  • Figure 3A to Figure 3H show topological stages of a seven level switched-capacitor multilevel inverter according to various embodiments.
  • igure 4 shows a simulation model according to various embodiments.
  • Figure 5 shows a diagram illustrating a 50 kHz multilevel (seven) staircase output voltage of an inverter according to various embodiments.
  • FIG. 6 shows a nine level switched–capacitor based multilevel inverter (MLI) according to various embodiments.
  • Figure 7 shows a nine level switched–capacitor based MLI according to various embodiments.
  • FIG 8 shows an illustration of a generalized topology for a switched capacitor based multilevel inverter (SCMLI) according to various embodiments.
  • SCMLI switched capacitor based multilevel inverter
  • Figure 9 shows a topology of a high frequency multilevel inverter according to various embodiments.
  • Figure 10A to Figure 10H show illustrations of topological stages of a seven level switched–capacitor multilevel inverter according to various embodiments.
  • Figure 11 shows a simulation model according to various embodiments.
  • Figure 12 shows a diagram illustrating a 50 kHz multilevel (seven) staircase output voltage of an inverter according to various embodiments.
  • Figure 13A shows a nine level switched–capacitor based MLI according to various embodiments.
  • FIG. 13B and Figure 13C show higher level switched-capacitor multilevel inverters according to various embodiments.
  • HFAC PDS high frequency AC power distribution systems
  • HFAC PDS find application for example in aerospace, telecommunication, lighting, computer power supply, micro-grids and auxiliary power supply units for automotive.
  • HFAC PDS offer significant advantages over conventional direct current (DC) PDS and low frequency alternating current PDS.
  • An advantage of HFAC PDS over DC PDS is that HFAC PDS eliminate the need for a rectifier stage in the front end power supply system, and the need for an inverter in the point of load power supply.
  • this reduction in the number of power conversion stages translates to fewer components, higher efficacy/efficiency, lower cost and better reliability.
  • Multilevel inverters are used in the power industry owing to benefits they present. With MLIs, it is easier to produce a high power, high voltage AC output with a multilevel topology as the voltage stress on the individual device is controlled. Advantageously, it is furthermore possible to obtain higher voltages with low harmonics without employing transformers. The harmonic content may be mitigated by increasing the number of voltage levels in the AC output.
  • Multilevel inverters are generally classified into diode–clamped, flying–capacitors (also called capacitor–clamped) and cascaded types.
  • Popular PWM (pulse width modulation) strategies include space vector modulation, multilevel selective harmonic elimination and multilevel sinusoidal pulse width modulation.
  • Switched–capacitor converters have drawn attention due to their simplicity, low weight and low cost features. They employ switches and capacitors to achieve voltage conversion. Since they eliminate the need for bulky inductors, they are usually small in size and extremely lighter. These features allow switched–capacitor converters to be also fabricated into ICs (integrated circuits) .
  • a switched–capacitor converter (in other words: a switched-capacitor inverter) may be provided in a multilevel inverter to realize a circuitry that outputs a staircase high frequency AC waveform.
  • a switched–capacitor based front end DC level shifter may enable a system to obtain multiple voltage levels to realize a multilevel inverter.
  • an inverter which uses a reasonable number of capacitors, and can be operated without relying on PWM (pulse width modulation) , in contrast to commonly used inverters which use a high number of switches and which use complex PWM techniques.
  • PWM pulse width modulation
  • a topology of multilevel inverters for high frequency AC applications may be provided.
  • the multilevel inverters according to various embodiments may employ a switched–capacitor technique.
  • the multilevel inverters according to various embodiments may include an inverter front end including a switched–capacitor based DC (direct current) level shifter that produces multiple DC levels at the DC bus of the inverter.
  • the multilevel inverters according to various embodiments may further include a full bridge inverter which obtains different voltage levels at the output.
  • FIG. 1 shows a multilevel inverter 100 according to various embodiments.
  • the multilevel inverter 100 may include a switched capacitor inverter 102 configured to output a unipolar sequence of DC voltages.
  • the multilevel inverter 100 may further include a full bridge inverter 104 configured to receive the unipolar sequence of DC voltages and to output a bipolar sequence of DC voltages.
  • the switched capacitor inverter 102 and the full bridge inverter 104 may be connected, like illustrated by line 106, for example electrically connected.
  • the full bridge inverter 104 of the multilevel inverter 100 receives a sequence of DC voltages of a single polarity from the switched capacitor inverter 102, and generates a sequence of DC voltages of two different polarities based on (in other words: from) the received sequence of DC voltages of the single polarity.
  • the full bridge inverter 104 of the multilevel inverter 100 converts a sequence of DC voltages of a single polarity received from the switched capacitor inverter 102 into a sequence of DC voltages of two different polarities.
  • the unipolar sequence may include or may be a periodic sequence.
  • the unipolar sequence may include or may be a rising sub-sequence and a falling sub-sequence.
  • the unipolar sequence may include or may be DC voltages of a single pre-determined polarity.
  • the bipolar sequence may include or may be a periodic sequence.
  • the bipolar sequence may include or may be a rising sub-sequence and a falling sub-sequence.
  • the bipolar sequence may include or may be DC voltages of two different polarities.
  • the switched capacitor inverter 102 may include or may be a charge pump.
  • the switched capacitor inverter 102 may include a plurality of capacitors.
  • the switched capacitor inverter 102 may be free from inductors.
  • the unipolar sequence may be free from pulse width modulation signals.
  • the bipolar sequence may be free from pulse width modulation signals.
  • the switched capacitor inverter 102 may be configured to be connected to a single voltage source.
  • generating the multilevel voltages from a single voltage source reduces complexity of the input to the multilevel inverter
  • the switched capacitor inverter 102 may be configured to be connected to a plurality of voltage sources.
  • the full bridge inverter 104 may be configured to selectively pass through the DC voltages of the unipolar sequence or to negate the DC voltages of the unipolar sequence.
  • the switched capacitor inverter 102 may be configured to be connected to a first voltage source and to a second voltage source.
  • the switched capacitor inverter 102 may include a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a first diode, a second diode and a capacitor.
  • the first switched capacitor inverter switch may be connected to the second voltage source, the second diode, and the second switched capacitor inverter switch; the second switched capacitor inverter switch may be connected to the first switched capacitor inverter switch, the second diode, the capacitor, and the third switched capacitor inverter switch; the third switched capacitor inverter switch may be connected to the first voltage source, the second voltage source, the second switched capacitor inverter switch, the capacitor, and the full bridge inverter 104; the first diode may be connected to the first voltage source and the second diode; the second diode may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the first diode, and the capacitor; and the capacitor may be connected to the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first diode, the second diode, and the full bridge inverter 104.
  • the unipolar sequence may include or may be DC voltages of four different levels corresponding to a zero voltage, a voltage of the first voltage source, a voltage of the second voltage source, and a sum of the voltage of the first voltage source and the voltage of the second voltage source.
  • the bipolar sequence may include or may be DC voltages of seven different levels corresponding to a zero voltage, the voltage of the first voltage source, the voltage of the second voltage source, the sum of the voltage of the first voltage source and the voltage of the second voltage source, an inverted voltage of the first voltage source, an inverted voltage of the second voltage source, and an inverted sum of the voltage of the first voltage source and the voltage of the second voltage source.
  • the switched capacitor inverter 102 may be configured to output a voltage of the first voltage source to the full bridge inverter 104 if the third switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an off state.
  • the switched capacitor inverter 102 may be configured to output a voltage of the second voltage source to the full bridge inverter 104 if the first switched capacitor inverter switch is in an on state and the second switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state.
  • the switched capacitor inverter 102 may be configured to output a voltage corresponding to a sum of the voltage of the first voltage source and the voltage of the second voltage source to the full bridge inverter 104 if the first switched capacitor inverter switch and the second switched capacitor inverter switch are in an on state and the third switched capacitor inverter switch is in an off state.
  • the switched capacitor inverter 102 may include or may be a voltage increaser configured to selectively increase a voltage of at least one of the first voltage source or the second voltage source.
  • the switched capacitor inverter 102 may include or may be a voltage doubler configured to selectively double a voltage of at least one of the first voltage source or the second voltage source.
  • the switched capacitor inverter 102 may include or may be a voltage reducer configured to selectively reduce a voltage of at least one of the first voltage source or the second voltage source.
  • the switched capacitor inverter 102 may include or may be a voltage reducer configured to selectively half a voltage of at least one of the first voltage source or the second voltage source.
  • the unipolar sequence may include or may be DC voltages of five different levels; and the bipolar sequence may include or may be DC voltages of nine different levels.
  • the switched capacitor inverter 102 may be configured to be connected to at least three voltage sources; and the switched capacitor inverter 102 may be configured to selectively output voltages corresponding to combinations of voltages of the three voltage sources to the full bridge inverter 104.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a relay.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a bipolar junction transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be an insulated-gate bipolar transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.
  • the switched capacitor inverter 102 may be configured to be connected to a single voltage source; and the switched capacitor inverter 102 may include or may be a first switched capacitor inverter switch, a second switched capacitor inverter switch, a third switched capacitor inverter switch, a fourth switched capacitor inverter switch, a first diode, a second diode, a first capacitor, and a second capacitor.
  • the first switched capacitor inverter switch may be connected to the voltage source, the first diode, the first capacitor, the second switched capacitor inverter switch, and the fourth switched capacitor inverter switch;
  • the second switched capacitor inverter switch may be connected to the voltage source, to the first switched capacitor inverter switch, to the first capacitor, to the fourth switched capacitor inverter switch, and to the full bridge inverter 104;
  • the third switched capacitor inverter switch may be connected to the fourth switched capacitor inverter switch, the first diode, the second diode, the first capacitor, and the second capacitor;
  • the fourth switched capacitor inverter switch may be connected to the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, the first capacitor, and the second capacitor;
  • the first diode may be connected to the voltage source, the first switched capacitor inverter switch, the third switched capacitor inverter switch, and the second diode;
  • the second diode may be connected to the third switched capacitor inverter switch, the
  • the unipolar sequence may include or may be DC voltages of four different levels corresponding to a zero voltage, a voltage of the voltage source, a doubled voltage of the voltage source, and a tripled voltage of the voltage source; and the bipolar sequence may include or may be DC voltages of seven different levels corresponding to a zero voltage, a voltage of the voltage source, a doubled voltage of the voltage source, and a tripled voltage of the voltage source, an inverted voltage of the voltage source, an inverted doubled voltage of the voltage source, and an inverted tripled voltage of the voltage source.
  • the switched capacitor inverter 102 may be configured to output a voltage of the voltage source to the full bridge inverter 104 if the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an on state and the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an off state.
  • the switched capacitor inverter 102 may be configured to output a doubled voltage of the voltage source to the full bridge inverter 104 if the first switched capacitor inverter switch is in an on state and the first switched capacitor inverter switch, the second switched capacitor inverter switch, and the third switched capacitor inverter switch are in an off state.
  • the switched capacitor inverter 102 may be configured to output a tripled voltage of the voltage source to the full bridge inverter 104 if the first switched capacitor inverter switch and the third switched capacitor inverter switch are in an on state and the second switched capacitor inverter switch and the fourth switched capacitor inverter switch are in an off state.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a relay.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a bipolar junction transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be an insulated-gate bipolar transistor.
  • one or more (for example all) of the first switched capacitor inverter switch, the second switched capacitor inverter switch, the third switched capacitor inverter switch, and the fourth switched capacitor inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.
  • the switched capacitor inverter 102 may be configured to be connected to a single voltage source; and the switched capacitor inverter 102 may include or may be a plurality of voltage increasers configured to selectively increase a voltage of the voltage source.
  • the switched capacitor inverter 102 may be configured to be connected to a single voltage source; and the switched capacitor inverter 102 may include or may be a plurality of voltage doublers configured to selectively double a voltage of the voltage source.
  • the switched capacitor inverter 102 may be configured to be connected to a single voltage source; and the switched capacitor inverter 102 may include or may be a plurality of voltage reducers configured to selectively reduce a voltage of the voltage source.
  • the switched capacitor inverter 102 may be configured to be connected to a single voltage source; and the switched capacitor inverter 102 may include or may be a plurality of voltage reducers configured to selectively half a voltage of the voltage source.
  • the full bridge inverter 104 may include a first full bridge inverter switch, a second full bridge inverter switch, a third full bridge inverter switch, and a fourth full bridge inverter switch.
  • the first full bridge inverter switch may be connected to the switched capacitor inverter 102, the second full bridge inverter switch, the fourth full bridge inverter switch, and an output of the full bridge inverter;
  • the second full bridge inverter switch may be connected to the switched capacitor inverter 102, the first full bridge inverter switch, the third full bridge inverter switch, and the output;
  • the third full bridge inverter switch may be connected to the switched capacitor inverter 102, the second full bridge inverter switch, the fourth full bridge inverter switch, and the output;
  • the fourth full bridge inverter switch may be connected to the switched capacitor inverter 102, the first full bridge inverter switch, the third full bridge inverter switch, and the output.
  • the full bridge inverter 104 may be configured to output a voltage received from the switched capacitor inverter 102 if the first full bridge inverter switch and the third full bridge inverter switch are in an on state and the second full bridge inverter switch and the fourth full bridge inverter switch are in an off state.
  • the full bridge inverter 104 may be configured to invert a voltage received from the switched capacitor inverter 102 and output the inverted voltage if the second full bridge inverter switch and the fourth full bridge inverter switch are in an on state and the first full bridge inverter switch and the third full bridge inverter switch are in an off state.
  • the full bridge inverter 104 may be configured to output a zero voltage after having output a positive voltage with the first full bridge inverter switch in an on state and the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch in an off state.
  • a body diode associated with the second full bridge inverter switch may be configured to provide freewheeling.
  • the full bridge inverter 104 may be configured to output a zero voltage after having output a negative voltage with the fourth full bridge inverter switch in an on state and the first full bridge inverter switch, the second full bridge inverter switch, and the third full bridge inverter switch in an off state.
  • a body diode associated with the fourth full bridge inverter switch may be configured to provide freewheeling.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a relay.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a transistor.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a bipolar junction transistor.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be an insulated-gate bipolar transistor.
  • one or more (for example all) of the first full bridge inverter switch, the second full bridge inverter switch, the third full bridge inverter switch, and the fourth full bridge inverter switch may include or may be a metal–oxide–semiconductor field-effect transistor.
  • a switched capacitor based multilevel inverter for high frequency AC power distribution systems may be provided.
  • a dual input switched capacitor based multilevel inverter for high frequency AC power distribution systems may be provided.
  • a front end DC level shifter with two (voltage) sources, three transistors, two diodes and a capacitor may be provided.
  • providing to voltage sources reduces complexity of the circuit of the multilevel inverter.
  • a front end DC level shifter with a single voltage source, four transistors, two diodes and two capacitors may be provided.
  • a family of circuits may be provided.
  • Each circuit of the family of circuits may use a low (for example a minimum) number of switches to obtain multiple DC voltage levels.
  • a multilevel inverter (or a topology of multilevel inverters) , for example a multilevel inverter circuit, for high frequency AC applications may employ a switched–capacitor technique.
  • the inverter front end may include a switched–capacitor based DC to DC converter (for example a DC level shifter) that produces multiple DC levels at the DC bus of the inverter.
  • a full bridge inverter may receive the multiple DC levels and may obtain different voltage levels at the output.
  • a multilevel inverter (which may use a plurality of DC input sources, or which may use a single DC input source and) may output for example a seven level (for example three positive levels, three negative levels and a zero level) staircase voltage waveform.
  • a switched–capacitor technique Utilizing a switched–capacitor technique according to various embodiments, the need to use heavy magnetic components, which may also occupy large space, may be eliminated.
  • an inverter according to various embodiments may be lighter, may be smaller in size and/or may be cheaper.
  • a multilevel inverter may include a front end multi-level generator, which is realized by a switched-capacitor DC level shifter, and an H-bridge converter.
  • the front end switched–capacitor converter may be configured to produce multiple DC levels at the DC bus of the inverter.
  • the front end converter may employ two voltage sources, two diodes, three transistors and one capacitor for voltage conversion.
  • FIG. 2 shows an illustration 200 of a high frequency multilevel inverter (HF MLI) according to various embodiments, which may output a seven level staircase voltage waveform (three positive, zero and three negative) .
  • the HF MLI may include two cascaded stages: a switched capacitor based front end DC level shifter 202 and a full bridge inverter 204.
  • the front end switched capacitor DC level shifter 202 may include (or employ) three (switched capacitor inverter) switches (for example MOSFETs) : a first switch S 1 214, a second switch S 2 216 and a third switch S 3 220.
  • the front end switched capacitor DC level shifter 202 may furthermore include two diodes: a first diode D 1 208 and a second diode D 2 210.
  • the front end switched capacitor DC level shifter 202 may furthermore include two voltage sources: a first voltage source V IN1 206 and a second voltage source V IN2 218.
  • the front end switched capacitor DC level shifter 202 may furthermore include a capacitor C 212.
  • the different DC levels obtained at the V DCbus 230 include V IN1 , V IN2 and V IN1 + V IN2 .
  • the full bridge inverter 204 employs four MOSFETs Q 1 222, Q 2 224, Q 3 226 and Q 4 228.
  • Full bridge inverter operation effectively produces seven levels, i.e., 0, ⁇ V IN1 , ⁇ V IN2 and ⁇ (V IN1 + V IN2 ) , which for example are available to a load 232.
  • the size of the capacitor 212 is large enough for the voltage ripple to be negligible, and that the switching devices (the MOSFETS 214, 216, 220, 222, 224, 226, and 228, and the diodes 208, 210) and the input voltage sources 206, 218 are ideal.
  • the working states will be explained in more detail with reference to Figure 3A to Figure 3H.
  • the capacitor C 212 is charged to V IN1 206 through the first diode D 1 208 and by turning ON S 3 220, while S 1 214 and S 2 216 remain turned OFF, in the front end DC level shifter 202.
  • V IN2 > V IN1 may be provided for normal operation, i.e., to produce a seven level staircase output.
  • V IN2 218 is directly connected to the V DCbus 230.
  • Q 1 222 and Q 3 226 are turned ON, while Q 2 224 and Q 4 228 remain turned OFF.
  • Q 2 224 and Q 4 228 are turned ON, while Q 1 222 and Q 3 226 remain turned OFF.
  • Voltage across the capacitor C 212 still remains at V IN1 .
  • S 1 214 and S 2 216 are turned ON, while S 3 220 remains turned OFF, D 1 208 and D 2 210 are reverse biased. Under this condition, the capacitor C 212 is connected in series to V IN2 218.
  • Figure 3G shows an equivalent circuit 312 of the multilevel inverter according to various embodiments for generating a zero level after a positive half cycle.
  • Figure 3H shows an equivalent circuit 316 of the multilevel inverter according to various embodiments for generating a zero level after a negative half cycle.
  • Table 1 shows a summary of the working states logic as described with reference to Figure 3A to Figure 3H for the multilevel inverter according to various embodiments.
  • the H-bridge converter (which may include or may consist of four transistors) may provide a bipolar waveform from a unipolar waveform at the DC bus.
  • Figures 3A to 3H and Table 1 explain in detail and show the seven levels, i.e., 0, ⁇ VIN1, ⁇ VIN2 and ⁇ (VIN1 + VIN2) .
  • Q1 and Q3 a positive cycle of AC is obtained at the output.
  • Q2 and Q4 a negative cycle of AC is obtained at the output.
  • Figure 4 shows an illustration 400 of a simulation model of a multilevel inverter (for example the multilevel inverter 200 of Figure 2) according to various embodiments.
  • a circuitry 402 for controlling the switches may be provided.
  • Figure 5 shows an illustration 500 of an output of the inverter (for example of the simulation model of Figure 4) , for example a 50 kHz multilevel (for example seven-level) staircase output voltage) .
  • Figure 6 shows a nine level inverter 600 according to various embodiments, and based on the seven level circuit of Figure 2, so that the same reference signs may be used, and some reference signs may be omitted for ease of readability of Figure 6.
  • the nine level inverter 600 may employ a voltage doubler 604 (for double the voltage V IN1 of the voltage source 206) as one of the voltage inputs to the front end DC level shifter 602. Therefore, the inverter 600 may output ⁇ V IN1 , ⁇ 2V IN1 ⁇ V IN2 and ⁇ (V IN1 + V IN2 ) .
  • the voltage double 604 may include switches S 1 610 and S 2 612, a diode 606, and a capacitor 608.
  • Figure 7 shows a nine level inverter 700 according to various embodiments, and based on the seven level circuit of Figure 2, so that the same reference signs may be used, and some reference signs may be omitted for ease of readability of Figure 7.
  • the nine level inverter 700 may employ a circuit 704 which reduces the input voltage V IN1 of the voltage source 206 by half as one of the voltage inputs to the front end DC level shifter 702. This enables the inverter 700 to output ⁇ (V IN1 /2) , ⁇ V IN1 , ⁇ V IN2 and ⁇ (V IN1 /2 + V IN2 ) .
  • the circuit 704 may include switches S 1 712 and S 2 714, a capacitor C 706, and diodes D 1 708 and D 2 710.
  • FIG 8 shows an illustration 800 of a switched–capacitor based multilevel inverter (SCMLI) according to various embodiments.
  • the switched–capacitor based multilevel inverter may be based on the seven level circuit of Figure 2, so that the same reference signs may be used, and some reference signs may be omitted for ease of readability of Figure 8.
  • the dotted lines 804 illustrate portions where further circuit elements may be provided for a higher level inverter based on a basic cell 812 of the switched-capacitor based front end DC level shifter 802 (in which the basic cell 812 (in other words: single unit) corresponds to the switched capacitor based front end DC level shifter 202 of the seven level circuit 200 of Figure 2) .
  • Table 2 shows a switching logic for the generalized topology of the SCMLI.
  • a multilevel converter may be provided with a front end converter which include one voltage sources, two diodes, four transistors and two capacitors for voltage conversion.
  • FIG 9 shows a high frequency multilevel inverter (HF MLI) 900 according to various embodiments.
  • the high frequency multilevel inverter (HF MLI) 900 may output a seven level staircase voltage waveform (for example three positive, one zero and three negative voltages) .
  • the high frequency multilevel inverter (HF MLI) 900 may include (or consist of) two cascaded stages: a switched capacitor based front end DC to DC converter 902 and a full bridge inverter 904.
  • the switched capacitor based front end DC to DC converter 902 may be a front end switched capacitor DC level shifter, and may include four (switched-capacitor) switches (a first switch G 1 916, a second switch G 2 918, a third switch G 3 920 and fourth switch G 4 922) , which may for example be MOSFETs, two diodes (a first diode D 1 908 and a second diode D 2 910) , a voltage sources V IN 906, and two capacitors (a first capacitor C 1 910 and a second capacitor C 2 914) .
  • the different DC levels obtained at the V DCbus 924 may include V IN , 2V IN and 3V IN .
  • the full bridge inverter 904 may include switches S 1 926, S 2 928, S 3 930, S 4 932, and may produce seven levels of voltages V 0 , for example, 0, ⁇ V IN , ⁇ 2V IN and ⁇ 3V IN , which for example may be output or provided to a load 934.
  • V 0 for example, 0, ⁇ V IN , ⁇ 2V IN and ⁇ 3V IN
  • the size of the capacitors 912, 914 is large enough for the voltage ripple to be negligible, and that the switching devices 916, 918, 920, 922, 926, 928, 930, 932 and the input voltage sources 906 are ideal.
  • the working states of the HF MLI 900 will be described in more detail with reference to Figure 10A to Figure 10H.
  • the numbering of the switches S i in other words: the index i in the switch name S i ) in the full bridge inverter 904 shown in Figure 9 may be different from the numbering of the switches Q i in the full bridge inverter 204 shown in Figure 2; for example, while the first (full bridge inverter) switch is Q 1 in Figure 2 and S 1 in Figure 9 (i.e. same index 1) , the second (full bridge inverter) switch is Q 2 in Figure 2 and S 3 in Figure 9 (i.e. different indexes 2 and 3, respectively) ; likewise, the third (full bridge inverter) switch is Q 3 in Figure 2 and S 4 in Figure 9; and the fourth (full bridge inverter) switch is Q 4 in Figure 2 and S 2 in Figure 9.
  • the first (full bridge inverter) switch is Q 1 in Figure 2 and S 1 in Figure 9 (i.e. same index 1)
  • the second (full bridge inverter) switch is Q 2 in Figure 2 and S 3 in Figure 9 (i.
  • the capacitor C 1 912 and C 2 914 may be charged to V IN through the diodes D 1 908 and D 2 910, respectively, by turning ON the switches G 2 918 and G 4 922, while the switches G 1 918 and G 3 920 remain turned OFF, in the front end DC level shifter 902.
  • switches S 1 926 and S 4 932 may be turned ON, while switches S 2 928 and S 3 930 remain turned OFF.
  • switches S 2 928 and S 3 930 may be turned ON, while switches S 1 926 and S 4 r932 remain turned OFF.
  • switches S 1 926 and S 4 932 may be are turned ON, while switches S 2 928 and S 3 930 remain turned OFF.
  • switches S 2 928 and S 3 930 are turned ON, while switches S 1 926 and S 4 932 remain turned OFF.
  • the voltage across both capacitors 912, 914 may remain at V IN .
  • diodes D 1 908 and D 2 910 may be reverse biased. Under this condition, both the capacitors 912, 914 are connected in series to V IN 906.
  • Figure 10G shows an equivalent circuit 1012 of the multilevel inverter according to various embodiments for generating the zero level after a positive half cycle.
  • Figure 10H shows an equivalent circuit 1016 of the multilevel inverter according to various embodiments for generating the zero level after a negative half cycle.
  • Table 3 shows a summary of the working states logic for the multilevel inverter like described with reference to Figure 10A to Figure 10H above.
  • the voltage levels at the DC bus 924 of the inverter 902 may include V IN , 2V IN and 3V IN .
  • V IN the voltage levels at the DC bus 924 of the inverter 902
  • FIG. 10A to 10H and Table 3 turning on different transistors 916, 918, 920, 922 at different instants may provide obtaining the mentioned DC levels.
  • turning ON only G 1 916 and G 2 918 may provide 3V IN at the DC bus 924.
  • Turning ON only G 1 916 may provide 2V IN at the DC bus 924.
  • Turning ON only G 2 918 and G 4 922 provides V IN at the DC bus 924.
  • FIG. 10A to Figure 10H above describe in more detail how seven levels, i.e., 0, ⁇ V IN1 , ⁇ 2V IN and ⁇ 3V IN ., are obtained.
  • a positive cycle of AC for example a sequence of piecewise DC voltages
  • a negative cycle of AC may be obtained at the output 934.
  • Figure 11 shows an illustration 1100 of a simulation model of a multilevel inverter (for example the multilevel inverter 900 of Figure 9) according to various embodiments.
  • a circuitry 1102 for controlling the switches may be provided.
  • Figure 12 shows an illustration 1200 of the states of the switches of the multilevel inverter 900 of Figure 9 (wherein for example Vs1 indicates the state of the switch S 1 926, wherein a higher value (i.e. a line closer to the top of the diagram) indicates an ‘on’s tate, and a lower value (i.e. a line closer to the bottom of the diagram) indicates an ‘off’s tate) in a sub-diagram 1202, and the resulting voltage V 0 in a sub-diagram 1204.
  • Vs1 indicates the state of the switch S 1 926, wherein a higher value (i.e. a line closer to the top of the diagram) indicates an ‘on’s tate, and a lower value (i.e. a line closer to the bottom of the diagram) indicates an ‘off’s tate) in a sub-diagram 1202, and the resulting voltage V 0 in a sub-diagram 1204.
  • Figure 13A shows a nine level inverter 1300, which is based on the five level inverter shown in Figure 9 (including the switched capacitor inverter 902 and the full bridge inverter 904) , with additional two switches 1308, 1310 (for example transistors) , an additional diode 1304, and an additional capacitor 1306.
  • the additional two switches 1308, 1310, the additional diode 1304, and the additional capacitor 1306 may form a (further) voltage doubler 1302, so that the following voltages may be provided to the load 934: 0, ⁇ V IN , ⁇ 2V IN , ⁇ 3V IN ., and ⁇ 4V IN . (in other words: -4V IN , -3V IN , -2V IN ., -V IN , 0, V IN , 2V IN , 3V IN ., and 4V IN ) .
  • Figure 13B shows a multilevel inverter 1310, which includes a plurality of voltage doublers 1302. Like indicated by lines 1312, further voltage doublers may be added.
  • Figure 13C shows a multilevel inverter 1314. Like indicated by lines 1316, further voltage doublers may be added.
  • one or more voltage sources may or may not be a part of the front end DC level shifter.
  • the front end DC level shifter may include one or more voltage sources.
  • the front end DC level shifter may be connected to one or more voltage sources.
  • the multilevel inverters may be configured to provide either a high frequency AC output, for example 400 Hz, or 50 kHz, or a low frequency AC output, for example 50 Hz or 60 Hz.
  • a lower number of switches (for example compared to commonly used inverters) may be used.
  • different topologies may be provided based on a basic topology (for example based on one of the topologies described above) .
  • a small capacitor size may be sufficient for high frequency applications (or high frequency operation) .
  • an intelligent placement of switches may be provided.
  • a modular design may be provided which may ensure extension of the topologies (for example extension to a higher number of voltage levels in the multilevel output) .
  • Various embodiments may solve (in other words: overcome; in other words: eliminate) the need to use excessive devices, power sources and passive components.
  • Various embodiments may eliminate the need to employ bulky inductors.
  • Various embodiments may provide a multilevel output which may reduce harmonic content.
  • Various embodiments may be applied in aerospace industry, telecommunications industry, lighting industry, and automotive industry.
  • a switched capacitor inverter switch is a switch
  • a full bridge inverter switch is a switch
  • the terms ‘switched capacitor inverter’ switch and ‘full bridge inverter’ switch are merely used to describe where the respective switch is provided, without necessarily requiring any specific property of the switch.
  • V may refer to a voltage source as a circuit element, and at the same time, ‘V’ may refer to the voltage that the voltage source ‘V’ provides.
  • a switch may be illustrated in the drawings as a transistor and a diode, and may be provided as a transistor and a diode accordingly.
  • transistors provided in the multilevel inverter may be any controllable switch, such as bipolar junction transistor, IGBT (Insulated-gate bipolar transistor) , MOSFET (metal–oxide–semiconductor field-effect transistor) or a relay.
  • bipolar junction transistor IGBT (Insulated-gate bipolar transistor)
  • MOSFET metal–oxide–semiconductor field-effect transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention concerne un onduleur multiniveau. L'onduleur multiniveau peut comprendre : un onduleur à condensateur commuté conçu pour délivrer une séquence unipolaire de tensions continues ; et un onduleur en pont complet conçu pour recevoir la séquence unipolaire de tensions continues et pour délivrer une séquence bipolaire de tensions continues.
PCT/CN2017/076559 2016-03-14 2017-03-14 Onduleurs multiniveau Ceased WO2017157271A1 (fr)

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CN111682790A (zh) * 2020-05-30 2020-09-18 郑州大学 一种双输入扩展增益多电平逆变器及其控制方法
CN111740627A (zh) * 2020-05-30 2020-10-02 郑州大学 非桥式多电平变换装置及其控制方法
CN111740626A (zh) * 2020-05-30 2020-10-02 郑州大学 X型模块化扩展多电平变换器及其控制方法
CN111740628A (zh) * 2020-05-30 2020-10-02 郑州大学 分布式发电多电平变换器及其调制方法
CN113258814A (zh) * 2021-06-11 2021-08-13 郑州大学 一种高增益低应力光伏多电平逆变器及控制方法
CN113381632A (zh) * 2021-05-31 2021-09-10 郑州大学 一种非桥式模块化逆变器及其控制方法
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CN116111870A (zh) * 2023-03-07 2023-05-12 南京邮电大学 共地型的十开关倍压五电平单相光伏逆变器的控制方法
CN119483320A (zh) * 2025-01-16 2025-02-18 南京理工大学 一种可减小容值的共地型开关电容多电平逆变器
CN119765963A (zh) * 2024-12-09 2025-04-04 南京理工大学 一种基于开关电容的七电平逆变器

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US11336203B2 (en) 2018-09-07 2022-05-17 Socovar S.E.C. Multilevel electric power converter
CN109194170A (zh) * 2018-09-28 2019-01-11 华东交通大学 一种采用开关电容电路的七电平逆变器
CN111682790B (zh) * 2020-05-30 2022-07-26 郑州大学 一种双输入扩展增益多电平逆变器及其控制方法
CN111740626A (zh) * 2020-05-30 2020-10-02 郑州大学 X型模块化扩展多电平变换器及其控制方法
CN111740628A (zh) * 2020-05-30 2020-10-02 郑州大学 分布式发电多电平变换器及其调制方法
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CN111740627B (zh) * 2020-05-30 2022-07-05 郑州大学 非桥式多电平变换装置及其控制方法
CN111682790A (zh) * 2020-05-30 2020-09-18 郑州大学 一种双输入扩展增益多电平逆变器及其控制方法
CN111740626B (zh) * 2020-05-30 2023-03-24 郑州大学 X型模块化扩展多电平变换器及其控制方法
CN113381632A (zh) * 2021-05-31 2021-09-10 郑州大学 一种非桥式模块化逆变器及其控制方法
CN113258814A (zh) * 2021-06-11 2021-08-13 郑州大学 一种高增益低应力光伏多电平逆变器及控制方法
CN116094359A (zh) * 2023-03-07 2023-05-09 南京邮电大学 一种共地型的十开关倍压五电平单相光伏逆变器拓扑
CN116111870A (zh) * 2023-03-07 2023-05-12 南京邮电大学 共地型的十开关倍压五电平单相光伏逆变器的控制方法
CN119765963A (zh) * 2024-12-09 2025-04-04 南京理工大学 一种基于开关电容的七电平逆变器
CN119483320A (zh) * 2025-01-16 2025-02-18 南京理工大学 一种可减小容值的共地型开关电容多电平逆变器

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