WO2017203535A1 - Égaliseur dynamique de stockage de coefficients - Google Patents

Égaliseur dynamique de stockage de coefficients Download PDF

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Publication number
WO2017203535A1
WO2017203535A1 PCT/IN2016/050153 IN2016050153W WO2017203535A1 WO 2017203535 A1 WO2017203535 A1 WO 2017203535A1 IN 2016050153 W IN2016050153 W IN 2016050153W WO 2017203535 A1 WO2017203535 A1 WO 2017203535A1
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Prior art keywords
equalizer
combining
weight prediction
signal
desired signal
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English (en)
Inventor
Lakshmi Mohan SARIPALLI
Balaji VENKATACHALAM
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Thotaka Tekhnologies India Private Ltd
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Thotaka Tekhnologies India Private Ltd
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/0335—Arrangements for removing intersymbol interference characterised by the type of transmission
    • H04L2025/03356—Baseband transmission
    • H04L2025/03363—Multilevel
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/0335—Arrangements for removing intersymbol interference characterised by the type of transmission
    • H04L2025/03426—Arrangements for removing intersymbol interference characterised by the type of transmission transmission using multiple-input and multiple-output channels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03592—Adaptation methods
    • H04L2025/03598—Algorithms
    • H04L2025/03611—Iterative algorithms
    • H04L2025/03636—Algorithms using least mean square [LMS]

Definitions

  • This invention relates to telecommunication systems, Multiple Input Multiple Output (MIMO) in particular that can align and equalize the multipath signals thereby reducing the effects of ISI induced due to increased data rates during the transmission.
  • MIMO Multiple Input Multiple Output
  • the conventional telecommunication systems involving Multiple Input Multiple Output (MIMO) arrangements require the installation of several antennas for transmitting and receiving the signals in order to obtain the final output signal with better Signal-to-Noise (S/N) ratio.
  • the multiple signals are associated with varying time delay in the path which creates the need for a system which can align and equalize the multipath signals to avoid the loss of data caused by intensity attenuation of the input stream.
  • the bulk data contained in the multiple input waves can be subjected to Inter-Symbol Interference (ISI) due to the overlapping of the symbols included in the signal data with each other that gives rise to distortion patterns.
  • ISI Inter-Symbol Interference
  • Dual equalizing units can resolve the above-stated issues by performing the equalization operations before and after the combination of multipath input data.
  • the Pre-Combining Equalizer ensures that the effects of the Inter-Symbol Interference (ISI) and multipath dispersion are minimal whereas the Post- Combining equalizer will reduce the net errors after the combination process.
  • MIMO Multiple Input Multiple Output
  • the systems involving Multiple Input Multiple Output (MIMO), related to the telecommunication devices require various arrangements for processing the multiple input signals so as to render the final output to be free of errors that may have been induced due to the phenomenon such as multipath fading, Inter-symbol Interference, multipath dispersion, degraded Carrier-to-Noise Ratio.
  • the arrangement includes units that deal with aligning, equalization and combination steps for processing these multipath signals.
  • US 3633107 A titled “Adaptive signal processor for diversity radio receivers” discloses "a signal processor in a diversity receiver for the digital data transmitted over dispersive and fading radio channels performs the functions of demodulation, diversity signal combining, delay equalization, multipath distortion equalization and timing jitter elimination. Transversal equalizers, one in each diversity channel, are made adaptive to a common, time-varying mean-square error signal derived from the combined post detection output data.'YSzc US Publication No. US 3633107 A).
  • US 3879664 A titled “High speed digital communication receiver” discloses "a high speed digital communications receiver used in a diversity receiver system in which the pre-detection combiner of the receiver operates on a forward adaptive filter equalizer, having multiple weighting sections, in each of the diversity channels to process each received bandpass diversity signals prior to demodulation.
  • the combined weighted output signal from the pre-detection combiner is then demodulated and the data therein appropriately reconstructed and an error signal is generated.
  • the error signal thus obtained is modulated and restricted for use in an adaptive control circuitry which provides appropriate adaptive weighting signals for use in the processing of the received diversity signals at each of the forward filter equalizers.
  • the un-modulated error signal is applied in a backward adaptation control circuit for providing appropriate adaptive weighting signals for use in a single backward filter equalizer which suitably processes the reconstructed data to form a cancellation signal which is used to eliminate inter-symbol interference and source correlation effects in the demodulated combined weighted output signal.
  • a novel adaptive timing system is disclosed which permits the receiver clock to follow transmitter clock variations. Further, a novel automatic gain control system at the input IF receiver amplifiers are used to reduce the dynamic range requirements of the forward filter weight components.” (Sic US Publication No. US 3879664 A ).
  • the Troposcatter Modem Receiver includes a combiner, demodulator, baseband filter, a complex coefficient forward equalizer, a detector and a feedback circuit.
  • the combiner is a linear maximal-ratio combiner and receives a plurality of input signals at an intermediate frequency and generates a combined output signal for presentation to the demodulator.
  • the demodulator produces a demodulated signal which is filtered by the baseband filter prior to being presented to a first input of the equalizer.
  • the output of the equalizer is forwarded to the detector which produces an output signal.
  • the signal is fed back by way of the feedback circuit to a second input of the equalizer to modify the output signal.
  • US 5068873A titled “Equalizer” discloses "An adaptive equalizer comprising a computer unit which receives a known signals sequence to estimate transmission channel characteristics and effect compensatory control of tap coefficients by use of a first algorithm that has fast convergence property, and a tap coefficient computing unit for making compensation for relatively slow changes in a random data input after the compensation for the transmission channel characteristics, which either employs an algorithm that involves a relatively low computational complexity or intermittently executes computation.” (Sic US Publication No. US 5068873 A).
  • US 5175747 A titled “Equalizer” discloses "an adaptive equalizer comprising a computing unit which receives a known signal sequence to estimate transmission channel characteristics and effect compensatory control of tap coefficients by use of a first algorithm that has fast convergence property, and a tap coefficient computing unit for making compensation for relatively slow changes in a random data input after the compensation for the transmission channel characteristics, which either employs an algorithm that involves a relatively low computational complexity or intermittently executes computation which contains an interpolation of consecutive sets of tap coefficients between intermittent intervals.
  • an adaptive equalizer comprising a computing unit which receives a known signal sequence to estimate transmission channel characteristics and effect compensatory control of tap coefficients by use of a first algorithm that has fast convergence property, and a tap coefficient computing unit for making compensation for relatively slow changes in a random data input after the compensation for the transmission channel characteristics, which either employs an algorithm that involves a relatively low computational complexity or intermittently executes computation which contains an interpolation of consecutive sets of tap coefficients between intermittent intervals.
  • US 6590933 Bl titled “Adaptive decision-feedback equalizer with error- predictor for improved convergence” discloses "a method for use in data communications equipment for improving convergence of a hybrid decision feedback apparatus including an adaptive feed-forward equalizer and an adaptive decision feedback equalizer. An independent error predictor component is used for better convergence and then is eliminated by converting, using z- transformations, the adaptive feed-forward equalizer and adaptive decision feedback equalizer to an equivalent feed forward equalizer and an equivalent decision feedback equalizer, respectively, in which the error predictor is embedded or incorporated therein. The smaller system with a reduced number of FFE-DFE coefficients has a faster convergence rate. "(Sic US Publication No. US 6590933 Bl).
  • the above stated prior arts employ various techniques to improvise the carrier-to- noise ratio (CNR)/signal-to noise ratio (SNR) mainly involved in the Multiple- Input Multiple- Output (MIMO) system.
  • CNR carrier-to- noise ratio
  • SNR signal-to noise ratio
  • MIMO Multiple- Input Multiple- Output
  • the difference between the input and output of the slicer are applied to compute the error signal which in-turn is used to update the weights, whereas in the proposed invention the weights are updated independently on each channel before the combining.
  • Another technique equalizes and combines in the passband (i.e. before demodulation).
  • a Post-Combining Equalizer structure in which there are feed-forward and feedback filters is proposed. Both these filter structure are inter-dependent.
  • the weight update is based on LMS algorithm in both the filters.
  • the equalization and combining is done in the passband while the present technique is done in the baseband.
  • the prior-art proposes Post-Combining Equalizer structures in which there are feed-forward and feedback filters, both these filter structures are inter-dependent.
  • the weight updation is based on LMS algorithm in both the filters whereas in the proposed invention, the weights are updated independently in the Pre-Combining Equalizer using LMS and a prediction algorithm, and for Post-Combining Equalizer, weights are updated using a decision feedback equalizer.
  • the present invention describes a Multilevel Equalizer consisting of two equalizer units for a single carrier.
  • the equalization operation is performed before and after combining the signals.
  • the incoming signals from analog to digital converters are passed through an Aligner unit having multiple individual channels that perform a pilot detection on each channel.
  • the pilot is a tone that occurs periodically and detected using standard methods.
  • the signal is then passed through a Chain Aligner unit that uses the pilot tone for finally obtaining the time-aligned signal.
  • the so-aligned signal is then set to proceed to the Pre-Combining Equalizer comprising a Weight Prediction Equalizer module and a storage -based Pilot Aided LMS Equalizer.
  • the Equalizer contains a Predictive Weight Computer that can efficiently update the weight history of the samples in the system memory after its effective processing, thereby resulting in the faster convergence of Least Mean Square Error (LMSE) and the requirement of fewer samples of the pilot transmission, thus conserving bandwidth.
  • LMSE Least Mean Square Error
  • the module functions by computing the initial weights based on Least Mean Square (LMS) criterion and storing these weights until some threshold value of Bit Error Rate (BER) is received from the final decode output. Once the desired threshold of BER is attained, the module switches to linear predictive filter method for upgrading the next weights, this predictive filter does not depend on the pilot data.
  • LMS Least Mean Square
  • BER Bit Error Rate
  • the system After the initial equalization, the system performs the diversity combining by means of methods like Maximal Ratio Combining or Equal Gain Combining, from where it is further sent to a receiving system connected to a Phase-Shift Keying (PSK) demodulator.
  • PSK Phase-Shift Keying
  • the errors further in the combined signal are rectified employing a second equalization process after the Combiner.
  • the second equalizer system ensures the removal of the net errors in the system, thereby performing improved equalization of the samples that could be decoded even with a lower code rate Forward Error Correction (FEC) enabling higher data bandwidth.
  • FEC Forward Error Correction
  • the Output of PSK Demodulator is fed to a FEC Decoder and Descrambler, which retrieves the original information.
  • a signal is also fed as Decision Feedback to a Post-Combining Equalizer, which minimizes the errors after the combining process.
  • the decode output signal after the FEC Decoder and Scrambler is also used to estimate the Bit Error Rate (BER) information that is used by the module of the Predictive Weight Computer present in the Pre- Combining Equalizer module for retaining the information related to the final weights on attainment of the steady state.
  • BER Bit Error Rate
  • the system consists of an Aligner, a Pre-Combining Equalizer module, a Combiner that applies Maximal Ratio Combining or Equal Gain Combining, a Receive module, a Phase-Shift Keying (PSK) demodulator, a Post-combining Equalizer and a Forward Error Correction (FEC) Decoder and Descrambler.
  • the Pre-Combining Equalizer module includes a set of Weight Prediction Equalizer and Least Mean Square Equalizer for each Channel.
  • the system introduces a known Pilot data which is a distinct Pilot tone after the Modulator at a fixed interval. These aids to detect these Pilot Data without the need for a complete decode.
  • a Field-Programmable Gate Array acquires the Analog-to- Digital Converter (ADC) samples that serve as input to the Aligner.
  • a Multilevel Equalizer Aided Channel Combining and Decode system having a Weight Prediction Equalizer in each receive channel for the effective operation in any channel condition consists of an Aligner, a Pre- combining Equalizer, a Combiner, a Receiver, a Phase-Shift Keying (PSK) Demodulator, a Post-Combining Equalizer, a Symbol Decode, an Adder, a Desired Signal Occurrence Estimate (DSOE), a Decision Feedback, a Decoded Symbol output, a Bit Error Rate (BER), one or more Raw samples and a FEC Decoder.
  • PSK Phase-Shift Keying
  • the Pre-combining equalizer includes multiple Weight Prediction Equalizers, CH-1 Weight Prediction Equalizer, CH-2 Weight Prediction Equalizer, CH-3 Weight Prediction Equalizer, CH-4 Weight Prediction Equalizer, multiple Least Mean Squared Error Equalizers (LMSE), CH-1 LMSE, CH-2 LMSE, CH-3 LMSE, CH-4 LMSE, one Weight Prediction Equalizer and one Least Mean Squared Error Equalizer for each of the receive channels.
  • the Raw Samples comprising a Pilot Data and information to be transmitted are captured from one of the Analog to Digital Converters.
  • the Aligner is comprised of a Time Aligner and a Phase Aligner.
  • the Desired Signal Occurrence Estimate is an estimate of a next desired signal in terms of receiver sample clocks.
  • the Pre- combining Equalizer observes the Bit Error Rate (BER) coming from the FEC Decoder and switches between the LMSE Equalizer and Weight Prediction Equalizer for each receive channel.
  • the corresponding Weight Prediction Equalizer takes the history of weights to compute the next weight.
  • the LMSE Equalizer in which samples from each of the Analog to Digital Converter are weighed independently, and each output signal is compared with the Desired Signal sample to generate error signals.
  • the Combiner performs merging of multiple inputs.
  • the Receiver is a part of a decision device and performs an initial set of signal processing such as DC offset removal and a small phase rotation.
  • the PSK Demodulator is also a part of the decision device comprising most of signal processing control loops such as Pilot Symbol Detection, Symbol Timing Recovery, and Carrier Recovery control loops.
  • the Post-Combining Equalizer is a decision feedback equalizer, in which output of the Symbol Decode is given to an array of delay elements where each output is weighed, and the weighted sum is fed to control the output of the Combiner.
  • the Symbol Decode converts samples into Symbols and combines In-Phase (I) symbols and Quadrature-Phase (Q) symbols into bits.
  • the Decision Feedback is a feedback given to the Post- Combining Equalizer.
  • the Decoded Symbol Output is symbol output from the Symbol Decode.
  • the Bit Error Rate (BER) corresponds to number of bit errors observed over a pre-defined pilot length.
  • the Adder performs a numeric signed addition of the two inputs, and the sum is given out as the output.
  • the Pilot Data is a pre-defined tone that occurs at a known interval and is a "Desired Signal" and is distinctly distinguishable by the Receiver.
  • One or more signals received by different receive channels encounter different path delays and the signals received by the different receive channels encounter different phase rotations.
  • a Time Aligner time aligns all the signals received at different receive channels by adding appropriate delays.
  • a Phase Aligner is responsible for aligning phase of all the received signals.
  • the corresponding Weight Prediction Equalizer takes the history of the weights and tries standard interpolation and prediction methods including the application of a Kalman Filter to compute the next weight, the LMSE Equalizer in which the samples from each of the Analog to Digital Converter are weighed independently, and each output signal is compared with a Desired Signal sample to generate the error signals. This along with the input samples and a Step Size is used to compute the next set of weights.
  • the Combiner uses Maximal Ratio Combining or Equal Gain Combining.
  • the Pre-combining Equalizer further comprises one or more Standard Delay Elements, a Multiplier, a Weight Prediction Equalizer, a Switcher, a Weight Update module, a Desired Signal and a Bit Error Rate (BER).
  • the standard delay element provides one sample clock delay to incoming samples that is when output of the Standard Delay Element is previous sample, and then input of the Standard Delay Element would be current sample.
  • the Multiplier performs numeric signed multiplication of the two inputs, and the product is given as the output.
  • the Weight Prediction Equalizer refers to any one of the CH-1 Weight Prediction Equalizer, CH-2 Weight Prediction Equalizer, CH-3 Weight Prediction Equalizer, CH-4 Weight Prediction Equalizer.
  • the Switcher observes the Bit Error Rate (BER) coming from the FEC Decoder and switches between the CH-1 Weight Prediction Equalizer or CH-1 Least Mean Squared Error Equalizer on Receive Channel- 1, CH-2 Weight Prediction Equalizer or CH-2 Least Mean Squared Error Equalizer on Receive Channel-2, CH-3 Weight Prediction Equalizer or CH-3 Least Mean Squared Error Equalizer on Receive Channel-3 and CH-4 Weight Prediction Equalizer or CH-4 Least Mean Squared Error Equalizer on Receive Channel-4.
  • the Weight Update module performs standard weight update computations including Least Mean Square (LMS).
  • LMS Least Mean Square
  • the Desired Signal is the known data (known to both transmitter and the receiver) that is transmitted at identified intervals.
  • the Post-combining Equalizer is a decision feedback equalizer, further comprises a Decision Feedback, a Multiplier, a Weight Update module and one or more standard delay elements.
  • the Decision Feedback is a feedback given to the Post- Combining Equalizer.
  • the standard delay element provides one sample clock delay to the incoming samples that is when the output of the Standard Delay Element is the previous sample, then the input of the Standard Delay Element would be the current sample.
  • the Multiplier performs numeric signed multiplication of the two inputs, and the product is given as the output.
  • the Weight Update module performs standard weight update computations including Least Means Square (LMS).
  • LMS Least Means Square
  • the method of the present invention having a Weight Prediction Equalizer in each receive channel for effective operation in any channel condition that consists of an Aligner, a Pre-combining Equalizer, multiple Weight Prediction Equalizers, CH-1 Weight Prediction Equalizer, CH-2 Weight Prediction Equalizer, CH-3 Weight Prediction Equalizer, CH-4 Weight Prediction Equalizer, multiple Least Mean Squared Error Equalizers (LMSE), CH-1 LMSE, CH-2 LMSE,CH-3 LMSE, CH-4 Least LMSE, a Combiner, a Receiver, a Phase-Shift Keying (PSK) Demodulator, a Post-Combining Equalizer, a Symbol Decode, an Adder, a Desired Signal Occurrence Estimate (DSOE), a Decision Feedback, a Decoded Symbol output, a Bit Error Rate (BER), one or more Raw samples, one or more final weights, one or more streams that correspond to the output of the Aligner and a FEC Decoder, comprising the steps of:
  • One or more final weights are applicable for the samples acquired after this calculation and are valid till the next set of weights are computed based on Pilot indicator state.
  • For the first pilot detected buffered samples are equalized, and simultaneously the other stream passes through the equalizer transparently without any modifications where once the weights are computed, the same are applied to the stream data by convolution.
  • the above step is repeated for each Desired Signal detected in received stream, and the previous weights are used as initial weights for every subsequent equalization process.
  • a weight array is created for every Desired Signal passing through the equalizer as copy of weights obtained from the equalizer is stored in another buffer.
  • the Bit Error Rate is computed using standard methods, once the signal is decoded which are fed to the equalizer and the process continues until an acceptable threshold of the Bit Error Rate is achieved. Upon attainment of the acceptable BER value, weight update process switches from the LMSE Equalizers to the corresponding Weight Prediction Equalizer.
  • CH-1 Least Mean Squared Error Equalizer is replaced with CH-1 Weight Prediction Equalizer
  • CH-2 Least Mean Squared Error Equalizer is replaced with CH-2 Weight Prediction Equalizer
  • CH- 3 Least Mean Squared Error Equalizer is replaced with CH-3 Weight Prediction Equalizer
  • CH-4 Least Mean Squared Error Equalizer is replaced with CH-4 Weight Prediction Equalizer weights in the system thereby assisting the system to adapt weights to changing channel in the absence of the new weights from the LMSE and also to aid faster convergence to steady state for LMSE.
  • the channel with the signal that is responsible for the termination of clock counters in the other channels is the reference channel and all other channels are referenced to this channel.
  • Desired Signal Occurrence Estimate is a pre-determined number of receive clock cycles after which the next pilot tone is expected to occur. Identification of the reference channel is responsible for the change in the signal path from Delay computation path flow to Data Path flow.
  • the Combiner incorporates maximal ratio combining (MRC) or equal gain combining (EGC) method.
  • MRC maximal ratio combining
  • ECG equal gain combining
  • a periodic Desired Signal tone that once aligned makes it possible to estimate the next occurrence in terms of receive clocks.
  • the clock count value is called Desired Signal Occurrence Estimate (DSOE) and is a number of receive clock cycles after which the next pilot tone is expected to occur. Identification of the reference channel is responsible for the change in the signal path to Data Path flow. Upon achieving steady state, the final weights computed depending on the Bit Error Rate output is retained, and the process of switching of the weights is avoided.
  • Radio channel Two types of communication systems benefit from this phenomena.
  • radio waves In over the horizon Communication systems, radio waves encounter the lower boundaries of the atmosphere where the atmospheric conditions can affect the Radio channel. However, these conditions are cyclic in nature and a predictive filter can leverage the cyclic nature to converge faster.
  • radio waves operate at a center- frequency as high as 20 GHz to 80GHz. At such high frequencies, the radio channel is susceptible to even minor environmental changes such as mist and seasonal humidity. The predictive filter helps counter this.
  • Figure 1 shows the overall block diagram for a Modem system equipped with an Encode Transmission and Decode unit.
  • Figure 2 shows the Multilevel Equalizer Aided Channel Combining and Decode system.
  • Figure 3 shows the various logical components of the Pre-Combining Equalizer.
  • Figure 4 shows the various logical components of the Post-Combining Equalizer.
  • Figure 5 shows the flowchart of the dual equalization process.
  • Figure 6 shows the flowchart representation of the computational process of the weight prediction by the Linear Weight Prediction module using an algorithm such as Kalman Filter.
  • FIG. 1 shows the overall block diagram for a Modem system equipped with an Encode transmission and Decode unit.
  • the system consists of a PC 500, a System Ethernet interface 501, a Receive block R, a Transmit block T, an Oven- Controlled Crystal Oscillator (OCXO) 522 and a Clock Distribution 524.
  • the PC 500 is connected via the System Ethernet interface 501 to the Receive block R and the Transmit block T.
  • the Transmit block T consists of a Scrambler 535, an FEC Encoder 534, a Burst Modulator 533, a DAC driver 531, a Digital to Analog Converter (DAC) 528, a DAC DATACLK Generator 529, a Low Pass Filter 527, an IQ-Modulator 526, an IQ-Modulator LO Generator 523, an IF Front-end 525, a Splitter 519 and Transmission channels 517, 518.
  • DAC Digital to Analog Converter
  • the Receive block R consists of Receive Channel- 1 516a, Receive Channel-2 516b, Receive Channel-3 516c and Receive Channel-4 516d, Intermediate Frequency (IF)Front-end- 1 515a, Intermediate Frequency (IF) Front-end-2 515b, Intermediate Frequency (IF) Front-end-3 515c and Intermediate Frequency (IF)Front-end-4 515d, IQ Demodulators 514a, 514b, 514c, 514d, Signal Conditioning 513a, 513b, 513c, 513d, Analog to Digital Converters (ADC) 512a, 512b, 512c, 512d, a Multilevel Equalizer Aided Channel Combining and Demodulator 511, a Forward Error Correction (FEC) Decoder 508, a Descrambler507, a 4x IQ DEMOD LO Generator520 and a 4xADC CLK Generator 521.
  • ADC Analog to Digital Converters
  • the PC 500 is any computing device that is capable of transmitting and receiving an Ethernet data.
  • the System Ethernet Interface 501 refers collectively to the Ethernet data processing system consisting of hardware ports and computing logic that acts on the data received from the PC 500 and given by the device to the PC 500.
  • Input bits 501x are to be transmitted over the Intermediate Frequency (IF) interface.
  • Bit Output 507x is decoded from the signal received over the Intermediate Frequency (IF) interface.
  • the Descrambler 507 is responsible for Descrambling of data that is scrambled by the Scrambler 535. If the Scrambler 535 is disabled, the Descrambler 507 has to be bypassed.
  • Scrambled Bit Output 508x corresponds to the bits that are an output of the FEC Decoder 508 and are input to the Descrambler 507.
  • the FEC Decoder 508 is responsible for decoding of data that is encoded by the FEC Encoder 534 on the Transmit side. If the FEC Encoder 534 is disabled on the Transmit side, the FEC Decoder 508 has to be bypassed.
  • Bit Error Rate (BER) 116 corresponds to the number of bit errors observed over a pre-defined pilot length.
  • the Encoded and Scrambled Bit Output 510 are the bits prior to being sent to the FEC Decoder 508.
  • the Multilevel Equalizer Aided Channel Combining and Demodulator 511 are responsible for acquiring the data from multiple Analog to Digital Converters 512a..d, does co- phasing, subsequently diversity combining, equalizes and demodulates the signal to obtain the data.
  • the Analog to Digital Converters 512a..d converts the analog signal from the Signal Conditioning 513a..d to proportional multi-bit parallel digital values.
  • the Signal Conditioning 513a..d performs amplification and DC level shifting of the Analog signal to the levels appropriate to each of the Analog to Digital Converters 512a..d.
  • the IQ Demodulators 514a..d converts the bandpass signal at Intermediate Frequency to a baseband signal.
  • the IF Front End 515a..d comprises a pair of Saw Filter Networks, Digital Step Attenuators and Low Noise Amplifiers.
  • the multiple Receive Channels 516a..d refers to the IF signal that is given to each of the IF Front End 515a..d.
  • the Transmit Out-1 517, Transmit Out-2 518 refers to the Analog Signal that is the IF output of the system.
  • the Splitter 519 is a device that divides the signal from TX IF Front End 525 into two and hands over to Transmit Out-1 517 and Transmit Out-2 518.
  • the input clocks are from the clock regenerators, the IQ Demodulator LO Generator 520 for the IQ Demodulators 514a..
  • the Oven Controlled Crystal Oscillator (OCXO) 522 is an Ultra- Low Jitter 10MHz clock which forms the "Station Clock" of the system.
  • the Clock Distribution 524 allocates the OCXO 522 clock to the other clock generators in the system.
  • the TX IF Front End 525 comprises a Saw Filter network, Attenuators and Low Noise Amplifiers of the Transmit side.
  • the IQ- Modulator 526 converts the baseband In-Phase (I) and Quadrature-Phase (Q) signal to bandpass signal at Intermediate Frequency (IF).
  • the Low Pass Filter 527 is used to remove the harmonics present in the output of the Digital to Analog Converter 528 and conserve the overall system bandwidth requirement.
  • the Digital to Analog Converter 528 produces an analog waveform proportional to the digital value on the transmit data. It accepts a parallel digital data and produces an analog voltage proportional to the digital value.
  • the DACDATACLK Generator 529 is clock regenerators that will clock the Digital to Analog Converter 528.
  • the DAC Driver 531 converts the data from the Burst Modulator 533 suitable for the Digital to Analog Converter 528.
  • the Burst Modulator 533 converts the data bits to In-Phase (I) and Quadrature-Phase (Q) data of appropriate levels.
  • the FEC Encoder 534 does the forward error correction encoding on the data.
  • Encoded and Scrambled Input Bits 534x are the bits after the scrambling and FEC encoding processes.
  • the Scrambler 535 is used for the following purposes, (a) to enable accurate timing recovery on the receiver without resorting to redundant line coding and (b) to disperse the energy on the carrier. It disperses the data to meet the maximum power spectral density requirements.
  • Scrambled Input Bits 535x refers to the bits to be transmitted after the scrambling process.
  • Figure 2 is the Multilevel Equalizer Aided Channel Combining and Decode system that consists of an Aligner 102, a Pre-Combining Equalizer 104, a Combiner 109, a Receiver 110, a PSK Demodulator 111, a Post-Combining Equalizer 112, a Symbol Decode 113 and an Adder 117.
  • the Pre-Combining Equalizer 104 includes multiple Weight Prediction Equalizers, CH-1 Weight Prediction Equalizer 104a, CH-2 Weight Prediction Equalizer 104b, CH-3 Weight Prediction Equalizer 104c, CH-4 Weight Prediction Equalizer 104d, multiple Least Mean Squared Error Equalizers (LMSE), CH-1 LMSE 105, CH-2 LMSE 106, CH-3 LMSE 107, CH-4 Least LMSE 108. There is one Weight Prediction Equalizer and one Least Mean Squared Error Equalizer for each of the receive channels.
  • Raw Samples 101 from each of the Analog to Digital Converters 512a..d is captured.
  • the Raw Samples 101 comprises a Pilot Data and the information to be transmitted.
  • This Pilot Data is a pre-defined tone that occurs at a known interval.
  • the Pilot Data is the "Desired Signal" and is distinctly distinguishable by the Receiver 110.
  • the Aligner 102 contains two portions which are a Time Aligner and a Phase Aligner.
  • the signals received by the different receive channels encounters different path delays.
  • the Time Aligner time aligns all the signals received at the different receive channels by adding appropriate delays.
  • the signals received by the different receive channels encounter different phase rotations.
  • the Phase Aligner is responsible for aligning the phase of all the received signals.
  • a Desired Signal Occurrence Estimate (DSOE) 103 is the estimate of the next desired signal 305 in terms of the receiver sample clocks.
  • the Pre-Combining Equalizer 104 observes a Bit Error Rate (BER) 116 coming from the FEC Decoder 508 and switches between the LMSE Equalizer and Weight Prediction Equalizer for each receive channel.
  • the respective Weight Prediction Equalizer 104a..d takes the history of the weights and try standard interpolation or prediction algorithms (like Kalman Filter) to compute the next weight.
  • the LMSE Equalizer 105, 106, 107, 108 in which the samples from each of the Analog to Digital Converter 512a..d is weighed independently, and each output signal is compared with a Desired Signal 305 sample to generate the error signals. These error signals, along with the input samples and a Step Size are used to compute the next set of weights.
  • the Combiner 109 that can be a Maximal Ratio Combining or an Equal Gain Combining performs merging of the multiple inputs.
  • the Receiver 110 is a part of the decision device and performs an initial set of signal processing such as DC offset removal and a small phase rotation.
  • the PSK Demodulator 111 is also a part of the decision device.
  • the PSK Demodulator 111 comprises most of the signal processing control loops such as Pilot Symbol Detection, Symbol Timing Recovery, and Carrier Recovery control loops.
  • the Post-Combining Equalizer 112 is a decision feedback equalizer, in which the output of the Symbol Decode 113 is given to an array of delay elements where each output is weighed, and the weighted sum is fed to control the output of the Combiner 109.
  • the Symbol Decode 113 converts the samples into Symbols and combines the In-Phase (I) symbols and Quadrature-Phase (Q) symbols into bits.
  • Decision Feedback 114 is the feedback given to the
  • Decoded Symbol Output 115 is the symbol output from the Symbol Decode
  • the Bit Error Rate (BER) 116 corresponds to the number of bit errors observed over a predefined pilot length.
  • the Adder 117 performs a numeric signed addition of the two inputs, and the sum is given out at the output.
  • Figure 3 includes the various logical components of the Pre-Combining Equalizer.
  • a Standard Delay Element 300 provides one sample clock delay to the incoming samples that is when the output of the Standard Delay Element 300 is the previous sample, then the input of the Standard Delay Element 300 would be the current sample.
  • the Multiplier 301 performs numeric signed multiplication of the two inputs, and the product is given as the output.
  • the Weight Prediction Equalizer 308 refers to any one of the CH-1 Weight Prediction Equalizer 104a, CH-2 Weight Prediction Equalizer 104b, CH-3 Weight Prediction Equalizer 104c, CH-4 Weight Prediction Equalizer 104d.
  • the Switcher 303 observes the Bit Error Rate (BER) 116 coming from the FEC Decoder 508 and switches between the CH-1 Weight Prediction Equalizer 104a or CH-1 Least Mean Squared Error Equalizer 105 on Receive Channel- 1, CH-2 Weight Prediction Equalizer 104b or CH-2 Least Mean Squared Error Equalizer 106 on Receive Channel-2, CH-3 Weight Prediction Equalizer 104c or CH-3 Least Mean Squared Error Equalizer 107 on Receive Channel-3 and CH-4 Weight Prediction Equalizer 104d or CH-4 Least Mean Squared Error Equalizer 108 on Receive Channel-4.
  • BER Bit Error Rate
  • the Weight Update 304 performs standard weight update computations (e.g. LMS).
  • the Desired Signal 305 is the known data (known to both transmitter and the receiver) that is transmitted at identified intervals.
  • the Bit Error Rate 116 corresponds to the number of bit errors observed over a predefined pilot length.
  • Figure 4 includes the various logical components of the Post-combining Equalizer.
  • the Receiver 110 is a part of the decision device and performs an initial set of signal processing such as DC offset removal and a small phase rotation.
  • the PSK Demodulator 111 is also a part of the decision device and comprises most of the signal processing control loops such as Pilot Symbol Detection, Symbol Timing Recovery and Carrier Recovery control loops.
  • the Adder 117 performs numeric signed addition of the two inputs, and the sum is given out at the output.
  • the Symbol Decode 113 converts the samples into Symbols and combines the In-Phase (I) symbols and Quadrature-Phase (Q) symbols into bits.
  • the Post-Combining Equalizer 112 is a decision feedback equalizer, in which the output of the Symbol Decode 113 is given to an array of delay elements where each output is weighed, and the weighted sum is fed to control the output of the Combiner 109.
  • the Decision Feedback 114 is the feedback given to the Post-Combining Equalizer 112.
  • the Decoded Symbol Output 115 is the symbol output from the Symbol Decode 113.
  • FIG. 5 shows the flowchart of the Dual Equalization process.
  • the process starts 1 by the acquisition of the digital signal 2 from the multiple Analog to Digital Converter 512a..d simultaneously 3 through the Aligner 102.
  • Desired Signal 305 is a tone that occurs periodically and detected using standard methods.
  • the received signal is subjected to identical processing 5, for the detection of the start of the Desired Signal frame at the multiple receive channels 4.
  • the respective Desired Signal 305 detection circuits in the receive channel are employed for the detection process 6.
  • the clock counter in the respective Desired Signal Detection circuit is initiated 7.
  • the same process applies to the detection of the Desired Signal 305 in the other channel at the respective Desired Signal detection circuit 8.
  • the clock counters in the previous channels are terminated 9.
  • the channel with the signal that is responsible for the termination of clock counters in the other channels is the reference channel. All other channels are referenced to this channel.
  • the count on each of the clock counters corresponds to the path delay experienced by the signal received at the respective antenna.
  • the Desired Signal 305 tone is periodic, once aligned it is possible to estimate the next occurrence in terms of the receive clocks 10.
  • the Desired Signal Occurrence Estimate (DSOE) 103 is a pre- determined number of receive clock cycles after which the next pilot tone is expected to occur.
  • the above flow is called the Delay Computation Path. Identification of the reference channel is responsible for the change in the signal path from Delay Computation Path flow to Data Path flow.
  • the Desired Signal Occurrence Estimate 103 is used to fill and flush the system buffer, and the arrival is kept track by a counter that expires on the start of the Desired Signal 305, checks if the desired signal estimations are aligned 11. If they are aligned then, the Desired Signal Occurrence estimate 103 is generated 12.
  • the signal is time-aligned as the Chain Delay Counter consists of predetermined time delay 13 for channels. The precision of alignment is limited by the resolution of time-base and the jitter of the clock.
  • the time-aligned signal in each channel is transmitted 14 to the corresponding Pre-Combining Equalizer 104, which stores the weight-related data of the Desired Signal Occurrence Estimate 103 in a system Buffer 15.
  • the LMSE equalization process begins 18 in the LMSE Equalizers 105, 106, 107, 108 and is done for a desired signal sample length.
  • One or more final weights, thus obtained will be applicable for the samples acquired after this calculation and are valid till the next set of weights are computed based on the Pilot indicator state.
  • the buffered samples are being equalized, and simultaneously the other stream passes through the equalizer transparently without any modifications.
  • the weights are computed, the same are applied to the stream data by convolution. This process is repeated for each Desired Signal detected in the received stream, and the previous weights are used as the initial weights for every subsequent equalization process.
  • a weight array is created for every Desired Signal passing through the equalizer as the copy of weights obtained from the Equalizer is stored in another buffer.
  • the Bit Error Rate 116 is computed using standard methods once the signal is decoded 27, which are fed to the equalizer and the process continues until an acceptable threshold of the Bit Error Rate 116 is achieved.
  • the weight update process switches 16 from the LMSE Equalizers 105, 106, 107, 108 to the corresponding Weight Prediction Equalizer 104a..d. This leads to the requirement of fewer instances of the pilot and thus increases the overall bandwidth of the system.
  • CH-1 Least Mean Squared Error Equalizer 105 is replaced with CH-1 Weight Prediction Equalizer 104a
  • CH-2 Least Mean Squared Error Equalizer 106 is replaced with CH-2 Weight Prediction Equalizer 104b
  • CH-3 Least Mean Squared Error Equalizer 107 is replaced with CH-3 Weight Prediction Equalizer 104c
  • CH-4 Least Mean Squared Error Equalizer 108 is replaced with CH-4 Weight Prediction Equalizer 104d weights in the system 17.
  • the equalized signal is combined by a multipath Combiner that incorporates either the maximal ratio combining (MRC) or equal gain combining (EGC) methods 19, so as to increase the signal- to-noise (S/N) ratio of the signal received.
  • the combined signal is processed 20 by the Receiver 110 and PSK Demodulator 111, followed by the process of post- combining equalization 21 by the Post-Combining Equalizer that equalizes the signal and eliminates the residual error that may be introduced or remaining during the combination process.
  • the Decision Feedback 114 is the feedback given to the Post-Combining Equalizer 112.
  • the original information is then extracted from the Post-Combining Equalizer 112 by the FEC Decoder 508 and a Descrambler 507 at 22.
  • the output of the FEC Decoder 23, the Bit Error Rate, 116 is given to the Pre-Combining Equalizer 104 for switching between Ch-1 Least Mean Squared Error Equalizer 105 and CH-1 Weight Prediction Equalizer 104a, CH-2 Least Mean Squared Error Equalizer 106 and CH-2 Weight Prediction Equalizer 104b, CH-3 Least Mean Squared Error Equalizer 107 and CH-3 Weight Prediction Equalizer 104c, CH-4 Least Mean Squared Error Equalizer 108 and CH-4 Weight Prediction Equalizer 104d which ends the Process 24.
  • Figure 6 shows the flowchart representation of the computational process of the weight prediction by the Linear Weight Prediction using an algorithm such as Kalman Filter.
  • the algorithm starts 401 with the acquisition of the observation vector 'V which corresponds to the actual weight that is obtained from the Least Mean Square Error (LMSE) method and defining a control vector 'u', which defaults to zero value while deriving the obtained value 'z' 402.
  • the next step includes the initialization of the system matrix involving the state transition matrix ⁇ ', input matrix 'B' and the observation matrix ⁇ ', with a default value of 1 for each matrix.
  • LMSE Least Mean Square Error
  • This step also initializes other parameters like process noise covariance 'Q' and measurement noise covariance 'R' at 403, followed by verifying if x, P are available. If available skips 405, else executes at 404. Since the values of x and P are not available, the algorithm will estimate an initial value for 'x' and 'P' 405.
  • the next step 406 involves consecutively computing the predictions for the state vector 'x'. Then compute the Co-variance Matrix P 407. Further computes the Kalman Gain 408, compute the correction based on the observation for the state estimate 409 and computes the correction based on the observation for the Covariance Matrix 410. The computed x is iteratively fed 406 to reduce the error 411 and thus ends the process 412.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

La présente invention concerne un égaliseur multi-niveau portant deux unités d'égaliseur permettant d'effectuer des opérations d'égalisation avant et après la combinaison des signaux à trajets multiples. L'égaliseur de pré-combinaison fonctionne sur la base du critère quadratique moyen minimal (LMS) et du procédé de filtrage prédictif linéaire au moyen du taux d'erreur sur les bits (BER)) de la sortie finale, ce qui réduit au minimum les erreurs causées par les retards de propagation par trajets multiples et les brouillages entre symboles (ISI) L'égaliseur de post-combinaison réduit efficacement les erreurs induites en raison d'une combinaison imparfaite. Un tel système peut fonctionner de manière appropriée par l'utilisation d'une correction d'erreurs sans voie de retour (FEC) ayant un taux de code inférieur qui peut être efficace pour obtenir une largeur de bande plus élevée.
PCT/IN2016/050153 2016-05-24 2016-05-24 Égaliseur dynamique de stockage de coefficients Ceased WO2017203535A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116170075A (zh) * 2023-01-19 2023-05-26 北京邮电大学 用于光通信系统的自适应均衡方法及装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6862315B1 (en) * 2000-07-25 2005-03-01 Advanced Micro Devices, Inc. Network receiver utilizing pre-determined stored equalizer coefficients

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6862315B1 (en) * 2000-07-25 2005-03-01 Advanced Micro Devices, Inc. Network receiver utilizing pre-determined stored equalizer coefficients

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116170075A (zh) * 2023-01-19 2023-05-26 北京邮电大学 用于光通信系统的自适应均衡方法及装置

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