WO2018176823A1 - 一种goa单元及其驱动方法、goa驱动电路、显示装置 - Google Patents

一种goa单元及其驱动方法、goa驱动电路、显示装置 Download PDF

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Publication number
WO2018176823A1
WO2018176823A1 PCT/CN2017/107689 CN2017107689W WO2018176823A1 WO 2018176823 A1 WO2018176823 A1 WO 2018176823A1 CN 2017107689 W CN2017107689 W CN 2017107689W WO 2018176823 A1 WO2018176823 A1 WO 2018176823A1
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WIPO (PCT)
Prior art keywords
pull
node
output
goa unit
transistor
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Ceased
Application number
PCT/CN2017/107689
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English (en)
French (fr)
Inventor
熊欣
熊雄
梁恒镇
刘荣铖
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/060,677 priority Critical patent/US11211022B2/en
Priority to EP17898348.2A priority patent/EP3605516B1/en
Publication of WO2018176823A1 publication Critical patent/WO2018176823A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the present disclosure relates to the field of display technologies, and more particularly to an array substrate row driving unit having a self-healing function and a driving method thereof, a GOA driving circuit including the GOA unit, and a display device including the GOA driving circuit.
  • the gate driving device is generally formed on the array substrate of the liquid crystal display by an array process, that is, the Gate Driver on Array (GOA) process, which saves the cost and is the development trend of the TFT-LCD in the future.
  • GOA Gate Driver on Array
  • the GOA unit still has a lot of things to be perfected. At present, most of the output abnormalities of the GOA unit are multiple output of the GOA unit (Multi-Output). If the GOA unit can achieve self-repair of multiple outputs through its own design, Improve product yield, improve product anti-interference ability, improve product quality and reliability, and increase design margin (Margin), thereby increasing design adjustability and reducing design difficulty.
  • Multi-Output multiple output of the GOA unit
  • the GOA unit is designed to replace the function of the gate driver IC, and the cost is reduced.
  • the function of the GOA unit has not yet reached the overall stability of the gate driver IC. Due to the instability in the process and the requirements of the customer system for the panel timing, the GOA unit is likely to cause abnormal output due to various reasons, that is, multiple output conditions. Once multiple outputs occur, due to the cascade characteristics of the GOA unit. It will affect the work of the entire GOA unit. AD (Abnormal Display) is not good. There is no repair circuit for self-repair of multiple outputs in the existing design, so the GOA unit is extremely sensitive to abnormal working signals and cannot be repaired. Recoverable).
  • a repair circuit is added at the back end of the front end GOA unit.
  • the frame start signal STV turns on the first repair control transistor M12, and the reset node RE of the GOA unit of each row of gates Charging.
  • the second repair control transistor M13 is turned on, and the output of the front end of the first frame is normal. Output.
  • the output of the front end output turns on the third repair control transistor M14, thereby lowering the level of the reset node RE, cutting off the second repair control transistor M13, and shielding other abnormal outputs. Thereby achieving self-healing function when abnormal output.
  • the present disclosure provides an array substrate row driving GOA unit, comprising: a front end GOA unit, a connection signal input end, a reset signal end, a first power supply voltage end, a second power supply voltage end, a third power supply voltage end, a clock signal end, and
  • the front end output end is configured to output a clock signal of the clock signal end to the front end output end when the input signal of the signal input end is at the effective input level; and a repair circuit connecting the front end output end, the frame start signal, and the first power supply voltage end
  • an output of the GOA unit configured to output a pulse of the front end output to the output of the GOA unit when the frame start signal is at the active input level; and to cause the GOA when the frame start signal is at an inactive input level There is no output at the output of the unit to leave the GOA unit in an output-free state.
  • the repair circuit includes: a first repair control transistor having a gate and a first pole connected to a frame start signal, a second pole connected to the reset node, and a second repair control transistor having a gate connected to the reset node, One pole is connected to the front end output, the second pole is connected to the output end of the GOA unit; the first capacitor has a first end connected to the reset node; and a third repair control transistor whose gate is connected to the output of the next stage GOA unit The first pole is connected to the second end of the first capacitor, and the second pole is connected to the first power voltage terminal.
  • the front end GOA unit comprises: an input circuit, a connection signal input end and a pull-up node, configured to transmit the received input signal to the pull-up node when the input signal of the signal input end is at the effective input level; the reset circuit, the connection The reset signal terminal, the first power supply voltage terminal and the pull-up node are configured to pull the pull-up signal at the pull-up node to the power supply voltage of the first power supply voltage terminal when the reset signal of the reset signal terminal is at the active control level; the pull-down control circuit Connecting the second power voltage terminal, the third power voltage terminal, the pull-up node, the pull-down node, and the first power voltage terminal, configured to control whether the pull-down circuit operates; the pull-down circuit, the connection pull-down node, the pull-up node, the first a supply voltage terminal and a front end output configured to pull a voltage of the front end output and the pull up node to a supply voltage of the first supply voltage terminal when a pull down signal at the pull down node is
  • the input circuit includes an input transistor having a gate and a first pole connected to the signal input end, and a second pole connected to the pull-up node.
  • the reset circuit includes: a reset transistor having a gate connected to the reset signal terminal, a first pole connected to the pull-up node, and a second pole connected to the first power voltage terminal.
  • the pull-down control circuit includes a first pull-down control circuit and a second pull-down control circuit, wherein the pull-down node includes a first pull-down node and a second pull-down node.
  • the first pull-down control circuit includes: a first pull-down control transistor, the gate is connected to the first pull-down control node, the first pole is connected to the second power voltage terminal, and the second pole is connected to the first pull-down node a second pull-down control transistor having a gate connected to the pull-up node, a first pole connected to the first pull-down node, a second pole connected to the first power supply voltage terminal, and a third pull-down control transistor having a gate and a first The poles are respectively connected to the second power voltage terminal, the second pole is connected to the first pull-down control node, and the fourth pull-down control transistor has a gate connected to the pull-up node, and the first pole is connected to the first pull-down control node, The second pole is connected to the first power voltage terminal, and the second pull-down control circuit comprises: a fifth pull-down control transistor, the gate is connected to the second pull-down control node, the first pole is connected to the third power voltage end, and the second pole is connected a second
  • the pull-down circuit includes a first pull-down circuit and a second pull-down circuit.
  • the first pull-down circuit includes: a first node pull-down transistor, a gate of the first node pull-down transistor is connected to the first pull-down node, a first pole of the first node pull-down transistor is connected to the pull-up node, and the first node pulls down the transistor
  • the second pole is connected to the first power voltage terminal; and the first output pull-down transistor, the gate of the first output pull-down transistor is connected to the first pull-down node, and the first pole of the first output pull-down transistor is connected with the front end output end,
  • the second pole of an output pull-down transistor is connected to the first power voltage terminal;
  • the second pull-down circuit comprises: a second node pull-down transistor, a gate of the second node pull-down transistor is connected to the second pull-down node, and a second node pull-down transistor One pole is connected to the pull-up node, the second pole of the second node pull-down transistor is connected to the first power voltage terminal; and the second output pull-down transistor
  • the output circuit comprises: an output transistor having a gate connected to the pull-up node, a first pole connected to the clock signal end, a second pole connected to the front end output end, and a second capacitor having a first end and a pull-up The node is connected, and the second end is connected to the front end output.
  • the frame start signal is a valid input level at the beginning of each frame.
  • the present disclosure also provides a driving method of a GOA unit, the GOA unit comprising the GOA unit as described above, the method comprising: when the frame start signal is at an effective input level, passing the front end output end of the front end GOA unit through the repair circuit A pulse is output to the output of the GOA unit; when the frame start signal is at an inactive input level, the output of the GOA unit is outputted by the repair circuit such that the GOA unit is in an output-free state.
  • the frame start signal is a valid input level at the beginning of each frame.
  • the present disclosure also provides a GOA driving circuit comprising cascaded N GOA units, the N GOA units being a first GOA unit to an Nth GOA unit, each GOA unit being a GOA unit as described above, wherein N Is an integer greater than or equal to 2.
  • the signal input end of the first GOA unit is connected to the frame start signal, and the reset signal end of the Nth GOA unit is connected to the frame start signal;
  • the second GOA unit to the Nth GOA unit a signal input end of each of the GOA units is connected to an output end of a GOA unit adjacent thereto, and a reset signal end of each of the first GOA unit to the N-1GOA unit is connected to The output of the adjacent next stage GOA unit.
  • the frame start signal is connected to each level of the GOA unit.
  • the present disclosure also provides a display device including the above-described GOA driving circuit.
  • FIG. 1 shows a block diagram of a single GOA unit with self-healing functionality in accordance with an embodiment of the present disclosure
  • FIG. 2A shows a block diagram of a single GOA unit with self-healing functionality in accordance with an embodiment of the present disclosure
  • Figure 2B shows a detailed block diagram of the single GOA unit of Figure 2A;
  • FIG. 3 illustrates an example circuit diagram of a single GOA unit with self-healing functionality in accordance with an embodiment of the present disclosure
  • FIG. 4 illustrates a self-healing function when a GOA unit is abnormal according to an embodiment of the present disclosure. Timing diagram of the GOA unit;
  • FIG. 5 illustrates a timing diagram of a GOA unit having a self-healing function when a GOA unit is normal according to an embodiment of the present disclosure
  • FIG. 6 illustrates an overall structure of a GOA driving circuit according to an embodiment of the present disclosure
  • FIG. 7 shows a flow chart of a driving method of a GOA unit according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the connection modes of the drain and the source of each transistor are interchangeable. Therefore, the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the thin film transistor used in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor. In an embodiment of the present disclosure, when an N-type thin film transistor is employed, its first electrode may be a source and the second electrode may be a drain.
  • a thin film transistor is an N-type transistor
  • the thin film transistor is turned on. It is conceivable that when a P-type transistor is used, the timing of the drive signal needs to be adjusted accordingly.
  • FIG. 1 illustrates a block diagram of a single GOA unit with self-healing functionality in accordance with an embodiment of the present disclosure.
  • the GOA unit includes a front end GOA unit 101 and a repair circuit 102.
  • the repair circuit 102 is added after the output of the front end GOA unit 101.
  • the front end GOA unit 101 is connected to the signal input terminal Input, the reset signal terminal RESET, the first power supply voltage terminal VSS, the second power supply voltage terminal VDD1, the third power supply voltage terminal VDD2, the clock signal terminal CLK, and the front end output.
  • the terminal is configured to output a clock signal of the clock signal terminal CLK to the front end output when the input signal Input of the signal input terminal is at the effective input level.
  • the repair circuit 102 is connected to the front end of the front end GOA unit 101.
  • the output terminal, the frame start signal STV, the first power supply voltage terminal VSS, and the output terminal of the GOA unit are configured to output a pulse of the front end output terminal to the output end of the GOA unit when the frame start signal STV is at the active input level. And when the frame start signal STV is at an inactive input level, the output of the GOA unit is outputted such that the GOA unit is in an outputless state.
  • the GOA unit according to the present disclosure can filter out abnormal output and interference signals.
  • the first power voltage terminal VSS is a low power voltage terminal.
  • the second and third supply voltage terminals VDD1 and VDD2 are high supply voltage terminals.
  • FIG. 2A shows a block diagram of a single GOA unit with self-healing functionality in accordance with an embodiment of the present disclosure.
  • the front end GOA unit 101 includes an input circuit 201, a reset circuit 202, a pull-down control circuit 203, a pull-down circuit 204, and an output circuit 205.
  • the input circuit 201 is coupled to the signal input terminal Input and the pull-up node PU, and is configured to pass the received input signal to the pull-up node PU when the input signal Input of the signal input terminal is at an active input level.
  • the reset circuit 202 is connected to the reset signal terminal RESET, the first power supply voltage terminal VSS and the pull-up node PU, and is configured to pull down the pull-up signal at the pull-up node PU when the reset signal of the reset signal terminal RESET is at the active control level.
  • the power supply voltage to the first power supply voltage terminal VSS.
  • the pull-down control circuit 203 is connected to the second power supply voltage terminal VDD1, the third power supply voltage terminal VDD2, the pull-up node PU, the pull-down nodes PD1 and PD2, and the first power supply voltage terminal VSS, and is configured to control whether the pull-down circuit 204 operates.
  • the pull-down control circuit 203 generates a pull-down signal at the pull-down node PD at the pull-down node PD when the pull-up signal at the pull-up node PU is at the active pull-up level; and the pull-up signal at the pull-up node PU is at At the non-active pull-up level, the high-level voltage signal VDD1 or VDD2 is supplied to the pull-down nodes PD1 and PD2 in response to the high-level voltage signal VDD1 or VDD2.
  • the pull-down circuit 204 is connected to the pull-down node PD, the pull-up node PU, the first power supply voltage terminal VSS and the front-end output terminal, and is configured to connect the front-end output terminal and the pull-down signal at the pull-down node PD when the pull-down signal is at the effective pull-down level
  • the pull-up node PU pulls down the power supply voltage to the first power supply voltage terminal VSS.
  • the output circuit 205 is connected to the clock signal terminal CLK, the pull-up node PU and the front-end output terminal, and is configured to set the clock signal end when the pull-up signal at the pull-up node PU is at an effective pull-up level.
  • the clock signal of CLK is output to the front-end output.
  • the repair circuit 102 is connected to the front end output, the frame start signal STV and the output of the GOA unit, and is configured to output a pulse of the front end output to the output of the GOA unit after the frame start signal STV has come, and In other time periods, there is no output at the output of the GOA unit, so that the GOA unit is in an outputless state.
  • Figure 2B shows a detailed block diagram of the single GOA unit of Figure 2A.
  • the pull-down control circuit 203 includes a first pull-down control circuit 2031 and a second pull-down control circuit 2032, and the pull-down node PD includes a first pull-down node PD1 and a second pull-down node PD2.
  • the pull-down circuit 204 includes a first pull-down circuit 2041 and a second pull-down circuit 2042.
  • the first pull-down control circuit 2031 is connected to the second power supply voltage terminal VDD1, the pull-up node PU, the first pull-down node PD1, and the first power supply voltage terminal VSS, and is configured to control whether the first pull-down circuit 2041 operates. For example, the first pull-down control circuit 2031 generates a pull-down signal at the first pull-down node PD1 at the non-active pull-down level when the pull-up signal at the pull-up node PU is at the active pull-up level; and at the pull-up node PU When the pull-up signal is at the non-active pull-up level, the high-level voltage signal VDD1 is supplied to the first pull-down node PD1 in response to the high-level voltage signal VDD1.
  • the second pull-down control circuit 2032 is connected to the third power supply voltage terminal VDD2, the pull-up node PU, the second pull-down node PD2, and the first power supply voltage terminal VSS, and is configured to control whether the second pull-down circuit 2042 operates. For example, the second pull-down control circuit 2032 generates a pull-down signal at the second pull-down node PD2 at the non-active pull-down level when the pull-up signal at the pull-up node PU is at the active pull-up level; and at the pull-up node PU When the pull-up signal is at the inactive pull-up level, the high-level voltage signal VDD2 is supplied to the second pull-down node PD2 in response to the high-level voltage signal VDD2.
  • the first pull-down circuit 2041 is connected to the first pull-down node PD1, the pull-up node PU, the first power voltage terminal VSS and the front-end output, and is configured to be when the pull-down signal at the first pull-down node PD1 is at the effective pull-down level
  • the front end output terminal and the pull-up node PU are pulled down to a power supply voltage of the first power supply voltage terminal VSS.
  • the second pull-down circuit 2042 is connected to the second pull-down node PD, the pull-up node PU, the first power voltage terminal VSS and the front-end output, and is configured to be the front-end when the pull-down signal at the second pull-down node PD2 is at the effective pull-down level
  • the output terminal and the pull-up node PU pull down a power supply voltage to the first power supply voltage terminal VSS.
  • FIG. 3 illustrates an illustration of a single GOA unit with self-healing functionality in accordance with an embodiment of the present disclosure.
  • the input circuit 201 includes an input transistor M1.
  • the gate and the first pole of the input transistor M1 are respectively connected to the signal input terminal INPUT, and the second pole and the pull-up of the input transistor M1.
  • the node PU is connected.
  • the input transistor M1 is turned on, and the input signal of the signal input terminal INPUT is transmitted to the pull-up node PU.
  • the specific implementation structure, control mode, and the like of the input circuit 201 do not constitute a limitation on the embodiments of the present disclosure.
  • the reset circuit 202 includes a reset transistor M2, the gate of the reset transistor M2 is connected to the reset signal terminal RESET, the first pole is connected to the pull-up node PU, and the second pole is connected to the first power supply voltage terminal VSS. .
  • the reset signal at the reset signal terminal RESET is at a high level
  • the reset transistor M2 is turned on, and the pull-up signal at the pull-up node PU is pulled down to the power supply voltage of the first power supply voltage terminal VSS.
  • the reset circuit 202 described above is merely an example, and it may have other structures.
  • the pull-down control circuit 203 includes a first pull-down control circuit 2031 and a second pull-down control circuit 2032
  • the pull-down node PD includes a first pull-down node PD1 and a second pull-down node PD2.
  • the first pull-down control circuit 2031 includes a first pull-down control transistor M5, a second pull-down control transistor M6, a third pull-down control transistor M9, and a fourth pull-down control transistor M8.
  • the gate of the first pull-down control transistor M5 is connected to the first pull-down control node PD_CN1, the first pole is connected to the second power supply voltage terminal VDD1, the second pole is connected to the first pull-down node PD1, and the second pull-down control transistor M6
  • the gate is connected to the pull-up node PU, the first pole is connected to the first pull-down node PD1, the second pole is connected to the first power supply voltage terminal VSS, and the gate and the first pole of the third pull-down control transistor M9 are respectively
  • the second power supply voltage terminal VDD1 is connected, the second pole is connected to the first pull-down control node PD_CN1, the gate of the fourth pull-down control transistor M8 is connected to the pull-up node PU, and the first pole is connected to
  • the second pull-down control circuit 2032 includes a fifth pull-down control transistor M5', a sixth pull-down control transistor M6', a seventh pull-down control transistor M9', and an eighth pull-down control transistor M8'.
  • the gate of the fifth pull-down control transistor M5' is connected to the second pull-down control node PD_CN2, the first pole is connected to the third power supply voltage terminal VDD2, the second pole is connected to the second pull-down node PD2, and the sixth pull-down control crystal is connected.
  • the gate of the tube M6' is connected to the pull-up node PU, the first pole is connected to the second pull-down node PD2, the second pole is connected to the first power supply voltage terminal VSS, and the gate of the seventh pull-down control transistor M9' and the first pole Connected to the third power supply voltage terminal VDD2, the second electrode is connected to the second pull-down control node PD_CN2, the gate of the eighth pull-down control transistor M8' is connected to the pull-up node PU, and the first pole is connected to the second pull-down control node PD_CN2.
  • the second pole is connected to the first power supply voltage terminal VSS.
  • the pull down circuit 204 includes a first pull down circuit 2041 and a second pull down circuit 2042.
  • the first pull-down circuit 2041 includes a first node pull-down transistor M10 and a first output pull-down transistor M11.
  • the gate of the first node pull-down transistor M10 and the gate of the first output pull-down transistor M11 are connected to the first pull-down node PD1.
  • the second pole of the one-stage pull-down transistor M10 and the second pole of the first output pull-down transistor M11 are connected to the first power supply voltage terminal VSS, and the first pole of the first node pull-down transistor M10 is connected to the pull-up node PU, and the first output pull-down The first pole of the transistor M11 is connected to the front end output.
  • the first node pull-down transistor M10 and the first output pull-down transistor M11 are turned on, respectively pulling the pull-up node PU and the front-end output terminal to the first power supply voltage terminal VSS Power supply voltage.
  • the second pull-down circuit 2042 includes a second node pull-down transistor M10' and a second output pull-down transistor M11'.
  • the gate of the second node pull-down transistor M10' and the gate of the second output pull-down transistor M11' are connected to the second pull-down node PD2.
  • the second pole of the second node pull-down transistor M10' and the second pole of the second output pull-down transistor M11' are connected to the first power supply voltage terminal VSS, and the first pole of the second node pull-down transistor M10' is connected to the pull-up node PU
  • the first pole of the second output pull-down transistor M11' is connected to the front end output.
  • the second node pull-down transistor M10' and the second output pull-down transistor M11' are turned on, respectively pulling the pull-up node PU and the front-end output terminal to the first power voltage terminal VSS supply voltage.
  • the pull-down control circuit 203 and the pull-down circuit 204 described above are merely examples, and may have other configurations.
  • the output circuit 205 includes an output transistor M3 and a second capacitor C2, the gate of the output transistor M3 is connected to the pull-up node PU, and the first electrode of the output transistor M3 is connected to the clock signal terminal CLK, and the output transistor The second pole of M3 is connected to the front end output terminal; the first end of the second capacitor C2 is connected to the pull-up node PU, and the second end of the second capacitor C2 is connected to the front end output end.
  • the output transistor M3 is turned on, and the second clock signal of the clock signal terminal CLK is output to the front-end output terminal.
  • the output circuit 205 described above is merely an example, and it may have other structures.
  • the repair circuit 102 includes a first repair control transistor T12, a second repair control transistor T13, a third repair control transistor T14, and a first capacitor C1.
  • the gate and the first pole of the first repair control transistor T12 are connected to the frame start signal STV, and the second pole of the first repair control transistor T12 is connected to the reset node RE.
  • the gate of the second repair control transistor T13 is connected to the reset node RE, the first pole of the second repair control transistor T13 is connected to the front end output terminal, and the second pole of the second repair control transistor T13 is connected to the output terminal of the GOA unit.
  • the first terminal of the first capacitor C1 is connected to the reset node RE, and the second end thereof is connected to the first pole of the third repair control transistor T14.
  • the gate of the third repair control transistor T14 is connected to the output terminal of the next stage GOA unit, and the second electrode of the third repair control transistor T14 is connected to the first power supply voltage terminal VSS.
  • the frame start signal STV turns on the first repair control transistor M12, charging the reset node RE of the GOA unit of each row of gates.
  • the second repair control transistor M13 is turned on, and the output of the front end output end of the first frame is normally output.
  • the output of the front end output turns on the third repair control transistor M14, thereby lowering the level of the reset node RE, cutting off the second repair control transistor M13, and shielding other abnormal outputs. Thereby achieving self-healing function when abnormal output.
  • the repair circuit 102 described above is merely an example, and it may have other structures capable of achieving the same function.
  • the function implementation steps of the repair circuit 102 are as follows:
  • the frame start signal STV causes the first repair control transistor M12 of each row of GOA cells to be turned on, charging the reset node RE, and maintaining a high level through the first capacitor C1.
  • the reset node RE is set high to maintain the second repair control transistor M13 in an on state.
  • the output of the front end output passes through the second repair control transistor M13 in the on state, and outputs a pulse to the output terminal of the GOA unit.
  • the reverse-trigger third repair control transistor M14 pulls down the voltage of the reset node RE.
  • the voltage of the reset node RE is turned off, and the second repair control transistor M13 is turned off.
  • FIG. 4 illustrates a timing diagram of a GOA unit having a self-healing function when a GOA unit is abnormal according to an embodiment of the present disclosure.
  • FIG. 5 illustrates a timing diagram of a GOA unit having a self-healing function when the GOA unit is normal according to an embodiment of the present disclosure.
  • the front end output of the front end GOA unit outputs an abnormality, that is, has a plurality of outputs.
  • the STV turns on the first repair control transistor M12 to charge the reset node RE.
  • the reset node RE is set high to maintain the second repair control transistor M13 in an on state.
  • the output of the front end output passes through the second repair control transistor M13 in the on state, and outputs a pulse to the output terminal of the GOA unit.
  • the reverse-trigger third repair control transistor M14 pulls down the voltage of the reset node RE.
  • the voltage of the reset node RE is turned off, and the second repair control transistor M13 is turned off. Therefore, the reset output is in an output-free state until the next frame start signal STV arrives. Therefore, even if the front-end output generates multiple output faults, the problem of multiple outputs can be repaired by the repair circuit.
  • the driving method of the GOA unit includes: outputting a pulse of the front end output of the front end GOA unit to the output end of the GOA unit when the frame start signal is at the effective input level; and at the start of the frame When the signal is at an inactive input level, there is no output at the output of the GOA unit to cause the GOA unit to be in an outputless state.
  • the front end output end of the front end GOA unit in FIG. 5 does not have an abnormality. At this time, the reset output terminal maintains the normal output of the front end output end.
  • the GOA unit with self-healing function can well solve the problem of abnormal multiple outputs.
  • FIG. 6 shows the overall structure of a GOA driving circuit in accordance with an embodiment of the present disclosure.
  • the GOA driving circuit shown in FIG. 6 includes cascaded N GOA units which are first GOA units to Nth GOA units, where N is an integer greater than or equal to 2. Each stage of the GOA unit can employ the structure described above.
  • the signal input end of the first GOA unit is connected to the frame start signal, and the reset signal end of the Nth GOA unit is connected to the frame start signal.
  • the signal input of each of the second GOA unit to the Nth GOA unit is connected to the output of the upper-level GOA unit adjacent thereto.
  • the reset signal terminal of each of the first GOA unit to the N-1GOA unit is connected to the output terminal of the next-stage GOA unit adjacent thereto.
  • the frame start signal is connected to each level of the GOA unit.
  • the drive signal output ends of the GOA units of each stage are connected to the gate lines.
  • the GOA driving circuit is connected to the corresponding gate line through the driving signal output ends of the GOA units of each stage for sequentially outputting the scanning signals to the corresponding gate lines.
  • the present disclosure also provides a display device including the GOA driving circuit described above.
  • FIG. 7 shows a flow chart of a driving method of a GOA unit according to an embodiment of the present disclosure.
  • the GOA unit includes a front end GOA unit and a repair circuit. As shown in FIG. 7, in step S701, when the frame start signal is at the effective input level, a pulse of the front end output terminal of the front end GOA unit is output to the output terminal of the GOA unit through the repair circuit.
  • step S702 when the frame start signal is at the inactive input level, the output of the GOA unit is outputted by the repair circuit so that the GOA unit is in the no-output state.
  • the frame start signal is a valid input level at the beginning of each frame.
  • the present disclosure adds a self-repairing structure to the existing GOA architecture, and performs reasonable selective output on the front-end output through the turn-on and turn-off of the three TFTs, thereby eliminating multiple output conditions and shielding abnormal interference signals.

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Abstract

一种GOA单元、GOA单元的驱动方法、GOA驱动电路和显示装置，该GOA单元包括：前端GOA单元(101)，连接信号输入端(Input)、复位信号端(RESET)、第一电源电压端(VSS)、第二电源电压端(VDD1)、第三电源电压端(VDD2)、时钟信号端(CLK)以及前端输出端，被配置以在信号输入端(Input)的输入信号处于有效输入电平时，将时钟信号端(CLK)的时钟信号输出到前端输出端；以及修复电路(102)，连接前端输出端、帧起始信号(STV)、第一电源电压端(VSS)以及GOA单元的输出端，被配置以在帧起始信号(STV)处于有效输入电平时，将前端输出端的一个脉冲输出到GOA单元的输出端；以及在帧起始信号(STV)处于非有效输入电平时，使得GOA单元的输出端无输出以使得该GOA单元处于无输出状态。

Description

一种GOA单元及其驱动方法、GOA驱动电路、显示装置 技术领域
本公开涉及显示技术领域，更具体地说，涉及一种具有自修复功能的阵列基板行驱动单元及其驱动方法、包含该GOA单元的GOA驱动电路以及包含该GOA驱动电路的显示装置。
背景技术
目前，栅极驱动装置一般通过阵列工艺形成在液晶显示器的阵列基板上，即阵列基板行驱动(Gate Driver on Array,GOA)工艺，这种集成工艺节省了成本，是未来TFT-LCD的发展趋势。
GOA单元目前仍旧还有许多需要完善的地方，目前GOA单元输出异常绝大部分都是GOA单元多个输出(Multi-Output)，若GOA单元能够通过自身的设计达到自我修复多个输出的功能，提升产品良率，提升产品的抗干扰能力，提升产品品质和可靠性，另一方面增加设计边框(Margin)，从而增加设计的可调整性，降低设计难度。
GOA单元是为了代替栅极驱动器IC的功能，实现成本降低，目前GOA单元的功能还没有达到栅极驱动器IC那么全面稳定。由于制程当中的不稳定性及客户系统对面板时序的要求，GOA单元很可能因为各种各样的原因导致异常输出，即多个输出状况，一旦发生多个输出，由于GOA单元的级联特性，会影响到整个GOA单元的工作发生AD(Abnormal Display异常显示)不良；现有设计中没有针对多个输出进行自我修复的修复电路，所以GOA单元对于异常的工作信号极其敏感且无法修复(重启可恢复)。
发明内容
本公开的另外方面和优点部分将在后面的描述中阐述，还有部分可从描述中明显地看出，或者可以在本公开的实践中得到。
在本公开中，在前端GOA单元后端增加修复电路，在每一帧的开始时，帧起始信号STV会导通第一修复控制晶体管M12，对每一行栅极的GOA单元的复位节点RE充电。当前端GOA单元输出多输出时，由于此时复位节点RE为高电平，导通第二修复控制晶体管M13，第一帧前端输出端的输出正常 输出。同时前端输出端的输出会导通第三修复控制晶体管M14，从而拉低复位节点RE的电平，截止第二修复控制晶体管M13，屏蔽掉其他的异常输出。从而达到异常输出时的自我修复功能。
本公开提供了一种阵列基板行驱动GOA单元，包括：前端GOA单元，连接信号输入端、复位信号端、第一电源电压端、第二电源电压端、第三电源电压端、时钟信号端以及前端输出端，被配置以在信号输入端的输入信号处于有效输入电平时，将时钟信号端的时钟信号输出到前端输出端；以及修复电路，连接前端输出端、帧起始信号、第一电源电压端以及GOA单元的输出端，被配置以在帧起始信号处于有效输入电平时，将前端输出端的一个脉冲输出到GOA单元的输出端；以及在帧起始信号处于非有效输入电平时，使得GOA单元的输出端无输出以使得该GOA单元处于无输出状态。
其中，修复电路包括：第一修复控制晶体管，其栅极和第一极分别与帧起始信号连接，第二极与复位节点连接；第二修复控制晶体管，其栅极和复位节点连接，第一极与前端输出端连接，第二极连接GOA单元的输出端；第一电容器，其第一端与复位节点连接；以及第三修复控制晶体管，其栅极与下一级GOA单元的输出端连接，第一极与第一电容器的第二端连接，第二极与第一电源电压端连接。
其中，前端GOA单元包括：输入电路，连接信号输入端和上拉节点，被配置以在信号输入端的输入信号处于有效输入电平时，将所接收的输入信号传递到上拉节点；复位电路，连接复位信号端、第一电源电压端和上拉节点，被配置以在复位信号端的复位信号处于有效控制电平时将上拉节点处的上拉信号下拉至第一电源电压端的电源电压；下拉控制电路，连接第二电源电压端、第三电源电压端、上拉节点、下拉节点以及第一电源电压端，被配置为控制下拉电路是否进行操作；下拉电路，连接下拉节点、上拉节点、第一电源电压端和前端输出端，被配置以在下拉节点处的下拉信号处于有效下拉电平时将所述前端输出端和所述上拉节点的电压下拉至所述第一电源电压端的电源电压；以及输出电路，连接时钟信号端、上拉节点和前端输出端，被配置以在上拉节点处的上拉信号处于有效上拉电平时将时钟信号端的时钟信号输出到前端输出端。
其中，输入电路包括：输入晶体管，其栅极和第一极与信号输入端连接，第二极与上拉节点连接。
其中，复位电路包括：复位晶体管，其栅极与复位信号端连接，第一极与上拉节点连接，第二极与第一电源电压端连接。
其中，下拉控制电路包括第一下拉控制电路和第二下拉控制电路，其中下拉节点包括第一下拉节点和第二下拉节点。
其中，第一下拉控制电路包括：第一下拉控制晶体管，其栅极和第一下拉控制节点连接，第一极与第二电源电压端连接，第二极与第一下拉节点连接；第二下拉控制晶体管，其栅极与上拉节点连接，第一极与第一下拉节点连接，第二极与第一电源电压端连接；第三下拉控制晶体管，其栅极和第一极分别与第二电源电压端连接，第二极与第一下拉控制节点连接；以及第四下拉控制晶体管，其栅极与上拉节点连接，第一极与第一下拉控制节点连接，第二极与第一电源电压端连接，第二下拉控制电路包括：第五下拉控制晶体管，其栅极和第二下拉控制节点连接，第一极与第三电源电压端连接，第二极与第二下拉节点连接；第六下拉控制晶体管，其栅极与上拉节点连接，第一极与第二下拉节点连接，第二极与第一电源电压端连接；第七下拉控制晶体管，其栅极和第一极分别与第三电源电压端连接，第二极与第二下拉控制节点连接；以及第八下拉控制晶体管，其栅极与上拉节点连接，第一极与第二下拉控制节点连接，第二极与第一电源电压端连接。
其中，下拉电路包括第一下拉电路和第二下拉电路。
第一下拉电路包括：第一节点下拉晶体管，第一节点下拉晶体管的栅极与第一下拉节点连接，第一节点下拉晶体管的第一极与上拉节点连接，第一节点下拉晶体管的第二极与第一电源电压端连接；和第一输出下拉晶体管，第一输出下拉晶体管的栅极与第一下拉节点连接，第一输出下拉晶体管的第一极与前端输出端连接，第一输出下拉晶体管的第二极与第一电源电压端连接；第二下拉电路包括：第二节点下拉晶体管，第二节点下拉晶体管的栅极与第二下拉节点连接，第二节点下拉晶体管的第一极与上拉节点连接，第二节点下拉晶体管的第二极与第一电源电压端连接；和第二输出下拉晶体管，第二输出下拉晶体管的栅极与第二下拉节点连接，第二输出下拉晶体管的第一极与前端输出端连接，第二输出下拉晶体管的第二极与第一电源电压端连接。
其中，输出电路包括：输出晶体管，其栅极与上拉节点连接，第一极与时钟信号端连接，第二极与前端输出端连接；第二电容器，其第一端与上拉 节点连接，第二端与前端输出端连接。
其中，在每一帧的开始时帧起始信号为有效输入电平。
本公开还提供了一种GOA单元的驱动方法，该GOA单元包含如上所述的GOA单元，该方法包括：在帧起始信号处于有效输入电平时，通过修复电路将前端GOA单元的前端输出端的一个脉冲输出到GOA单元的输出端；在帧起始信号处于非有效输入电平时，通过修复电路使得GOA单元的输出端无输出以使得该GOA单元处于无输出状态。
其中，在每一帧的开始时帧起始信号为有效输入电平。
本公开还提供了一种GOA驱动电路，包括级联的N个GOA单元，该N个GOA单元是第一GOA单元至第N GOA单元，每一个GOA单元是如上所述的GOA单元，其中N为大于等于2的整数。
其中在所述级联的N个GOA单元中，第一GOA单元的信号输入端连接帧起始信号，第N GOA单元的复位信号端连接帧起始信号；第二GOA单元至第N GOA单元中的每个GOA单元的信号输入端连接到与其相邻的上一级GOA单元的输出端，所述第一GOA单元至第N-1GOA单元中的每个GOA单元的复位信号端连接到与其相邻的下一级GOA单元的输出端。
其中，在GOA驱动电路中，将帧起始信号接入每一级GOA单元。
本公开还提供了一种显示装置，包括上述的GOA驱动电路。
附图说明
通过结合附图对本公开的优选实施例进行详细描述，本公开的上述和其他目的、特性和优点将会变得更加清楚，其中相同的标号指定相同结构的单元，并且在其中：
图1示出了根据本公开实施例具有自我修复功能的单一GOA单元的框图；
图2A示出了根据本公开实施例具有自我修复功能的单一GOA单元的结构图；
图2B示出了图2A的单一GOA单元的详细框图；
图3示出了根据本公开实施例具有自我修复功能的单一GOA单元的示例电路图；
图4示出了根据本公开实施例当GOA单元异常时具有自我修复功能的 GOA单元的时序图；
图5示出了根据本公开实施例当GOA单元正常时具有自我修复功能的GOA单元的时序图；
图6示出了根据本公开实施例GOA驱动电路的整体结构；
图7示出了根据本公开实施例的GOA单元的驱动方法的流程图。
具体实施方式
下面将参照示出本公开实施例的附图充分描述本公开。然而，本公开可以以许多不同的形式实现，而不应当认为限于这里所述的实施例。相反，提供这些实施例以便使本公开透彻且完整，并且将向本领域技术人员充分表达本公开的范围。在附图中，为了清楚起见放大了组件。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除栅极之外的两极，而将其中一极称为漏极，另一极称为源极。本公开实施例中采用的薄膜晶体管可以为N型晶体管，也可以为P型晶体管。在本公开实施例中，当采用N型薄膜晶体管时，其第一极可以是源极，第二极可以是漏极。在以下实施例中，以薄膜晶体管为N型晶体管为例进行的说明，即栅极的信号是高电平时，薄膜晶体管导通。可以想到，当采用P型晶体管时，需要相应调整驱动信号的时序。
图1示出了根据本公开实施例具有自我修复功能的单一GOA单元的框图。
如图1所示的，在一个实施例中，GOA单元包括前端GOA单元101和修复电路102。在根据本公开的GOA单元中，在前端GOA单元101的输出端之后增加了修复电路102。
在一个实施例中，例如前端GOA单元101连接信号输入端Input、复位信号端RESET、第一电源电压端VSS、第二电源电压端VDD1、第三电源电压端VDD2、时钟信号端CLK以及前端输出端，被配置以在信号输入端的输入信号Input处于有效输入电平时，将时钟信号端CLK的时钟信号输出到前端输出端。
在一个实施例中，例如修复电路102连接前端GOA单元101的前端输 出端、帧起始信号STV、第一电源电压端VSS以及GOA单元的输出端，被配置以在帧起始信号STV处于有效输入电平时，将前端输出端的一个脉冲输出到GOA单元的输出端；以及在帧起始信号STV处于非有效输入电平时，使得GOA单元的输出端无输出以使得该GOA单元处于无输出状态。从而，根据本公开的GOA单元可以滤除掉异常输出和干扰信号。
其中，第一电源电压端VSS是低电源电压端。第二和第三电源电压端VDD1和VDD2是高电源电压端。
图2A示出了根据本公开实施例具有自我修复功能的单一GOA单元的结构图。
如图2A所示的，在一个实施例中，例如前端GOA单元101包括：输入电路201、复位电路202、下拉控制电路203、下拉电路204和输出电路205。
所述输入电路201连接信号输入端Input和上拉节点PU，被配置以在信号输入端的输入信号Input处于有效输入电平时，将所接收的输入信号传递到上拉节点PU。
所述复位电路202连接复位信号端RESET、第一电源电压端VSS和上拉节点PU，被配置以在复位信号端RESET的复位信号处于有效控制电平时将上拉节点PU处的上拉信号下拉至第一电源电压端VSS的电源电压。
所述下拉控制电路203连接第二电源电压端VDD1、第三电源电压端VDD2、上拉节点PU、下拉节点PD1和PD2以及第一电源电压端VSS，被配置为控制下拉电路204是否进行操作。例如，下拉控制电路203在上拉节点PU处的上拉信号处于有效上拉电平时在下拉节点PD处产生处于非有效下拉电平的下拉信号；而在上拉节点PU处的上拉信号处于非有效上拉电平时，响应高电平电压信号VDD1或VDD2，将高电平电压信号VDD1或VDD2提供给下拉节点PD1和PD2。
所述下拉电路204连接下拉节点PD、上拉节点PU、第一电源电压端VSS和前端输出端，被配置以在下拉节点PD处的下拉信号处于有效下拉电平时将所述前端输出端和所述上拉节点PU下拉至所述第一电源电压端VSS的电源电压。
所述输出电路205连接时钟信号端CLK、上拉节点PU和前端输出端，被配置以在上拉节点PU处的上拉信号处于有效上拉电平时将时钟信号端 CLK的时钟信号输出到前端输出端。
所述修复电路102连接前端输出端、帧起始信号STV和GOA单元的输出端，被配置以在帧起始信号STV来了之后，将前端输出端的一个脉冲输出到GOA单元的输出端，并且在其他时间段内，使得GOA单元的输出端无输出，以使得该GOA单元处于无输出状态。
图2B示出了图2A的单一GOA单元的详细框图。
如图2B所示，下拉控制电路203包括第一下拉控制电路2031和第二下拉控制电路2032，并且下拉节点PD包括第一下拉节点PD1和第二下拉节点PD2。
下拉电路204包括第一下拉电路2041和第二下拉电路2042。
第一下拉控制电路2031连接第二电源电压端VDD1、上拉节点PU、第一下拉节点PD1以及第一电源电压端VSS，被配置为控制第一下拉电路2041是否进行操作。例如，第一下拉控制电路2031在上拉节点PU处的上拉信号处于有效上拉电平时在第一下拉节点PD1处产生处于非有效下拉电平的下拉信号；而在上拉节点PU处的上拉信号处于非有效上拉电平时，响应高电平电压信号VDD1，将高电平电压信号VDD1提供给第一下拉节点PD1。
第二下拉控制电路2032连接第三电源电压端VDD2、上拉节点PU、第二下拉节点PD2以及第一电源电压端VSS，被配置为控制第二下拉电路2042是否进行操作。例如，第二下拉控制电路2032在上拉节点PU处的上拉信号处于有效上拉电平时在第二下拉节点PD2处产生处于非有效下拉电平的下拉信号；而在上拉节点PU处的上拉信号处于非有效上拉电平时，响应高电平电压信号VDD2，将高电平电压信号VDD2提供给第二下拉节点PD2。
第一下拉电路2041连接第一下拉节点PD1、上拉节点PU、第一电源电压端VSS和前端输出端，被配置以在第一下拉节点PD1处的下拉信号处于有效下拉电平时将所述前端输出端和所述上拉节点PU下拉至所述第一电源电压端VSS的电源电压。
第二下拉电路2042连接第二下拉节点PD、上拉节点PU、第一电源电压端VSS和前端输出端，被配置以在第二下拉节点PD2处的下拉信号处于有效下拉电平时将所述前端输出端和所述上拉节点PU下拉至所述第一电源电压端VSS的电源电压。
图3示出了根据本公开实施例具有自我修复功能的单一GOA单元的示 例电路图。
下面以图3中的晶体管均为在栅极输入高电平时导通的N型晶体管为例进行说明。
如图3所示，在一个实施例中，例如，输入电路201包括输入晶体管M1，输入晶体管M1的栅极和第一极分别与信号输入端INPUT连接，输入晶体管M1的第二极与上拉节点PU连接。在信号输入端INPUT的输入信号处于高电平时，输入晶体管M1导通，将信号输入端INPUT的输入信号传递到上拉节点PU。输入电路201的具体实现结构和控制方式等不构成对本公开实施例的限制。
在一个实施例中，例如，复位电路202包括复位晶体管M2，复位晶体管M2的栅极与复位信号端RESET连接，第一极与上拉节点PU连接，第二极与第一电源电压端VSS连接。在复位信号端RESET处的复位信号处于高电平时，复位晶体管M2导通，将上拉节点PU处的上拉信号下拉至第一电源电压端VSS的电源电压。上述的复位电路202仅仅是示例，其还可以具有其它结构。
在一个实施例中，例如，下拉控制电路203包括第一下拉控制电路2031和第二下拉控制电路2032，下拉节点PD包括第一下拉节点PD1和第二下拉节点PD2。
第一下拉控制电路2031包括第一下拉控制晶体管M5、第二下拉控制晶体管M6、第三下拉控制晶体管M9和第四下拉控制晶体管M8。第一下拉控制晶体管M5的栅极和第一下拉控制节点PD_CN1连接，第一极与第二电源电压端VDD1连接，第二极与第一下拉节点PD1连接；第二下拉控制晶体管M6的栅极与上拉节点PU连接，第一极与第一下拉节点PD1连接，第二极与第一电源电压端VSS连接；第三下拉控制晶体管M9的栅极和第一极分别与第二电源电压端VDD1连接，第二极与第一下拉控制节点PD_CN1连接；第四下拉控制晶体管M8的栅极与上拉节点PU连接，第一极与第一下拉控制节点PD_CN1连接，第二极与第一电源电压端VSS连接。
第二下拉控制电路2032包括第五下拉控制晶体管M5’、第六下拉控制晶体管M6’、第七下拉控制晶体管M9’和第八下拉控制晶体管M8’。第五下拉控制晶体管M5’的栅极和第二下拉控制节点PD_CN2连接，第一极与第三电源电压端VDD2连接，第二极与第二下拉节点PD2连接；第六下拉控制晶体 管M6’的栅极与上拉节点PU连接，第一极与第二下拉节点PD2连接，第二极与第一电源电压端VSS连接；第七下拉控制晶体管M9’的栅极和第一极分别与第三电源电压端VDD2连接，第二极与第二下拉控制节点PD_CN2连接；第八下拉控制晶体管M8’的栅极与上拉节点PU连接，第一极与第二下拉控制节点PD_CN2连接，第二极与第一电源电压端VSS连接。
在一个实施例中，例如，下拉电路204包括第一下拉电路2041和第二下拉电路2042。
第一下拉电路2041包括第一节点下拉晶体管M10和第一输出下拉晶体管M11，第一节点下拉晶体管M10的栅极和第一输出下拉晶体管M11的栅极与第一下拉节点PD1连接，第一节点下拉晶体管M10的第二极和第一输出下拉晶体管M11的第二极与第一电源电压端VSS连接，第一节点下拉晶体管M10的第一极与上拉节点PU连接，第一输出下拉晶体管M11的第一极与前端输出端连接。在第一下拉节点PD1处的下拉信号处于高电平时，第一节点下拉晶体管M10和第一输出下拉晶体管M11导通，分别将上拉节点PU和前端输出端下拉至第一电源电压端VSS的电源电压。
第二下拉电路2042包括第二节点下拉晶体管M10’和第二输出下拉晶体管M11’，第二节点下拉晶体管M10’的栅极和第二输出下拉晶体管M11’的栅极与第二下拉节点PD2连接，第二节点下拉晶体管M10’的第二极和第二输出下拉晶体管M11’的第二极与第一电源电压端VSS连接，第二节点下拉晶体管M10’的第一极与上拉节点PU连接，第二输出下拉晶体管M11’的第一极与前端输出端连接。在第二下拉节点PD2处的下拉信号处于高电平时，第二节点下拉晶体管M10’和第二输出下拉晶体管M11’导通，分别将上拉节点PU和前端输出端下拉至第一电源电压端VSS的电源电压。
上述的下拉控制电路203和下拉电路204仅仅是示例，其还可以具有其它结构。
在一个实施例中，例如，输出电路205包括输出晶体管M3和第二电容器C2，输出晶体管M3的栅极与上拉节点PU连接，输出晶体管M3的第一极与时钟信号端CLK连接，输出晶体管M3的第二极与前端输出端连接；第二电容器C2的第一端与上拉节点PU连接，第二电容器C2的第二端与前端输出端连接。在上拉节点PU处的上拉信号处于高电平时，输出晶体管M3导通，将时钟信号端CLK的第二时钟信号输出到前端输出端。
上述的输出电路205仅仅是示例，其还可以具有其它结构。
在一个实施例中，例如，修复电路102包括第一修复控制晶体管T12、第二修复控制晶体管T13、第三修复控制晶体管T14和第一电容器C1。第一修复控制晶体管T12的栅极和第一极与帧起始信号STV连接，第一修复控制晶体管T12的第二极与复位节点RE连接。第二修复控制晶体管T13的栅极和复位节点RE连接，第二修复控制晶体管T13的第一极与前端输出端连接，第二修复控制晶体管T13的第二极连接GOA单元的输出端。第一电容器C1第一端与复位节点RE连接，其第二端与第三修复控制晶体管T14的第一极连接。第三修复控制晶体管T14的栅极与下一级GOA单元的输出端连接，第三修复控制晶体管T14的第二极与第一电源电压端VSS连接。
在每一帧的开始时，帧起始信号STV会导通第一修复控制晶体管M12，对每一行栅极的GOA单元的复位节点RE充电。当前端GOA单元输出多输出时，由于此时复位节点RE为高电平，导通第二修复控制晶体管M13，第一帧前端输出端的输出正常输出。同时前端输出端的输出会导通第三修复控制晶体管M14，从而拉低复位节点RE的电平，截止第二修复控制晶体管M13，屏蔽掉其他的异常输出。从而达到异常输出时的自我修复功能。
上述的修复电路102仅仅是示例，其还可以具有能够实现相同功能的其它结构。
修复电路102的功能实现步骤如下：
每一帧开始时，帧起始信号STV使得每一行GOA单元的第一修复控制晶体管M12导通，给复位节点RE充电，通过第一电容器C1维持高电平。
复位节点RE置高电平使得第二修复控制晶体管M13维持导通状态。
此时前端输出端的输出通过导通状态的第二修复控制晶体管M13，输出一个脉冲到GOA单元的输出端。
前端输出端输出一个脉冲后反向导通第三修复控制晶体管M14拉低复位节点RE的电压。
复位节点RE的电压置低，截止第二修复控制晶体管M13。
由于第二修复控制晶体管M13截止，在下一个帧起始信号STV到来之前该行GOA单元锁定无输出状态。
图4示出了根据本公开实施例当GOA单元异常时具有自我修复功能的GOA单元的时序图。
图5示出了根据本公开实施例当GOA单元正常时具有自我修复功能的GOA单元的时序图。
参照图4，前端GOA单元的前端输出端输出异常，即具有多个输出。在前端输出端输出第一个脉冲期间，STV导通第一修复控制晶体管M12，给复位节点RE充电。复位节点RE置高电平使得第二修复控制晶体管M13维持导通状态。此时前端输出端的输出通过导通状态的第二修复控制晶体管M13，输出一个脉冲到GOA单元的输出端。前端输出端输出一个脉冲后反向导通第三修复控制晶体管M14拉低复位节点RE的电压。复位节点RE的电压置低，截止第二修复控制晶体管M13。因此，在下一个帧起始信号STV到来之前复位输出端处于无输出状态。因此，即使前端输出端产生多输出故障，通过修复电路也能够修复多输出的问题。
也即，根据本公开实施例的GOA单元的驱动方法包括：在帧起始信号处于有效输入电平时，将前端GOA单元的前端输出端的一个脉冲输出到GOA单元的输出端；以及在帧起始信号处于非有效输入电平时，使得GOA单元的输出端无输出以使得该GOA单元处于无输出状态。
参照图5，图5中的前端GOA单元的前端输出端未出现异常，此时，复位输出端保持了前端输出端的正常输出。
通过图4和图5的时序图可知，根据本公开实施例的具有自我修复功能的GOA单元能够很好地解决异常多个输出的问题。
图6示出了根据本公开实施例GOA驱动电路的整体结构。
图6所示的GOA驱动电路包括级联的N个GOA单元，该N个GOA单元是第一GOA单元至第N GOA单元，其中N为大于等于2的整数。每级GOA单元都可以采用上文中所描述的结构。
其中在所述级联的N个GOA单元中，
第一GOA单元的信号输入端连接帧起始信号，第N GOA单元的复位信号端连接帧起始信号。
第二GOA单元至第N GOA单元中的每个GOA单元的信号输入端连接到与其相邻的上一级GOA单元的输出端。
所述第一GOA单元至第N-1GOA单元中的每个GOA单元的复位信号端连接到与其相邻的下一级GOA单元的输出端。
其中，在GOA驱动电路中，将帧起始信号接入每一级GOA单元。
各级GOA单元的驱动信号输出端与栅线相连。
上述GOA驱动电路通过各级GOA单元的驱动信号输出端与对应的栅线连接，用于顺序地向对应的栅线输出扫描信号。
本公开还提供了一种包括上述的GOA驱动电路的显示装置。
图7示出了根据本公开实施例的GOA单元的驱动方法的流程图。
该GOA单元包括前端GOA单元和修复电路。如图7所示，在步骤S701，在帧起始信号处于有效输入电平时，通过修复电路将前端GOA单元的前端输出端的一个脉冲输出到GOA单元的输出端。
在步骤S702，在帧起始信号处于非有效输入电平时，通过修复电路使得GOA单元的输出端无输出以使得该GOA单元处于无输出状态。
其中，在每一帧的开始时帧起始信号为有效输入电平。
本公开在现有的GOA架构上增加了自修复结构，通过3个TFT的导通和截止对前端输出进行合理选择性输出，从而达到消除多个输出状况和屏蔽异常干扰信号。提升产品品质，产品良率及产品可靠性；提升设计边框，降低设计难度；通过对前端输出端输出后的信号进行处理，达到对GOA单元的自修复功能和抗干扰功能。
除非另有定义，这里使用的所有术语(包括技术和科学术语)具有与本公开所属领域的普通技术人员共同理解的相同含义。还应当理解，诸如在通常字典里定义的那些术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
上面是对本公开的说明，而不应被认为是对其的限制。尽管描述了本公开的若干示例性实施例，但本领域技术人员将容易地理解，在不背离本公开的新颖教学和优点的前提下可以对示例性实施例进行许多修改。因此，所有这些修改都意图包含在权利要求书所限定的本公开范围内。应当理解，上面是对本公开的说明，而不应被认为是限于所公开的特定实施例，并且对所公开的实施例以及其他实施例的修改意图包含在所附权利要求书的范围内。本公开由权利要求书及其等效物限定。
本申请要求于2017年03月30日递交的中国专利申请第201710203914.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种GOA单元，包括：
    前端GOA单元，连接信号输入端、复位信号端、第一电源电压端、第二电源电压端、第三电源电压端、时钟信号端以及前端输出端，被配置以在信号输入端的输入信号处于有效输入电平时，将时钟信号端的时钟信号输出到前端输出端；以及
    修复电路，连接前端输出端、帧起始信号、第一电源电压端以及GOA单元的输出端，被配置以在帧起始信号处于有效输入电平时，将前端输出端的一个脉冲输出到GOA单元的输出端；以及在帧起始信号处于非有效输入电平时，使得GOA单元的输出端无输出以使得该GOA单元处于无输出状态。
  2. 根据权利要求1所述的GOA单元，其中，修复电路包括：
    第一修复控制晶体管，其栅极和第一极分别与帧起始信号连接，第二极与复位节点连接；
    第二修复控制晶体管，其栅极和复位节点连接，第一极与前端输出端连接，第二极连接GOA单元的输出端；
    第一电容器，其第一端与复位节点连接；以及
    第三修复控制晶体管，其栅极与下一级GOA单元的输出端连接，第一极与第一电容器的第二端连接，第二极与第一电源电压端连接。
  3. 根据权利要求2所述的GOA单元，其中，前端GOA单元包括：
    输入电路，连接信号输入端和上拉节点，被配置以在信号输入端的输入信号处于有效输入电平时，将所接收的输入信号传递到上拉节点；
    复位电路，连接复位信号端、第一电源电压端和上拉节点，被配置以在复位信号端的复位信号处于有效控制电平时将上拉节点处的上拉信号下拉至第一电源电压端的电源电压；
    下拉控制电路，连接第二电源电压端、第三电源电压端、上拉节点、下拉节点以及第一电源电压端，被配置为控制下拉电路是否进行操作；
    下拉电路，连接下拉节点、上拉节点、第一电源电压端和前端输出端，被配置以在下拉节点处的下拉信号处于有效下拉电平时将所述前端输出端和所述上拉节点的电压下拉至所述第一电源电压端的电源电压；以及
    输出电路，连接时钟信号端、上拉节点和前端输出端，被配置以在上拉节点处的上拉信号处于有效上拉电平时将时钟信号端的时钟信号输出到前端输出端。
  4. 根据权利要求3所述的GOA单元，其中，输入电路包括：
    输入晶体管，其栅极和第一极与信号输入端连接，第二极与上拉节点连接。
  5. 根据权利要求3所述的GOA单元，其中，复位电路包括：
    复位晶体管，其栅极与复位信号端连接，第一极与上拉节点连接，第二极与第一电源电压端连接。
  6. 根据权利要求3所述的GOA单元，其中，下拉控制电路包括第一下拉控制电路和第二下拉控制电路，其中下拉节点包括第一下拉节点和第二下拉节点。
  7. 根据权利要求6所述的GOA单元，其中，第一下拉控制电路包括：
    第一下拉控制晶体管，其栅极和第一下拉控制节点连接，第一极与第二电源电压端连接，第二极与第一下拉节点连接；
    第二下拉控制晶体管，其栅极与上拉节点连接，第一极与第一下拉节点连接，第二极与第一电源电压端连接；
    第三下拉控制晶体管，其栅极和第一极分别与第二电源电压端连接，第二极与第一下拉控制节点连接；以及
    第四下拉控制晶体管，其栅极与上拉节点连接，第一极与第一下拉控制节点连接，第二极与第一电源电压端连接，
    第二下拉控制电路包括：
    第五下拉控制晶体管，其栅极和第二下拉控制节点连接，第一极与第三电源电压端连接，第二极与第二下拉节点连接；
    第六下拉控制晶体管，其栅极与上拉节点连接，第一极与第二下拉节点连接，第二极与第一电源电压端连接；
    第七下拉控制晶体管，其栅极和第一极分别与第三电源电压端连接，第二极与第二下拉控制节点连接；以及
    第八下拉控制晶体管，其栅极与上拉节点连接，第一极与第二下拉控制节点连接，第二极与第一电源电压端连接。
  8. 根据权利要求3所述的GOA单元，其中，下拉电路包括第一下拉电 路和第二下拉电路。
  9. 根据权利要求8所述的GOA单元，其中，第一下拉电路包括：
    第一节点下拉晶体管，第一节点下拉晶体管的栅极与第一下拉节点连接，第一节点下拉晶体管的第一极与上拉节点连接，第一节点下拉晶体管的第二极与第一电源电压端连接；和
    第一输出下拉晶体管，第一输出下拉晶体管的栅极与第一下拉节点连接，第一输出下拉晶体管的第一极与前端输出端连接，第一输出下拉晶体管的第二极与第一电源电压端连接；
    第二下拉电路包括：
    第二节点下拉晶体管，第二节点下拉晶体管的栅极与第二下拉节点连接，第二节点下拉晶体管的第一极与上拉节点连接，第二节点下拉晶体管的第二极与第一电源电压端连接；和
    第二输出下拉晶体管，第二输出下拉晶体管的栅极与第二下拉节点连接，第二输出下拉晶体管的第一极与前端输出端连接，第二输出下拉晶体管的第二极与第一电源电压端连接。
  10. 根据权利要求3所述的GOA单元，其中，输出电路包括：
    输出晶体管，其栅极与上拉节点连接，第一极与时钟信号端连接，第二极与前端输出端连接；
    第二电容器，其第一端与上拉节点连接，第二端与前端输出端连接。
  11. 根据权利要求1-10中任一项所述的GOA单元，其中，在每一帧的开始时帧起始信号为有效输入电平。
  12. 一种GOA单元的驱动方法，该GOA单元包含如权利要求1-11的任意一项所述的GOA单元，该方法包括：
    在帧起始信号处于有效输入电平时，通过修复电路将前端GOA单元的前端输出端的一个脉冲输出到GOA单元的输出端；
    在帧起始信号处于非有效输入电平时，通过修复电路使得GOA单元的输出端无输出以使得该GOA单元处于无输出状态。
  13. 根据权利要求12所述的驱动方法，其中，在每一帧的开始时帧起始信号为有效输入电平。
  14. 一种GOA驱动电路，包括级联的N个GOA单元，该N个GOA单元是第一GOA单元至第N GOA单元，每一个GOA单元是如权利要求1至 11中任一项所述的GOA单元，其中N为大于等于2的整数。
  15. 根据权利要求14的GOA驱动电路，其中在所述级联的N个GOA单元中，
    第一GOA单元的信号输入端连接帧起始信号，第N GOA单元的复位信号端连接帧起始信号；
    第二GOA单元至第N GOA单元中的每个GOA单元的信号输入端连接到与其相邻的上一级GOA单元的输出端，
    所述第一GOA单元至第N-1GOA单元中的每个GOA单元的复位信号端连接到与其相邻的下一级GOA单元的输出端。
  16. 根据权利要求15的GOA驱动电路，其中，在GOA驱动电路中，将帧起始信号接入每一级GOA单元。
  17. 一种显示装置，包括根据权利要求14-16的任何一个所述的GOA驱动电路。
PCT/CN2017/107689 2017-03-30 2017-10-25 一种goa单元及其驱动方法、goa驱动电路、显示装置 Ceased WO2018176823A1 (zh)

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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11436973B2 (en) * 2018-12-13 2022-09-06 Shenzhen Royole Technologies Co., Ltd. Repairable GOA drive system, driving method for GOA circuit, and display panel
CN110459189B (zh) * 2019-08-21 2021-10-12 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN111223452B (zh) * 2020-03-18 2021-07-23 深圳市华星光电半导体显示技术有限公司 Goa电路
US11694631B2 (en) * 2021-09-03 2023-07-04 Lg Display Co., Ltd. Gate driving circuit having a repair circuit and display device including the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010116778A1 (ja) * 2009-04-08 2010-10-14 シャープ株式会社 シフトレジスタおよびそれを備えた表示装置、ならびにシフトレジスタの駆動方法
US20110157030A1 (en) * 2009-12-31 2011-06-30 Amlogic Co., Ltd. Methods and Systems for Data Serialization
CN104866141A (zh) * 2015-06-10 2015-08-26 京东方科技集团股份有限公司 触控驱动电路、显示装置及其驱动方法
CN105976755A (zh) * 2016-07-19 2016-09-28 京东方科技集团股份有限公司 一种显示驱动电路及其控制方法、显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180226A (ja) 1984-09-28 1986-04-23 Toshiba Corp アクテイブ・マトリツクス駆動装置
DE69326419T2 (de) * 1992-12-10 2000-02-17 Sharp K.K., Osaka Flache Anzeigevorrichtung und Verfahren zu ihrer Herstellung
JP4659180B2 (ja) * 2000-07-12 2011-03-30 シャープ株式会社 表示装置
CN102654982B (zh) * 2011-05-16 2013-12-04 京东方科技集团股份有限公司 移位寄存器单元电路、移位寄存器、阵列基板及液晶显示器
CN102651187B (zh) * 2011-05-16 2014-09-24 京东方科技集团股份有限公司 移位寄存器单元电路、移位寄存器、阵列基板及液晶显示器
CN103208263B (zh) * 2013-03-14 2015-03-04 京东方科技集团股份有限公司 移位寄存器、显示装置、栅极驱动电路及驱动方法
CN103680451B (zh) * 2013-12-18 2015-12-30 深圳市华星光电技术有限公司 用于液晶显示的goa电路及显示装置
CN103680387B (zh) * 2013-12-24 2016-08-31 合肥京东方光电科技有限公司 一种移位寄存器及其驱动方法、显示装置
CN103730094B (zh) * 2013-12-30 2016-02-24 深圳市华星光电技术有限公司 Goa电路结构
CN103778896B (zh) * 2014-01-20 2016-05-04 深圳市华星光电技术有限公司 集成栅极驱动电路及具有集成栅极驱动电路的显示面板
CN104008739B (zh) * 2014-05-20 2017-04-12 深圳市华星光电技术有限公司 一种扫描驱动电路和一种液晶显示装置
CN104318888B (zh) * 2014-11-06 2017-09-15 京东方科技集团股份有限公司 阵列基板栅极驱动单元、方法、电路和显示装置
CN104537977B (zh) * 2015-01-20 2017-08-11 京东方科技集团股份有限公司 一种goa单元及驱动方法、goa电路和显示装置
CN105390116B (zh) * 2015-12-28 2018-04-20 深圳市华星光电技术有限公司 栅极驱动电路
CN106448536B (zh) * 2016-10-31 2019-05-14 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路、显示面板及驱动方法
CN106486082B (zh) * 2017-01-03 2020-03-31 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010116778A1 (ja) * 2009-04-08 2010-10-14 シャープ株式会社 シフトレジスタおよびそれを備えた表示装置、ならびにシフトレジスタの駆動方法
US20110157030A1 (en) * 2009-12-31 2011-06-30 Amlogic Co., Ltd. Methods and Systems for Data Serialization
CN104866141A (zh) * 2015-06-10 2015-08-26 京东方科技集团股份有限公司 触控驱动电路、显示装置及其驱动方法
CN105976755A (zh) * 2016-07-19 2016-09-28 京东方科技集团股份有限公司 一种显示驱动电路及其控制方法、显示装置

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