WO2018201692A1 - 电致发光显示面板、其制作方法及显示装置 - Google Patents

电致发光显示面板、其制作方法及显示装置 Download PDF

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Publication number
WO2018201692A1
WO2018201692A1 PCT/CN2017/111316 CN2017111316W WO2018201692A1 WO 2018201692 A1 WO2018201692 A1 WO 2018201692A1 CN 2017111316 W CN2017111316 W CN 2017111316W WO 2018201692 A1 WO2018201692 A1 WO 2018201692A1
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WIPO (PCT)
Prior art keywords
display panel
electrode
electroluminescent display
resistance reducing
reducing electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/111316
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English (en)
French (fr)
Inventor
王磊
玄明花
杨盛际
卢鹏程
肖丽
付杰
陈小川
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to JP2019547277A priority Critical patent/JP7034170B2/ja
Priority to US15/773,057 priority patent/US10535726B2/en
Priority to EP17908182.3A priority patent/EP3621114B1/en
Publication of WO2018201692A1 publication Critical patent/WO2018201692A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape

Definitions

  • the present application relates to the field of display technologies, and in particular, to an electroluminescent display panel, a method for fabricating the same, and a display device.
  • OLED Organic Light-Emitting Diode
  • the electroluminescent display panel generally includes a substrate, a pixel driving circuit disposed on the substrate, an anode disposed on the pixel driving circuit, and a hole injection layer disposed on the anode, disposed in the hole injection layer. a hole transporting layer, a light emitting layer disposed on the hole transporting layer, an electron transporting layer disposed on the light emitting layer, and an electron injecting layer disposed on the electron transporting layer, disposed on the electron injecting layer a cathode, and an encapsulation layer disposed over the cathode.
  • a superposed film layer of a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer is referred to as an organic light emitting material layer, and an anode, an organic light emitting material layer, and a cathode are in contact with each other.
  • the electroluminescence display panel must be driven by the pixel driving circuit to realize the screen display.
  • embodiments of the present disclosure provide an electroluminescent display panel, a method of fabricating the same, and a display device.
  • An electroluminescent display panel includes: a substrate, a plurality of pixel units disposed on the substrate, a pixel driving circuit electrically connected to each of the pixel units, and a plurality of signal lines electrically connected to the pixel driving circuit; further comprising:
  • a resistance reducing electrode disposed in a different layer from at least one of the signal lines and connected in parallel.
  • the signal line extends in a first direction, and the signal line is configured to transmit a constant voltage signal.
  • the resistance reducing electrode extends in a first direction, or the resistance reducing electrode extends in a second direction; wherein the first direction and the There is an angle in the second direction.
  • the resistance reducing electrode has a grid structure.
  • the resistance reducing electrode and the signal line are electrically connected through a plurality of via holes.
  • the resistance reduction power An orthographic projection of the pole on the base substrate and an orthographic projection of the pixel defining layer on the base substrate have overlapping regions.
  • an orthographic projection of the resistance reducing electrode on the substrate substrate and an orthographic projection of each of the pixel units on the substrate substrate Do not overlap each other.
  • the pixel unit includes a first electrode, a second electrode, and a light emitting layer between the first electrode and the second electrode;
  • the resistance reducing electrode is disposed in the same layer as the first electrode, or the resistance reducing electrode is disposed in the same layer as the second electrode.
  • the resistance reducing electrode is disposed in a different layer from the pixel unit.
  • the method further includes: an insulating layer disposed between the resistance reducing electrode and the anode.
  • the resistance reducing electrode is located between the pixel unit and the pixel driving circuit.
  • a display device includes the above electroluminescent display panel.
  • a resistance reducing electrode disposed in a different layer from the signal line is formed, and the resistance reducing electrode is connected to the signal line.
  • forming the resistance reducing electrode disposed in a different layer from the signal line is specifically:
  • FIG. 1 is a schematic structural view of a 2T1C pixel circuit in the prior art
  • FIG. 2 is a schematic diagram of an arrangement of anodes of each pixel unit in an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a resistance reducing electrode in an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 4 is a second structural schematic diagram of a resistance reducing electrode in an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 5 is a third structural schematic diagram of a resistance reducing electrode in an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 6 is a fourth structural schematic diagram of a resistance reducing electrode in an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 7 is a cross-sectional structural diagram of an electroluminescent display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method for fabricating an electroluminescent display panel according to an embodiment of the present disclosure.
  • FIG. 1 shows a 2T1C pixel driving circuit including two TFT1, TFT2 having a switching function and a capacitor for storing charges (Capacitance, C) for driving electroluminescence. Display panel.
  • the gate line Gate supplies an ON signal to the TFT 1
  • the TFT 1 is turned on, and then the TFT 1 selectively connects the data voltage signal supplied from the data line Data to the gate of the TFT 2, and stores the data voltage signal through the capacitor C.
  • the stored data voltage signal is converted into a current signal flowing through the TFT2 by the TFT2, and the TFT2 and the OLED are connected in series, and the current signal flowing through the TFT2 is a current signal when the OLED is in operation.
  • VDD DC high-level signal line of the vertical wiring which is usually disposed in the same layer as the data line Data
  • VDD DC high-level signal line
  • the molybdenum metal resistivity of the DC high-level lateral signal line is much larger than that of the direct current.
  • the aluminum metal resistivity of the high-level vertical signal line, so the lateral wiring makes the signal load of the DC high-level signal line greatly increased.
  • the panel will cause signal delay due to the large load, which greatly reduces the display quality of the electroluminescent display panel.
  • electroluminescent display panels have shown a trend of increasing size and higher resolution and refresh rate.
  • Increasing display panel size, higher resolution and refresh rate make the signal load of signal lines such as gate lines and data lines connected to the pixel driving circuit larger and larger, which seriously affects the electroluminescent display panel. Display quality.
  • embodiments of the present disclosure provide an electroluminescent display panel, a method of fabricating the same, and a display device.
  • the present disclosure will be further described in detail with reference to the accompanying drawings in the claims. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without departing from the inventive scope are the scope of the disclosure.
  • An electroluminescent display panel includes: a substrate substrate, a plurality of pixel units disposed on the substrate, a pixel driving circuit electrically connected to each pixel unit, and a pixel driving circuit a plurality of signal lines connected in a sexual connection; and, as shown in FIG. 3 and FIG. 4, further comprising:
  • the resistance reducing electrode 301 and the signal line are disposed and electrically connected in different layers, that is, the falling resistance electrode 301 is connected in parallel with each signal line, the signal lines can be reduced.
  • the resistance thereby reducing the signal load of each signal line, improves the display quality of the electroluminescent display panel.
  • the embodiment of the present disclosure provides In the above electroluminescent display panel, a resistance reducing electrode connected in parallel to each of the signal lines is provided.
  • the signal line extends in the first direction, and the signal line is configured to transmit the constant voltage signal.
  • the first direction is generally parallel to the direction of the short side of the display panel.
  • each signal line may be a DC high level lateral signal line. That is, the resistance of each DC high-level horizontal signal line can be reduced by setting a falling-resistance electrode which is disposed separately and electrically connected to each of the DC high-level lateral signal lines, so as to improve the overall uniformity of the display screen and improve the display screen. The effect of quality.
  • the resistance of the DC high-level lateral signal line can be reduced by providing the resistance-reducing electrode; but also the resistance-reducing electrode can be disposed to reduce other The resistance of the signal line, for example, a gate line, a data line, a common electrode line, a clock signal line, or a touch signal line, to improve the display quality of the electroluminescence display panel.
  • the signal line is a DC high-level horizontal signal line.
  • the pixel driving circuit is generally located between the substrate substrate and the pixel unit, and the pixel driving circuit may be a pixel of any structure for driving the pixel unit to emit light.
  • the driving circuit for example, the 2T1C pixel driving circuit shown in FIG. 1 may of course be a pixel driving circuit of another structure having an internal compensation function or an external compensation function, which is not limited herein.
  • the pixel unit 11 mainly includes a first electrode, a second electrode, and a light emitting layer between the first electrode and the second electrode. 203.
  • One of the first electrode and the second electrode is the anode 201 and the other is the cathode 202.
  • the pixel driving circuit 12 is connected to the anode 201, which is generally a common electrode layer.
  • Each of the signal lines 13 is generally disposed between the pixel unit 11 and the base substrate 10.
  • the base substrate may be a flexible substrate substrate, for example, the material is polyvinyl ether phthalate, polyethylene naphthalate. , polycarbonate, polyarylate, polyetherimide, polyether sulfone or polyimide, etc.
  • the heat-resistant and durable plastic substrate; or a rigid substrate, such as a glass substrate, is not limited herein.
  • the anti-resistance electrode 301 can be implemented in various manners.
  • the anti-resistance electrode 301 extends along the first direction;
  • the resistance reducing electrode 301 extends in the second direction; wherein the first direction has an angle with the second direction.
  • the first direction is taken as an example of the row direction
  • the second direction is taken as an example of the column direction in FIG. 3, but the present invention is not limited thereto.
  • the resistance-reducing electrode 301 has a grid structure, which is not limited herein. Moreover, the resistance of the resistance-reducing electrode 301 having a lattice structure is smaller than that of the resistance-reducing electrode 301 composed of the wiring extending in the direction of extension, and the resistance of the DC-level horizontal signal line can be further reduced, thereby improving the electric power.
  • the display quality of the light-emitting display panel. 3 to 5 only show the relative positional relationship between the anode 201 and the resistance reducing electrode 301.
  • the resistance reducing electrode 301 having a grid structure is adopted.
  • the arrangement and shape of the pixel unit are not limited.
  • the shape of the anode 201 in the pixel unit is to match the substrate.
  • the layout of the gate lines is designed to be arranged. Therefore, it can be understood that the shape of the anode 201 can also be a rectangle in FIG.
  • the shape of the anti-resistance electrode may be various, for example, may be a straight line, a broken line or a wavy line, and may be specifically performed according to actual needs and process conditions. Settings, not limited here.
  • a resistance reducing electrode in order to obtain a resistance reducing electrode having a small resistance, a resistance reducing electrode can be formed using a metal material.
  • the material of the resistance-reducing electrode may be one of magnesium, aluminum, copper, silver or a combination of alloys having a small electrical resistivity, which is not limited herein.
  • the resistance reducing electrode 301 and the DC high-level lateral signal line may pass through multiple The vias 302 are electrically connected.
  • This setting is equivalent to dc high-level lateral signal lines and constitutes a reduced-resistance
  • the plurality of metal resistors of the pole 301 are connected in parallel, thereby minimizing the resistance of the DC high-level transverse signal line, thereby greatly reducing the signal load of the DC high-level transverse signal line, and significantly improving the display of the electroluminescent display panel. quality.
  • the resistance-reducing electrode 301 is preferably disposed on the base substrate 10.
  • the orthographic projection of the gap between the respective pixel units 11 in the orthographic projection on the base substrate 10, that is, the orthographic projection of the resistive electrode 301 on the base substrate 10 and the orthographic projection of the pixel defining layer 14 on the base substrate 10 There is an overlap area.
  • the orthographic projection of the resistance reducing electrode 301 on the substrate substrate completely overlaps with the orthographic projection of the pixel defining layer on the substrate.
  • the orthographic projection of the resistance reducing electrode 301 on the substrate substrate and the orthographic projection of each pixel unit on the substrate substrate Do not overlap each other. That is, the orthographic projection of the resistance-reducing electrode 301 on the substrate substrate does not have any overlapping area with the orthographic projection of the light-emitting layer of each pixel unit on the substrate.
  • the resistance reducing electrode is disposed in the same layer as the first electrode, such that the resistance reducing electrode and the first electrode may be formed by one patterning process.
  • the resistance reducing electrode is disposed in the same layer as the second electrode, so that the resistance reducing electrode and the second electrode can be formed by one patterning process.
  • the resistance reducing electrode 301 can be disposed in the same layer as the anode 201, that is, the resistance reducing electrode 301 is set at a safety guarantee distance. Internally, and insulated from the anode 201.
  • the orthographic projection of the resistance reducing electrode 301 on the substrate substrate and the orthographic projection of the light emitting region of each pixel unit on the substrate substrate can be made without any Overlap The region, in turn, can avoid affecting the normal display function; on the other hand, by providing the lowering resistance electrode 301 and the anode 201 in the same layer, the introduction of a new film layer structure is avoided, which is advantageous for realizing the slim and light design of the electroluminescent display panel.
  • the resistance reducing electrode 301 and the anode 201 can be simultaneously fabricated. That is, a patterning process is employed, and the pattern of the resistance-reducing electrode 301 and the pattern of the anode 201 are simultaneously formed.
  • the resistance-reducing electrode 301 is formed at the original gap of each anode 201, that is, within the safety distance, which can be based on the existing electroluminescent display panel preparation process, Additional processes are required to save production costs and increase production efficiency.
  • the falling resistance electrode 301 and the pixel unit may be disposed in different layers, that is, the pattern of the resistance reducing electrode 301 is formed by a separate patterning process.
  • the resistive electrode 301 and the pixel unit are disposed in a different layer, in order to avoid mutual interference between the anti-resistance electrode 301 and the anode 201.
  • An insulating layer disposed between the resistance reducing electrode 301 and the anode 201.
  • the insulating layer may be a single layer structure or a multilayer structure, which is not limited herein.
  • the anti-resistance electrode 301 is located between the pixel unit and the pixel driving circuit.
  • a flat layer is disposed between the anode 201 and the pixel driving circuit.
  • the falling resistance electrode 301 may be specifically disposed between the pixel driving circuit and the flat layer.
  • the existing flat layer can be utilized as the insulating layer between the anti-resistance electrode 301 and the anode 201, so that the fabrication process of the anti-resistance electrode 301 can be increased only in the fabrication process of the electroluminescent display panel without simultaneously
  • the manufacturing process of the resistance reducing electrode 301 and the insulating layer is increased, thereby simplifying the manufacturing process to a certain extent and reducing the manufacturing cost.
  • the material of the flat layer may be polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, urethane acrylate resin, phenolic epoxy acrylic
  • An organic insulating material such as a resin is not limited herein.
  • the resistance reducing electrode 301 is a film layer between the anode 201 and the pixel driving circuit, it can be avoided that the resistance reducing electrode 301 affects the anode 201 to supply holes to the light emitting layer, and therefore, the resistance reducing electrode 301 is on the substrate.
  • the orthographic projection on the substrate may not only have an overlap region with the orthographic projection of the pixel defining layer on the substrate, but may also have an overlapping region with the orthographic projection of each pixel unit on the substrate.
  • the anode 201 of the pixel unit generally includes a light-emitting layer and a cathode. Based on the above, when the resistance-reducing electrode 301 and the anode 201 are disposed in different layers, in the above-mentioned electroluminescent display panel provided by the embodiment of the present disclosure, The anti-resistance electrode 301 is disposed as a film layer between the anode 201 and the luminescent layer, or the anti-resistance electrode 301 is disposed as a film layer between the luminescent layer and the cathode, which is not limited herein.
  • the resistance-reducing electrode 301 is disposed between the anode 201 and the light-emitting layer, or the resistance-resisting electrode.
  • the 301 is disposed between the light-emitting layer and the cathode, it should be ensured that the orthographic projection of the resistance-resistance electrode 301 on the substrate substrate and the orthographic projection of each pixel unit on the substrate substrate do not overlap each other.
  • the above electroluminescent display panel provided by the embodiment of the present disclosure is a top emission type electroluminescent display panel. Therefore, the cathode should be formed using a material having light transmissivity so that light emitted from the light emitting layer is from the cathode. Shoot out.
  • the anti-resistance electrode 301 provided by the embodiment of the present disclosure may also be applied to a bottom emission type electroluminescent display panel, which is not limited herein.
  • an embodiment of the present disclosure provides a method for fabricating the above-described electroluminescent display panel.
  • the principle of solving the problem is similar to the principle of solving the problem of the electroluminescent display panel. Therefore, the embodiment of the present disclosure
  • For the implementation of the manufacturing method refer to the implementation of the above-mentioned electroluminescent display panel provided by the embodiments of the present disclosure, and the repeated description is omitted.
  • a method for fabricating the above-mentioned electroluminescent display panel provided by the embodiment of the present disclosure, as shown in FIG. 8 may specifically include the following steps:
  • the pixel unit may be formed after forming the resistance reducing electrode.
  • one of the pixel units may be simultaneously formed when the resistance reducing electrode is formed.
  • the resistance reducing electrode formed in a different layer from the signal line is specifically:
  • the first electrode and the resistance reducing electrode are simultaneously formed in the first electrode layer by one patterning process. This eliminates the patterning process of separately forming the resistance-reducing electrode, but simultaneously forms the resistance-reducing electrode when forming the first electrode in the pixel unit.
  • the patterning process involved in forming each layer structure may include not only evaporation, deposition, photoresist coating, mask masking, exposure, development, Some or all of the processes, such as etching and photoresist stripping, may also include other processes, which are specifically determined by the pattern forming the desired pattern in the actual manufacturing process, and are not limited herein.
  • a post-baking process may also be included after development and prior to etching.
  • the deposition process may be a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or a physical vapor deposition method, which is not limited herein; the mask used in the mask process may be a halftone mask (Half Tone Mask).
  • the single-slit sizing mask or the gray sizing mask is not limited herein; the etching may be dry etching or wet etching, which is not limited herein.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned electroluminescent display panel provided by the embodiment of the present disclosure, which may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, Any product or component with display functions such as digital photo frames, navigators, smart watches, fitness wristbands, and personal digital assistants.
  • a display device including the above-mentioned electroluminescent display panel provided by the embodiment of the present disclosure, which may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, Any product or component with display functions such as digital photo frames, navigators, smart watches, fitness wristbands, and personal digital assistants.
  • the display device reference may be made to the embodiment of the electroluminescent display panel described above, and the repeated description is omitted.
  • the electroluminescent display panel, the manufacturing method thereof and the display device provided by the embodiment of the present disclosure include: a substrate, a plurality of pixel units disposed on the substrate, electrically connected to each pixel unit And a plurality of signal lines electrically connected to the pixel driving circuit; and further comprising: a resistance reducing electrode disposed in a different layer from the at least one signal line and connected in parallel. Since the resistance reducing electrode is connected in parallel with each signal line, the resistance of each signal line can be reduced. Therefore, the signal load of each signal line is reduced, and the display quality of the electroluminescence display panel is improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

提供了一种电致发光显示面板、其制作方法及显示装置，包括：衬底基板，设置于衬底基板上的多个像素单元，与各像素单元电性连接的驱动电路，以及与驱动电路电性连接的多条信号线；并且，还包括：与至少一条信号线异层设置且并联连接的降阻电极（301）。由于将降阻电极（301）与各信号线并联，可以降低各信号线的电阻，因此，减小了各信号线的信号负载，提高了电致发光显示面板的显示品质。

Description

电致发光显示面板、其制作方法及显示装置
本申请要求在2017年5月4日提交中国专利局、申请号为201710309230.X、发明名称为“一种电致发光显示面板、其制作方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种电致发光显示面板、其制作方法及显示装置。
背景技术
随着显示面板的不断发展，用户对显示面板的分辨率(Pixels Per Inch，PPI)的要求越来越高。逐渐兴起的虚拟现实(Virtual Reality，VR)技术和增强现实(Augmented Reality，AR)技术，由于其是近眼显示，尤其对PPI提出了更高的要求。
电致发光显示面板(Organic Light-Emitting Diode，OLED)，其具备自发光，不需背光源、对比度高、厚度薄、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、构造及制程较简单等优异的特性，这些优势使得电致发光显示面板有望成为未来显示面板的主流。
电致发光显示面板一般包括衬底基板，设置于衬底基板上的像素驱动电路，设置于像素驱动电路之上的阳极，设置于阳极之上的空穴注入层，设置于空穴注入层之上的空穴传输层，设置于空穴传输层之上的发光层，设置于发光层之上的电子传输层，设置于电子传输层之上的电子注入层，设置于电子注入层之上的阴极，以及设置于阴极之上的封装层。一般地，将空穴注入层、空穴传输层、发光层、电子传输层和电子注入层的叠加膜层称为有机发光材料层，且阳极、有机发光材料层和阴极之间相互接触。由上述描述可知，电致发光显示面板必须由像素驱动电路进行驱动，才可以实现画面显示。相 比于每个像素只需一个薄膜晶体管(Thin Film Transistor，TFT)进行驱动的液晶显示面板(Liquid Crystal Display，LCD)，高PPI的电致发光显示面板很难实现。
在实际的像素驱动电路的设计中，由于要极度压缩空间，只能将通常与数据线同层设置的纵向布线的直流高电平信号线(VDD)改为与栅线同层设置的横向布线的直流高电平信号线(VDD)。而对于电致发光显示面板工艺来说，直流高电平横向信号线的钼金属电阻率远远大于直流高电平纵向信号线的铝金属电阻率，所以横向布线使得直流高电平信号线的信号负载大大增加。负载大造成信号延迟较大，从而极大地降低了电致发光显示面板的显示品质。
发明内容
有鉴于此，本公开实施例提供一种电致发光显示面板、其制作方法及显示装置。
本公开实施例提供的一种电致发光显示面板，包括：衬底基板，设置于所述衬底基板上的多个像素单元，与各所述像素单元电性连接的像素驱动电路，以及与所述像素驱动电路电性连接的多条信号线；还包括：
与至少一条所述信号线异层设置且并联连接的降阻电极。
可选地，在本公开实施例提供的上述电致发光显示面板中，所述信号线沿第一方向延伸，所述信号线被配置为传输恒压信号。
可选地，在本公开实施例提供的上述电致发光显示面板中，所述降阻电极沿第一方向延伸，或所述降阻电极沿第二方向延伸；其中所述第一方向与所述第二方向存在夹角。
可选地，在本公开实施例提供的上述电致发光显示面板中，所述降阻电极呈网格状结构。
可选地，在本公开实施例提供的上述电致发光显示面板中，所述降阻电极与所述信号线之间通过多个过孔电性连接。
可选地，在本公开实施例提供的上述电致发光显示面板中，所述降阻电 极在所述衬底基板上的正投影与像素界定层在所述衬底基板上的正投影存在交叠区域。
可选地，在本公开实施例提供的上述电致发光显示面板中，所述降阻电极在所述衬底基板上的正投影与各所述像素单元在所述衬底基板上的正投影互不重叠。
可选地，在本公开实施例提供的上述电致发光显示面板中，所述像素单元包括第一电极、第二电极以及位于所述第一电极和所述第二电极之间的发光层；
所述降阻电极与所述第一电极同层设置，或所述降阻电极与所述第二电极同层设置。
可选地，在本公开实施例提供的上述电致发光显示面板中，所述降阻电极与所述像素单元异层设置。
可选地，在本公开实施例提供的上述电致发光显示面板中，还包括：设置于所述降阻电极与所述阳极之间的绝缘层。
可选地，在本公开实施例提供的上述电致发光显示面板中，所述降阻电极位于所述像素单元与所述像素驱动电路之间。
本公开实施例提供的一种显示装置，包括：上述电致发光显示面板。
本公开实施例提供的一种上述电致发光显示面板的制作方法，包括：
提供一衬底基板；
在所述衬底基板上形成像素驱动电路，与所述像素电路连接的多条信号线；
形成与所述信号线异层设置的降阻电极，所述降阻电极与所述信号线连接。
可选地，在本公开实施例提供的上述制作方法中，形成与所述信号线异层设置的降阻电极具体为：
形成与所述信号线异层设置的第一电极层；
通过一次构图工艺在所述第一电极层中同时形成第一电极和所述降阻电 极。
附图说明
图1为现有技术中2T1C像素电路的结构示意图；
图2为本公开实施例提供的电致发光显示面板中各像素单元的阳极的排列示意图；
图3为本公开实施例提供的电致发光显示面板中降阻电极的结构示意图之一；
图4为本公开实施例提供的电致发光显示面板中降阻电极的结构示意图之二；
图5为本公开实施例提供的电致发光显示面板中降阻电极的结构示意图之三；
图6为本公开实施例提供的电致发光显示面板中降阻电极的结构示意图之四；
图7为本公开实施例提供的电致发光显示面板的剖面结构示意图；
图8为本公开实施例提供的一种电致发光显示面板的制作方法的流程图。
具体实施方式
为了提高电致发光显示面板的PPI，图1给出了一种包括两个具有开关功能的TFT1、TFT2和一个存储电荷的电容(Capacitance,C)的2T1C像素驱动电路，用于驱动电致发光显示面板。在栅线Gate向TFT1提供开启信号时，TFT1打开，之后TFT1有选择性地将数据线Data提供的数据电压信号接入到TFT2的栅极，并通过电容C对该数据电压信号进行存储。之后，由TFT2将储存的数据电压信号转换为流经TFT2的电流信号，而TFT2与OLED为串联结构，流经TFT2的电流信号即为OLED工作时候的电流信号。
但是，在实际的像素驱动电路的设计中，由于要尽可能地提高空间的利用率，只能将通常与数据线Data同层设置的纵向布线的直流高电平信号线 (VDD)设置成如图1所示的与栅线Gate同层设置的横向布线方式，而对于电致发光显示面板工艺来说，直流高电平横向信号线的钼金属电阻率远远大于直流高电平纵向信号线的铝金属电阻率，所以横向布线使得直流高电平信号线的信号负载大大增加。
发明人通过仿真测试发现，具有直流高电平横向信号线的2T1C像素驱动电路只适用于驱动1英寸左右的电致发光显示面板，而对于采用VR和AR技术的3.5英寸以上的电致发光显示面板，则会由于负载较大，造成信号延迟，从而极大地降低了电致发光显示面板的显示品质。
此外，随着显示技术的发展，电致发光显示面板表现出尺寸越来越大，分辨率和刷新率越来越高的发展趋势。越来越大的显示面板尺寸、越来越高的分辨率和刷新率使得与像素驱动电路连接的栅线和数据线等信号线的信号负载越来越大，严重影响了电致发光显示面板的显示品质。
有鉴于此，本公开实施例提供了一种电致发光显示面板、其制作方法及显示装置。为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述，显然，所描述的实施例仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
本公开实施例提供的一种电致发光显示面板，包括：衬底基板，设置于衬底基板上的多个像素单元，与各像素单元电性连接的像素驱动电路，以及与像素驱动电路电性连接的多条信号线；并且，如图3和图4所示，还包括：
与至少一条信号线(图中未示出)异层设置且并联连接的降阻电极301。
在本公开实施例提供的上述电致发光显示面板中，由于通过将降阻电极301与信号线异层设置且电性连接，即将降阻电极301与各信号线并联，可以降低各信号线的电阻，从而减小了各信号线的信号负载，提高了电致发光显示面板的显示品质。
可选地，为了尽可能的减小信号线的信号负载，在本公开实施例提供的 上述电致发光显示面板中，设置有与各条信号线并联连接的降阻电极。
可选地，在本公开实施例提供的上述电致发光显示面板中，信号线沿第一方向延伸，信号线被配置为传输恒压信号。第一方向一般为平行于显示面板短边的方向。
具体地，各信号线可以为直流高电平横向信号线。即可以通过设置与各直流高电平横向信号线异层设置且电性连接的降阻电极来降低各直流高电平横向信号线的电阻，以达到提高显示画面的整体均一性，提升显示画面品质的效果。
需要说明的是，在本公开实施例提供的上述电致发光显示面板中，不仅可以通过设置降阻电极来降低直流高电平横向信号线的电阻；而且还可以通过设置降阻电极来降低其他信号线的电阻，例如，栅线、数据线、公共电极线、时钟信号线或触控信号线，以提高电致发光显示面板的显示品质。
为便于理解本公开实施例的技术方案，以下均以信号线为直流高电平横向信号线为例进行说明。
可选地，在本公开实施例提供的电致发光显示面板中，像素驱动电路一般位于衬底基板与像素单元之间，像素驱动电路可以是用于驱动像素单元发光的任意一种结构的像素驱动电路，例如图1所示的2T1C像素驱动电路，当然也可以是具内部补偿功能或外部补偿功能的其它结构的像素驱动电路，在此不作限定。
可选地，在本公开实施例提供的电致发光显示面板中，如图7所示，像素单元11主要包括第一电极、第二电极以及位于第一电极和第二电极之间的发光层203。第一电极和第二电极中之一为阳极201，另一个为阴极202。像素驱动电路12与阳极201连接，阴极202一般为公共电极层。各信号线13一般设置在像素单元11与衬底基板10之间。
可选地，在本公开实施例提供的上述电致发光显示面板中，衬底基板可以是柔性衬底基板，例如材料为聚乙烯醚邻苯二甲酸酯、聚萘二甲酸乙二醇酯、聚碳酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜或聚酰亚胺等具有优良 的耐热性和耐久性的塑料基板；还可以是刚性衬底基板，例如玻璃基板，在此不做限定。
可选地，在本公开实施例提供的上述电致发光显示面板中，降阻电极301的实现方式可以为多种，例如，如图5所示，降阻电极301沿第一方向延伸；又如，如图3所示，降阻电极301沿第二方向延伸；其中第一方向与第二方向存在夹角。图5中以第一方向为行方向为例进行说明，图3中以第二方向为列方向为例进行说明，但是不限于此。
或者，如图4所示，降阻电极301呈网格状结构，在此不做限定。并且，相较于由单独延伸方向的走线构成的降阻电极301，具有网格状结构的降阻电极301的电阻更小，可以进一步降低直流高电平横向信号线的电阻，进而提高电致发光显示面板的显示品质。其中附图3至图5仅视出了阳极201与降阻电极301之间的相对位置关系。
可选地，在本公开实施例提供的上述电致发光显示面板中，采用具有网格状结构的降阻电极301。
需要说明的是，本发明实施例提供的电致发光显示面板，对像素单元的排布以及形状不进行限定，图2至图5中，像素单元中阳极201的形状是为了匹配衬底基板上栅线的布线排布而设计的。因此，可以理解的是，阳极201的形状还可以是图6中的矩形。
需要说明的是，在本公开实施例提供的上述电致发光显示面板中，降阻电极的形状可以有多种，例如，可以为直线、折线或波浪线，具体可以根据实际需要及工艺条件进行设置，在此不做限定。
并且，为了获得电阻较小的降阻电极，可以采用金属材料制作降阻电极。可选地，降阻电极的材料可以为电阻率较小的镁、铝、铜、银其中之一或合金组合，在此不做限定。
可选地，在本公开实施例提供的上述电致发光显示面板中，如图3所示，降阻电极301与直流高电平横向信号线(图中未示出)之间可以通过多个过孔302电性连接。这样设置，相当于将直流高电平横向信号线和构成降阻电 极301的多个金属电阻并联，从而可以最大限度的减少直流高电平横向信号线的电阻，进而大大降低了直流高电平横向信号线的信号负载，显著提高了电致发光显示面板的显示品质。
可选地，为了不影响阳极201向发光层提供空穴，在本公开实施例提供的上述电致发光显示面板中，如图7所示，宜使降阻电极301在衬底基板10上的正投影位于各像素单元11之间的间隙在衬底基板10上的正投影内，即降阻电极301在衬底基板10上的正投影与像素界定层14在衬底基板10上的正投影存在交叠区域。
可选地，为最大化地增大降阻电极301的线宽，降低降阻电极301的电阻，从而大大减小直流高电平横向信号线的电阻，在本公开实施例提供的上述电致发光显示面板中，降阻电极301在衬底基板上的正投影与像素界定层在衬底基板上的正投影完全重叠。
进一步地，为了不影响像素单元的发光，在本公开实施例提供的上述电致发光显示面板中，降阻电极301在衬底基板上的正投影与各像素单元在衬底基板上的正投影互不重叠。即降阻电极301在衬底基板上的正投影与各像素单元的发光层在衬底基板上的正投影没有任何交叠区域。
可选地，在本公开实施例提供的上述电致发光显示面板中，降阻电极与第一电极同层设置，这样降阻电极与第一电极可以通过一次构图工艺形成。或降阻电极与第二电极同层设置，这样降阻电极与第二电极可以通过一次构图工艺形成。
由于电致发光显示面板的工艺制作需求，为防止不同颜色的像素单元之间发生串色，如图2所示，各像素单元的阳极201之间会有一个较大的安全保证距离。基于此，可选地，在本公开实施例提供的上述电致发光显示面板中，如图7所示，降阻电极301可以与阳极201同层设置，即将降阻电极301设置在安全保证距离内，且与阳极201之间相互绝缘。如此以来，一方面，通过将降阻电极301设置在安全保证距离内，可以使降阻电极301在衬底基板上的正投影与各像素单元的发光区域在衬底基板上的正投影没有任何交叠 区域，进而可以避免影响正常的显示功能；另一方面，通过将降阻电极301与阳极201同层设置，避免了引入新的膜层结构，有利于实现电致发光显示面板的轻薄化设计。
并且，如图7所示，在降阻电极301与阳极201同层设置时，在本公开实施例提供的上述电致发光显示面板中，降阻电极301和阳极201可以同时制作。即采用一次构图工艺，同时形成降阻电极301的图形和阳极201的图形。这样，通过将各阳极201所在层的结构进行变更，在各阳极201原有的间隙处即安全距离内形成降阻电极301，可以在现有的电致发光显示面板制备工艺的基础上，不需要增加额外的工艺，从而节省了生产成本，提高了生产效率。
当然，可选地，在本公开实施例提供的上述电致发光显示面板中，还可以将降阻电极301与像素单元异层设置，即采用单独的构图工艺制作降阻电极301的图形。
进一步地，在降阻电极301与像素单元异层设置时，为避免降阻电极301与阳极201之间的相互干扰，在本公开实施例提供的上述电致发光显示面板中，还可以包括：设置于降阻电极301与阳极201之间的绝缘层。并且，该绝缘层可以为单层结构，也可以为多层结构，在此不做限定。
可选地，在降阻电极301与像素单元异层设置时，在本公开实施例提供的上述电致发光显示面板中，降阻电极301位于像素单元与像素驱动电路之间。一般地，阳极201与像素驱动电路之间设置有平坦层，基于此，降阻电极301具体可以设置于像素驱动电路与平坦层之间。这样设置，就可以利用已有的平坦层作为降阻电极301与阳极201之间的绝缘层，从而可以仅在电致发光显示面板的制作工艺中增加降阻电极301的制作工艺，而不必同时增加降阻电极301和绝缘层的制作工艺，从而在一定程度上简化了制作工艺，降低了制作成本。
进一步地，平坦层的材料可以为聚丙烯酸树脂、聚环氧丙烯酸树脂、感光性聚酰亚胺树脂、聚酯丙烯酸酯、聚氨酯丙烯酸酯树脂、酚醛环氧压克力 树脂等有机绝缘材料，在此不做限定。
可选地，由于当降阻电极301为位于阳极201与像素驱动电路之间的膜层时，可以避免降阻电极301影响阳极201向发光层提供空穴，因此，降阻电极301在衬底基板上的正投影不仅可以与像素界定层在衬底基板上的正投影之间存在交叠区域，还可以与各像素单元在衬底基板上的正投影之间存在交叠区域。
此外，像素单元的阳极201上一般还包括发光层和阴极，基于此，在降阻电极301与阳极201异层设置时，在本公开实施例提供的上述电致发光显示面板中，还可以将降阻电极301设置为位于阳极201与发光层之间的膜层，或者，将降阻电极301设置为位于发光层与阴极之间的膜层，在此不做限定。
并且，在本公开实施例提供的上述电致发光显示面板中，为了不影响具有的阳极201向发光层提供空穴，在降阻电极301设置于阳极201与发光层之间，或降阻电极301设置于发光层与阴极之间时，应保证降阻电极301在衬底基板上的正投影与各像素单元在衬底基板上的正投影互不重叠。
需要说明的是，本公开实施例提供的上述电致发光显示面板为顶发射型电致发光显示面板，因此，阴极宜使用具有透光性的材料形成，以使从发光层发出的光从阴极射出。然而，值得注意的是，本公开实施例提供的降阻电极301亦可应用于底发射型电致发光显示面板，在此不做限定。
基于同一发明构思，本公开实施例提供了一种上述电致发光显示面板的制作方法，由于该制作方法解决问题的原理与上述电致发光显示面板解决问题的原理相似，因此，本公开实施例提供的该制作方法的实施具体可以参见本公开实施例提供的上述电致发光显示面板的实施，重复之处不再赘述。
本公开实施例提供的一种上述电致发光显示面板的制作方法，如图8所示，具体可以包括以下步骤：
S801、提供一衬底基板；
S802、在衬底基板上形成像素驱动电路，以及与像素电路连接的多条信号线；
S803、形成与信号线异层设置的降阻电极，降阻电极与信号线连接。
具体地，在本发明实施例提供的制作方法中，像素单元可以在形成降阻电极之后形成，当然，也可以在形成降阻电极时同时形成像素单元中的其中一个电极。
可选地，为了节省制作工艺，降低生产成本，提高生产效率，在本公开实施例提供的上述制作方法中，形成与信号线异层设置的降阻电极具体为：
形成与信号线异层设置的第一电极层；
通过一次构图工艺在第一电极层中同时形成第一电极和降阻电极。这样省去单独制作降阻电极的构图工艺，而是在形成像素单元中的第一电极时同时形成降阻电极。
需要说明的是，在本公开实施例提供的上述制作方法中，形成各层结构涉及到的构图工艺，不仅可以包括蒸镀、沉积、光刻胶涂覆、掩模板掩模、曝光、显影、刻蚀、光刻胶剥离等部分或全部的工艺过程，还可以包括其他工艺过程，具体以实际制作过程中形成所需构图的图形为准，在此不做限定。例如，在显影之后和刻蚀之前还可以包括后烘工艺。
其中，沉积工艺可以为化学气相沉积法、等离子体增强化学气相沉积法或物理气相沉积法，在此不做限定；掩膜工艺中所用的掩膜板可以为半色调掩膜板(Half Tone Mask)、单缝衍射掩模板(Single Slit Mask)或灰色调掩模板(Gray Tone Mask)，在此不做限定；刻蚀可以为干法刻蚀或者湿法刻蚀，在此不做限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述电致发光显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述电致发光显示面板的实施例，重复之处不再赘述。
本公开实施例提供的上述电致发光显示面板、其制作方法及显示装置，包括：衬底基板，设置于衬底基板上的多个像素单元，与各像素单元电性连 接的像素驱动电路，以及与像素驱动电路电性连接的多条信号线；并且，还包括：与至少一条信号线异层设置且并联连接的降阻电极。由于将降阻电极与各信号线并联，可以降低各信号线的电阻，因此，减小了各信号线的信号负载，提高了电致发光显示面板的显示品质。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (14)

  1. 一种电致发光显示面板，包括：衬底基板，设置于所述衬底基板上的多个像素单元，与各所述像素单元电性连接的像素驱动电路，以及与所述像素驱动电路电性连接的多条信号线；其中，还包括：
    与至少一条所述信号线异层设置且并联连接的降阻电极。
  2. 如权利要求1所述的电致发光显示面板，其中，所述信号线沿第一方向延伸，所述信号线被配置为传输恒压信号。
  3. 如权利要求1所述的电致发光显示面板，其中，所述降阻电极沿第一方向延伸，或所述降阻电极沿第二方向延伸；其中所述第一方向与所述第二方向存在夹角。
  4. 如权利要求1所述的电致发光显示面板，其中，所述降阻电极呈网格状结构。
  5. 如权利要求1所述的电致发光显示面板，其中，所述降阻电极与各所述信号线之间通过多个过孔电性连接。
  6. 如权利要求1所述的电致发光显示面板，其中，所述降阻电极在所述衬底基板上的正投影与像素界定层在所述衬底基板上的正投影存在交叠区域。
  7. 如权利要求6所述的电致发光显示面板，其中，所述降阻电极在所述衬底基板上的正投影与各所述像素单元在所述衬底基板上的正投影互不重叠。
  8. 如权利要求7所述的电致发光显示面板，其中，所述像素单元包括第一电极、第二电极以及位于所述第一电极和所述第二电极之间的发光层；
    所述降阻电极与所述第一电极同层设置，或所述降阻电极与所述第二电极同层设置。
  9. 如权利要求6所述的电致发光显示面板，其中，所述降阻电极与所述像素单元异层设置。
  10. 如权利要求9所述的电致发光显示面板，其中，还包括：设置于所述降阻电极与所述像素单元之间的绝缘层。
  11. 如权利要求10所述的电致发光显示面板，其中，所述降阻电极位于所述像素单元与所述像素驱动电路之间。
  12. 一种显示装置，其中，包括：如权利要求1-11任一项所述的电致发光显示面板。
  13. 一种如权利要求1-11任一项所述的电致发光显示面板的制作方法，其中，包括：
    提供一衬底基板；
    在所述衬底基板上形成像素驱动电路，与所述像素电路连接的多条信号线；
    形成与所述信号线异层设置的降阻电极，所述降阻电极与所述信号线连接。
  14. 如权利要求13所述的制作方法，其中，形成与所述信号线异层设置的降阻电极具体为：
    形成与所述信号线异层设置的第一电极层；
    通过一次构图工艺在所述第一电极层中同时形成第一电极和所述降阻电极。
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CN106910765A (zh) * 2017-05-04 2017-06-30 京东方科技集团股份有限公司 一种电致发光显示面板、其制作方法及显示装置

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CN113287161A (zh) * 2019-03-29 2021-08-20 三星电子株式会社 显示模块和显示模块的驱动方法
CN113287161B (zh) * 2019-03-29 2024-05-03 三星电子株式会社 显示模块和显示模块的驱动方法
CN114097089A (zh) * 2020-04-26 2022-02-25 京东方科技集团股份有限公司 显示基板以及显示装置
CN115881761A (zh) * 2022-12-29 2023-03-31 广州华星光电半导体显示技术有限公司 显示面板及显示装置

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