WO2019094338A1 - Procédé et ensemble pour atténuer des effets de canal court dans des dispositifs de transistor mosfet au carbure de silicium - Google Patents

Procédé et ensemble pour atténuer des effets de canal court dans des dispositifs de transistor mosfet au carbure de silicium Download PDF

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Publication number
WO2019094338A1
WO2019094338A1 PCT/US2018/059243 US2018059243W WO2019094338A1 WO 2019094338 A1 WO2019094338 A1 WO 2019094338A1 US 2018059243 W US2018059243 W US 2018059243W WO 2019094338 A1 WO2019094338 A1 WO 2019094338A1
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Prior art keywords
region
hard mask
layer
substrate
mask layer
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Ceased
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PCT/US2018/059243
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English (en)
Inventor
Dumitru Gheorge SDRULA
Avinash Srikrichnan KASHYAP
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Microsemi Corp
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Microsemi Corp
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Priority to CN201880072111.XA priority Critical patent/CN111316447B/zh
Priority to DE112018005308.3T priority patent/DE112018005308T5/de
Publication of WO2019094338A1 publication Critical patent/WO2019094338A1/fr
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs

Definitions

  • This description relates to semiconductor devices and fabrication of semiconductor devices, and more specifically to a vertical, double implanted, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices on silicon carbide (SiC), and methods of fabricating them.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • SiC Silicon Carbide
  • WBG wide-band gap
  • SiC also exhibits an undesirable lack of diffusion of any implanted species. This limitation means that all implanted layers are shallow relative to the surface of the semiconductor material, and therefore all junction depths are limited to the capability of the ion implantation equipment (typically in the range of 1.0- 2.0 ⁇ ).
  • VDIMOS Vertical, Double Implanted Metal Oxide Semiconductor
  • This abnormal leakage current is that it can be totally eliminated with a negative bias on the gate, which has the effect of electronically increasing the effective length of the channel. Because of a threshold voltage dependence on temperature characteristic, the "short channel” effect is even more pronounced at elevated ambient and operating temperatures, when the voltage required to create an inversion layer in the P-Well is lowered. Short channel effects, also referred to as, drain induced barrier lowering (DIBL) or punch through, can affect the long term reliability of the MOSFET due to local temperature increase and increased inj ection rate of hot carriers in the gate oxide.
  • DIBL drain induced barrier lowering
  • the gate voltage required to form an inversion layer in the body is entirely independent on the drain voltage.
  • DIBL Drain Induced Barrier Lowering
  • the depletion region in the body has the effect of lowering the potential energy barrier for the electrons.
  • the gate voltage has the function of lowering the potential barrier down to the point where electrons are able to flow.
  • V D Drain Induced Barrier Lowering
  • a power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer.
  • the power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.
  • a method of mitigating short channel effects in a power transistor assembly includes using a polysilicon layer as the hard mask to block the implants, over a first surface of a substrate formed of a silicon carbide material, the polysilicon layer having an outer surface and an inner surface relative to the substrate, and a face extending between the inner surface and the outer surface, a distance between the inner surface and outer surface defining a thickness of the polysilicon layer.
  • the method also includes opening a window through the polysilicon layer to the first surface of the substrate and implanting impurities in the first surface of the substrate to form a body region perfectly aligned with the window.
  • the method further includes forming a source region in the body region, growing an oxide on the polysilicon layer, etching away the oxide, and implanting additional impurities into the first surface of the substrate proximate the etched oxidized face forming a lateral extension of the body region extending away from the source region to create a longer channel of the power transistor assembly.
  • a power semiconductor assembly in yet another embodiment, includes a semiconductor substrate formed of an N-type material and having a first impurity concentration and a P-well formed on a first surface of the semiconductor substrate and having a second impurity concentration, the second impurity concentration greater than the first impurity concentration of the semiconductor substrate.
  • the power semiconductor assembly also includes an N-type source region formed on the first surface of the semiconductor substrate in the P-well and having a third impurity concentration that is greater than the first impurity concentration, at least one P-type extension region formed in the first surface of the semiconductor substrate and extending laterally away from the N-type source region, and a gate insulating film formed on the first surface of the semiconductor substrate between the N-type source regions.
  • FIGS. 1 -10 show example embodiments of the method and apparatus described herein.
  • FIGS. 1-4 illustrate a sequence of forming a vertical, double implanted, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in accordance with an example embodiment of the present disclosure.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • FIGS. 5-8 illustrate a sequence of forming a vertical, double implanted, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in accordance with another example embodiment of the present disclosure.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • FIG. 9 is a cross-sectional view of a process of forming a power transistor assembly having a plurality of channel extensions.
  • FIG. 10 is a flowchart of a method of mitigating short channel effects in a power transistor assembly in accordance with an example embodiment of the present disclosure.
  • VDMOS vertical double implanted metal oxide semiconductor
  • the VDMOS device incorporates a double implantation fabrication process where a p-type doped region and an n+ type source region are implanted through a common window defined by an edge of a hard mask (polysilicon) of the device.
  • the hard mask layer includes a metal or metals, which may be in the form of a metal nitride, for example, titanium nitride.
  • Hard mask layer may also be formed of a non-metal nitride such as silicon nitride, an oxynitride such as silicon oxynitride, or the like.
  • the p- region is implanted deeper than the n+ source and the surface channel length is defined as the lateral implantation distance between the p- and the n+ source.
  • a positive bias on the gate causes a surface inversion layer— or channel— to form in a p-type region under the gate oxide and thereby creates a conductive path between source and drain.
  • the application of a positive drain voltage then produces current flow between drain and source. Electrons enter the source terminal and flow laterally through the inversion layer under the gate to the n-drift region, the electrons then flow vertically through the n- drift region to the drain terminal.
  • a power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material such as, an epitaxially formed substrate of silicon carbide (SiC) with a hard mask layer of for example, a polysilicon material covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer.
  • a thin oxide layer is formed on the first layer of semiconductor material before the hard mask layer is formed.
  • a first region is formed in the first layer of semiconductor material of a second conductivity type material and closely aligned with the window. The one or more source regions form a pn junction with the first region.
  • One or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region.
  • An extension of the first region is formed to extend laterally through the surface of the first layer.
  • the extension may include one or more serial extensions formed separately from each other of the one or more serial extensions.
  • the extensions of the first region serve to lengthen the channel and to reduce short channel effects.
  • the first region cannot simply be lengthened to accomplish the same end. If the first region (P-well) were simply extended, which would accomplish approximately the same outcome as forming the first region as a longer body originally except, this would have a negative effect by pinching the JFET region. To avoid pinching, in the example embodiment, the first region extends into the first layer to a depth of greater than 1.0 microns.
  • the first region extends into the first layer to a depth of approximately 0.75 microns to approximately 1.25 microns.
  • the one or more serial extensions extend into first layer to a depth of approximately 50% of the depth of the first region.
  • the one or more serial extensions extend into first layer to a depth of approximately 0.2 microns to approximately 0.5 microns. The shallower extension facilitates mitigating the effects of the short channel without the pinching phenomenon.
  • a drain region formed on a side of the first layer opposite the one or more source regions.
  • a method of mitigating short channel effects in a power transistor assembly includes forming a hard mask layer of for example, a polysilicon material, over a first surface of a substrate formed of a first conductivity type silicon carbide material.
  • the hard mask layer has an outer surface and an inner surface relative to the substrate, and a face extending between the inner surface and the outer surface. A distance between the inner surface and outer surface defining a thickness of the hard mask layer.
  • the method includes opening a window through the hard mask layer to the first surface of the substrate, implanting impurities in the first surface of the substrate to form a body region approximately aligned with the window, and forming a source region in the body region having the first conductivity type silicon carbide material.
  • the method further includes oxidizing the face of the hard mask layer, etching away the oxidized face of the hard mask layer, and implanting additional impurities into the first surface of the substrate proximate the etched oxidized face forming a lateral extension of the body region extending away from the source region in a direction of the layer.
  • the face of the hard mask layer may be repeatedly oxidized, etched, and additional impurities implanted into the first surface of the substrate to form additional lateral extensions of the body region extending away from the source region in a direction of the hard mask layer.
  • a drain region may be formed on a second surface of the substrate opposite the polysilicon layer.
  • a real power MOSFET is constructed by repeating cells of the same layout and vertical composition of the layers as illustrated in the cross sections and drawings.
  • the cells can be, for example, an array of stripes or a hexagonal honeycomb in plan view.
  • this disclosure is applicable to P- channel and N-channel Power MOSFET and Power IGBTs formed of SiC material.
  • FIGS. 1-4 illustrate a sequence of forming a vertical, double implanted, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 100 in accordance with an example embodiment of the present disclosure.
  • MOSFET 100 is formed of a wide-band gap (WBG) semiconductor material, such as, but not limited to Silicon Carbide (SiC).
  • WBG materials include semiconductors that have bandgaps on the order of 2 to 4 eV.
  • the electronic properties of WBG semiconductors permit devices formed of WBG semiconductors to operate at relatively higher voltages, frequencies and temperatures than conventional semiconductor materials. WBG semiconductors can be operated at temperatures greater than 300° C.
  • WBG semiconductors are able to operate at relatively higher voltages and currents.
  • MOSFET 100 includes a first semiconductor layer 102 configured as a substrate for MOSFET 100.
  • First semiconductor layer 102 is formed, in one embodiment, of an epitaxial layer of a mono-crystalline SiC semiconductor material of a of a first dopant type.
  • first semiconductor layer 102 is formed of other semiconductor materials.
  • a first dopant type of first semiconductor layer 102 is N-type, in which case the second, opposite dopant type, for example, P-Well 112 refers to P-type.
  • the first dopant type of first semiconductor layer 102 can be P-type, in which case the opposite dopant type is N-type.
  • N-type dopant include, but are not limited to, Phosphorus and Nitrogen (in the case of SiC).
  • the implantation energy is in the range of 30-600 keV.
  • Dopants of the P-type include boron or aluminum.
  • a surface 104 of first semiconductor layer 102 is oxidized using an oxidizing agent, for example, by heating in a furnace, forming an oxide layer 106 on surface 104.
  • Layer 106 in most cases is a deposited oxide on the top of a thermally grown oxide.
  • a hard mask layer 108 is deposited on oxide layer 106.
  • hard mask layer 108 is formed of a poly silicon or other material with oxidizing properties.
  • a window 110 is formed in the hard mask layer 108 by, in some embodiments, by etching, for example, by dry or wet etching.
  • Oxide layer 106 is etched using an acid, such as, hydrofluoric acid (HF) to expose surface 104 in a region of window 110.
  • a body region or P-Well 112 is formed by ion implantation in the region of window 110.
  • a spacer oxide layer 114 is formed self-aligned to hard mask layer 108, which acts as a spacer that offsets next implanted layers 116 and 117.
  • Layers 116 and 117 which will form the source regions of MOSFET 100, are formed by ion implantation and have the opposite polarity in comparison to P-Well 112.
  • a region 118 between a tip 120 of source region 116 and an end 122 of P-Well 112 is defined at least partially by the offset, and which includes a channel 124 is defined by a width 126 of spacer oxide layer 114.
  • a region 119 between a tip 121 of source region 117 and an end 123 of P-Well 112 is defined at least partially by the offset, and which includes a channel 125 defined by a width 127 of spacer oxide layer 114 on source region 117 side.
  • UIS region 128 of the second dopant type is positioned depth-wise in first semiconductor layer 102 beneath the source region 116 and vertically with them, inward from a channel region 130, to enhance a doping concentration of the body regions beneath source region 116 without affecting a gate threshold voltage.
  • FIGS. 5-8 illustrate a sequence of forming a vertical, double implanted, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 500 in accordance with another example embodiment of the present disclosure.
  • MOSFET 500 is formed with a channel region 130 having an increased length 132 in a lateral direction 134.
  • lengthening channel region 130 is accomplished by successively oxidizing hard mask layer 108, etching away the formed oxidation layer, ion implanting first semiconductor layer 102 under where the etched oxidation layer was to move P-Well 112, thus lengthening channel region 130. These steps can be repeated a predetermined number of times to lengthen channel region 130 to a desired dimension as described in detail below.
  • Poly silicon material is selected for hard mask layer 108 because of its oxidation properties, which permits incrementally "walking" hard mask layer 108 back away from source regions 116 and 117, by first oxidizing a face 516 of hard mask layer 108 and then etching the oxidized face 516 away creating a new face 517 on hard mask layer 108.
  • oxidizable material is its oxidation rate, which may be expressed in units of Angstroms per hour (A/hr). A low oxidation rate will unnecessarily extend the oxide formation process, a high oxidation rate will affect the completeness of the oxidation process. In one embodiment, the oxidation rate is selected to be in the range of 60-20,000 A/hr. In another embodiment, the oxidation rate is selected to be in the range of 1000-12,000 A/hr. In still another embodiment, the oxidation rate is selected to be in the range of 1000-2000 A/hr.
  • FIG. 5 illustrates MOSFET 500, which is similar to MOSFET 100 shown in FIG. 4, with spacer oxide layer 114 etched away.
  • hard mask layer 108 is again oxidized forming a second oxide layer 514 (shown in FIG. 6), which is etched away again as shown in FIG. 7. Oxidizing hard mask layer 108 and etching the formed second oxide layer 514, moves face 516 laterally away from P- Well 112, permitting an addition of P-well material up to approximately a position of face 516.
  • a channel of any length can thus be formed to accommodate various electrical requirements of MOSFET 500.
  • FIG. 9 is a cross-sectional view of a process of forming a power transistor assembly 900 having a plurality of channel extensions 902.
  • power transistor assembly 900 is formed of a semiconductor substrate 904, such as, but not limited to silicon carbide (SiC).
  • a hard mask layer 906 is formed on a layer of thin oxide 907 that is formed on or over semiconductor substrate 904 and a window 908 is etched in hard mask layer 906 and thin oxide layer 907 down to a surface 910 of semiconductor substrate 904.
  • a gate region 911 is left in window 908.
  • a body region 912 is formed in semiconductor substrate 904 at surface 910, in one embodiment, by ion implantation.
  • a source region 914 is formed in body region 912.
  • a source region 916 is formed in body region 912 spaced apart a distance 918 from source region 914.
  • a first short channel 920 is formed in body region 912 between source region 914 and a first end 922 of body region 912.
  • a second short channel 924 is formed in body region 912 between source region 916 and a second end 926 of body region 912.
  • body region 912 is extended laterally away from source region 914 and source region 916.
  • a first region 928 and 930 of hard mask layer 906 is oxidized and then etched away leaving a first portion 932 and 934 of semiconductor substrate 904 exposed where first regions 928 and 930 were etched from.
  • a first extension 936 and 938 are formed, for example, by ion implantation of first portions 932 and 934.
  • First extensions 936 and 938 extend short channels 920 and 924 a distance equal to a width of first regions 928 and 930.
  • a second extension 940 and 942 is formed by oxidizing second regions 944 and 946 of hard mask layer 906, etching away oxidized second regions 944 and 946, and ion implanting second portions 948 and 950.
  • second extensions 940 and 942 extend short channels 920 and 924 an additional distance equal to a width of second regions 944 and 946.
  • the procedure can be implemented a third time to form additional extensions 952 and 954, respectively, and additional extensions as needed.
  • FIG. 10 is a flowchart of a method 1000 of mitigating short channel effects in a power transistor assembly in accordance with an example embodiment of the present disclosure.
  • method 1000 includes forming 1002 a hard mask layer over a surface of a substrate formed of a silicon carbide material.
  • the hard mask layer includes an outer surface and an inner surface relative to the substrate, and a face extending between the inner surface and the outer surface. A distance between the inner and outer surfaces defines a thickness of the hard mask layer.
  • Method 1000 also includes opening 1004 a window in the hard mask layer to the surface of the substrate, implanting 1006 impurities in the surface of the substrate to form a body region approximately aligned with the window, and forming 1008 a source region in the body region.
  • Method 1000 further includes oxidizing 1010 the face of the hard mask layer, etching 1012 away the oxidized face of the hard mask layer, and implanting 1014 additional impurities into the surface of the substrate in the region of the etched oxidized face forming a lateral extension of the body extending away from the source region in a direction of the hard mask layer.
  • Approximating language may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about” and “substantially”, are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value.
  • range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise.
  • the above-described embodiments of a power transistor assembly and method of fabricating the power transistor assembly provides a cost-effective and reliable means for mitigating short channel effects in silicon carbide DMOSFET devices. More specifically, the assembly and method described herein facilitate increasing the channel length by oxidizing a portion of the hard mask layer covering the substrate and then by exposing additional substrate surface area by etching away the oxidized portion. The exposed substrate is then implanted with impurities to form extensions of areas forming the channel. Such process may be repeated a number of times to increase the length of the channel as desired. As a result, the assembly and method described herein facilitate electrically mitigating short channel effects in vertical DMOS type power transistors in a cost-effective and reliable manner.
  • Example assemblies and methods for mitigating short channel effects in power transistor devices are described above in detail.
  • the apparatus illustrated is not limited to the specific embodiments described herein, but rather, components of each may be utilized independently and separately from other components described herein.
  • Each system component can also be used in combination with other system components.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Cette invention concerne un ensemble transistor de puissance et un procédé d'atténuation des effets de canal court dans un ensemble transistor de puissance. L'ensemble transistor de puissance comprend une première couche de matériau semi-conducteur formée à partir d'un matériau d'un premier type de conductivité et une couche de masque dur recouvrant au moins une partie de la première couche et ayant une fenêtre à travers celle-ci exposant une surface de la première couche. L'ensemble transistor de puissance comprend en outre une première région formée dans la première couche de matériau semi-conducteur à partir d'un matériau d'un second type de conductivité et alignée avec la fenêtre, une ou plusieurs régions de source formées à partir d'un matériau du premier type de conductivité à l'intérieur de la première région et séparées par une partie de la première région, et une extension de la première région s'étendant latéralement à travers la surface de la première couche.
PCT/US2018/059243 2017-11-07 2018-11-05 Procédé et ensemble pour atténuer des effets de canal court dans des dispositifs de transistor mosfet au carbure de silicium Ceased WO2019094338A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201880072111.XA CN111316447B (zh) 2017-11-07 2018-11-05 用于减轻碳化硅mosfet器件中的短沟道效应的方法和组件
DE112018005308.3T DE112018005308T5 (de) 2017-11-07 2018-11-05 Verfahren und Anordnung zum Abschwächen von Kurzkanaleffekten in Siliciumcarbid-MOSFET-Vorrichtungen

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US201762582438P 2017-11-07 2017-11-07
US62/582,438 2017-11-07

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EP1058303A1 (fr) * 1999-05-31 2000-12-06 STMicroelectronics S.r.l. Fabrication d'une structure VDMOS ayant des effets parasites réduits
US20030059983A1 (en) * 2001-09-21 2003-03-27 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device with offset sidewall structure
EP2083449A2 (fr) * 2008-01-25 2009-07-29 Cree, Inc. Dispositif pour contrôler la conduction électrique à travers un corps semiconducteur
US20100163888A1 (en) * 2008-12-30 2010-07-01 Stmicroelectronics S.R.L Manufacturing process of a power electronic device integrated in a semiconductor substrate with wide band gap and electronic device thus obtained
US20130009256A1 (en) * 2010-03-30 2013-01-10 Rohm Co Ltd Semiconductor device
US20120049902A1 (en) * 2010-08-30 2012-03-01 Stmicroelectronics S.R.L. Integrated electronic device and method for manufacturing thereof

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DE112018005308T5 (de) 2020-06-25
CN111316447A (zh) 2020-06-19

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