WO2019105331A1 - Système informatique et appareil électronique correspondant - Google Patents

Système informatique et appareil électronique correspondant Download PDF

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Publication number
WO2019105331A1
WO2019105331A1 PCT/CN2018/117588 CN2018117588W WO2019105331A1 WO 2019105331 A1 WO2019105331 A1 WO 2019105331A1 CN 2018117588 W CN2018117588 W CN 2018117588W WO 2019105331 A1 WO2019105331 A1 WO 2019105331A1
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WIPO (PCT)
Prior art keywords
arithmetic
unit
data
control
signal
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Ceased
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PCT/CN2018/117588
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English (en)
Inventor
Guochen Sun
Cunyong YANG
Micree ZHAN
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Bitmain Technologies Inc
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Bitmain Technologies Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors

Definitions

  • the present disclosure relates to the field of electronic technology, in particular to a computational system and the corresponding electronic apparatus.
  • the present disclosure provides a computational system and the corresponding electronic apparatus.
  • a computational system comprising a computing device and a control device.
  • the control device comprises a data input-output interface connecting the control device to external devices and a control-device data-input component connecting the control device to the computing device.
  • the computing device comprises a plurality of arithmetic units connected in series, each arithmetic unit comprising an arithmetic-unit data-input component, an arithmetic-unit data-output component, and a clock-signal-input interface.
  • a first-stage arithmetic unit among the plurality of arithmetic units is connected to the control device.
  • the arithmetic-unit data-input component of the first-stage arithmetic unit is connected to the arithmetic-unit data-output component of a second-stage arithmetic unit among the plurality of arithmetic units, and is configured to receive data processed by the second-stage arithmetic unit.
  • the arithmetic-unit data-output component of the first-stage arithmetic unit is connected to the control-device data-input component of the control device, and is configured to transmit data processed by the computing device to the control device.
  • control device further comprises a control-device clock-signal-output interface.
  • the control-device clock-signal-output interface is connected to the clock-signal-input interface of the first-stage arithmetic unit to transmit a clock signal to the computing device.
  • At least one of the plurality of arithmetic units comprises an arithmetic-unit clock-signal-output interface.
  • the arithmetic-unit clock-signal-output interface is connected to the clock-signal-input interface of a next-stage arithmetic unit to transmit clock signal to the next-stage arithmetic unit.
  • control device further comprises a control-device command-output interface.
  • Each arithmetic unit further comprises a command-input interface and an arithmetic-unit command-output interface.
  • the control-device command-output interface of the control device is connected to the command-input interface of the first-stage arithmetic unit, and is configured to transmit command signals to the first-stage arithmetic unit.
  • the arithmetic-unit command-output interface of the first-stage arithmetic unit is connected to the command-input interface of the second-stage arithmetic unit, and is configured to transmit command signals to the second-stage arithmetic unit.
  • the computing device further comprises a data interface.
  • the data interface is connected to both the arithmetic-unit data-output component of the first-stage arithmetic unit of the computing device and the control-device data-input component of the control device.
  • the computing device further comprises a signal conversion unit connected to at least two of the plurality of arithmetic units to match a signal voltage range.
  • the computational system further comprises at least one additional of the control device.
  • each of the control devices comprises a control-device data-output component; and the control devices are connected to each other through their respective control-device data-input components and control-device data-output components.
  • the computational system further comprises one or more crystal oscillators.
  • Each crystal oscillator comprises: a power-input interface connected to a power source; and a crystal-oscillator clock-signal-output interface connected to the clock-signal-input interface of an arithmetic unit in the computing device.
  • an electronic apparatus comprises one or more computational systems in the forgoing description.
  • FIG. 1 is an illustrative diagram of a computational system according to an embodiment of the present disclosure
  • FIG 2 is an illustrative diagram of a computational system according to another embodiment of the present disclosure.
  • FIG 3 is an illustrative diagram of a computational system according to another embodiment of the present disclosure.
  • FIG. 1 is an illustrative block diagram of a computational system according to certain embodiments.
  • the computational system may include a computing device 11 and control device 12.
  • the computing device 11 may comprise a plurality of arithmetic units 111 that are sequentially connected in series.
  • a first-stage arithmetic unit among the plurality arithmetic units in the computing device 11 is connected to the control unit 12.
  • a plurality of arithmetic units 111 are incorporated in the computing device 11, and the arithmetic units 111 are connected in series. Only one of arithmetic units 111 needs to be connected to the control device 12.
  • the first-stage arithmetic unit may be connected to the control device 12 to receive signal data and command data from the control device 12.
  • the first-stage arithmetic unit may be the arithmetic unit that is placed closest to the control device.
  • operation of multiple arithmetic units may be coordinated to perform parallel processing of multiple computing tasks, and the wiring space and complexity may be reduced.
  • control device 12 may comprise a clock-signal-output interface, a data-input component, and an input-output interface.
  • the control device 12 is connected to external devices through the input-output interface for data exchange.
  • the clock-signal-output interface of the control device is connected to a clock-signal-input interface of the first-stage arithmetic unit in the computing device.
  • the data-input component of the control device is connected to a data-output component of the first-stage arithmetic unit in the computing device.
  • the control device 12 comprises a clock-signal-output interface, a data-input component, and an input-output interface capable of satisfying basic data transmission requirements.
  • the clock-signal-output interface of the control device is for transmitting a clock signal to the computing device.
  • the data-input component of the control device is for receiving data processed and sent by the computing device.
  • the input-output interface of the control device is used to exchange data between the control device and external devices.
  • each of the arithmetic units 111 comprises a data-input component and a data-output component.
  • the data-input component of an arithmetic unit is connected to the data-output component of a neighboring next-stage arithmetic unit to receive data processed and sent by the neighboring next-stage arithmetic unit.
  • the data-output component of the first-stage arithmetic unit is connected to the data-input component of the control device for transmitting data processed by and sent from the computing device to the control device.
  • each of the arithmetic units 111 further comprises a clock-signal-input interface and one or more clock-signal-output interfaces. Any one of clock-signal-output interfaces of an arithmetic unit may be connected to the clock-signal-input interface of a next-stage arithmetic unit for transmitting a clock signal.
  • the clock-signal-input interface of the first-stage arithmetic unit is connected to the clock-signal-output interface of the control device for receiving clock signal from the control device.
  • the plurality of arithmetic units 111 are connected to each other in series, and each of the arithmetic units 111 comprises a clock-signal-input interface, one or more clock-signal-output interfaces, a data-input component, and a data-output component.
  • the clock-signal-input interface of the first-stage arithmetic unit is connected to the clock-signal-output interface of the control device for receiving clock signal from the control device.
  • the clock-signal-output interface of the first-stage arithmetic unit is connected to the clock-signal-input interface of a second-stage arithmetic unit to transmit the clock signal to the second-stage arithmetic unit, which in turn may pass the clock signal to the third-stage arithmetic unit, and so on, so that all the arithmetic units connected in series may receive the clock signal. If an arithmetic unit at certain stage has two or more clock-signal-output interfaces, one of them may be connected to the clock-signal-input interface of the neighboring next-stage arithmetic unit to transmit the clock signal.
  • the data-output component of the last-stage arithmetic unit is connected to the data-input component of the second-last-stage arithmetic unit, and is used for transmitting the data processed by and sent from the last-stage arithmetic unit to the second-last-stage arithmetic unit; and the data-output component of the second-last-stage arithmetic unit is connected to the data-input component of the third-last-stage arithmetic unit, and is used for transmitting the data processed by and sent from the second-last-stage arithmetic unit to the arithmetic unit above, and so on; until computed data that computed by the computing device is received by the data-input component of the first-stage arithmetic unit, and passed through the data-output component of the first-stage arithmetic unit transmitting to the control device.
  • control device 12 further comprises a command-output interface
  • each arithmetic unit 111 further comprises a command-input interface and a command-output interface.
  • the command-output interface of the control device 12 is connected to the command-input interface of the first-stage arithmetic unit to send the command signal to the first-stage arithmetic unit.
  • the command-output interface of the first-stage arithmetic unit is connected to the command-input interface of the second-stage arithmetic unit to send the received command signal to the second-stage arithmetic unit, and so on.
  • control device 12 further comprises a command-output interface
  • each arithmetic unit 111 further comprises a command-input interface and a command-output interface.
  • the command-output interface of the control device 12 is connected to the command-input interface of the first-stage arithmetic unit in the computing device.
  • the command-output interface of the arithmetic unit at each stage is connected to the command-input interface of the neighboring next-stage arithmetic unit to transmit the command signal to the arithmetic unit at each stage.
  • the computing device 11 further comprises a data interface 112.
  • the data interface 112 is connected to both the data-output component of the first-stage arithmetic unit and the data-input component of the control device 12 to transmit the computed data from the computing device 11 to the control device 12.
  • FIG. 2 is an illustrative diagram of the computational system according to certain other embodiments of the present disclosure.
  • the computing device 11 further comprises one or more signal conversion units 113.
  • Each signal conversion unit 113 is connected to two arithmetic units 111 for adapting their signal voltage levels.
  • the operating voltage levels of two arithmetic units 111 that are connected to each other may be different, and data cannot be transmitted between them without voltage level conversion.
  • the signal conversion unit 113 may be inserted between the two arithmetic units 111 having different operating voltage levels to convert the signal voltage level of the sender into a voltage range that meets the requirement of the receiver.
  • the signal conversion unit converts the signal voltage level of the first-stage arithmetic unit output into a voltage level that is within the acceptable operation voltage range of the second-stage arithmetic unit.
  • a present-stage arithmetic unit sends data to its previous-stage arithmetic unit
  • the signal of the present-stage arithmetic unit also needs to be converted by the signal conversion unit before the signal is transmitted to the neighboring previous-stage arithmetic unit, that is, the voltage range of the present-stage arithmetic unit output is converted into a voltage range that matches the operation voltage range of the neighboring previous-stage arithmetic unit.
  • the present-stage arithmetic unit can directly communicate with the next-stage arithmetic unit without performing signal conversion.
  • the computational system may comprise a plurality of the control devices 12.
  • the control device 12 may further comprise a data-output component.
  • the control devices 12 may be connected to each other through their respective data-output components and the data-input components.
  • the multiple control devices may be integrated into one unit.
  • FIG. 3 is an illustrative diagram of a computational system according to certain other embodiments of the present disclosure.
  • the computational system may further comprise one or more crystal oscillators 114.
  • each crystal oscillator 114 may comprise a power input interface and a clock-signal-output interface.
  • the power input interface is connected to a power source.
  • the clock-signal-output interface of the crystal oscillator is connected to the clock-signal-input interface of one of the arithmetic units.
  • crystal oscillators 114 are added for every two arithmetic units 111, or for every certain number of arithmetic units, or at other suitable intervals and locations.
  • the power input interface of each crystal oscillator is connected to and powered by a power source.
  • the clock-signal-output interface of each crystal oscillator is connected to the clock-signal-input interface of the first-stage arithmetic unit in an arithmetic-unit group that needs to have the clock signal restored to provide clock signal for the arithmetic-unit group.
  • the computational integrated circuit chip may be used to perform Hash calculations in a cryptocurrency mining process.
  • the backbone of a cryptocurrency is its blockchain, which is a global ledger formed by linking together individual blocks of transaction data.
  • the blockchain only contains validated transactions, which prevents fraudulent transactions and double spending of the currency.
  • the validation process relies on data being encrypted using algorithmic hashing.
  • the resulting encrypted value is a series of numbers and letters that does not resemble the original data, and is called a hash.
  • Cryptocurrency mining involves working with the hash. Hashing requires processing the data from a block through a mathematical function, which results in an output of a fixed length.
  • hashing the word “hello” will produce an output that is the same length as the hash for “I am going to the store” .
  • the function used to generate the hash is deterministic, meaning that it will produce the same result each time the same input is used; can generate a hashed input efficiently; makes determining the input difficult (leading to mining) ; and makes small changes to the input result in a very different hash.
  • Solving the hash is essentially solving a complex mathematical problem, and starts with the data available in the block header.
  • Each block header contains a version number, a timestamp, the hash used in the previous block, the hash of the Merkle Root, the nonce, and the target hash.
  • the miner focuses on the nonce, a string of numbers. This number is appended to the hashed contents of the previous block, which is then itself hashed. If this new hash is less than or equal to the target hash, then it is accepted as the solution, the miner is given the reward, and the block is added to the blockchain.
  • BitCoin uses the SHA-256 hash algorithm to generate verifiably "random" numbers in a way that requires a predictable amount of CPU effort. Generating a SHA-256 hash with a value less than the current target solves a block and wins coins for mining machines.
  • the mining computer may calculate a hash functions of a set of random numbers to find a combination that match the current condition for a new block. As a result, an extremely large amount of computation may be required.
  • the computational integrated circuit chip in the foregoing description may be used as Application Specific Integrated Chips (ASIC) to perform multiple hash calculations in parallel using the multiple arithmetic units.
  • ASIC Application Specific Integrated Chips
  • the multiple arithmetic units are connected in series and may communicate the calculation results to one another, these ASICs may be used to calculate a single hash or an iterated hash in parallel.
  • the arithmetic units may be designed and arranged to optimize a specific computation sequence, and the operating voltage levels of two adjacent arithmetic units may be different. If the operating voltage level difference between two arithmetic units connected in series is significant, direct connection for data transmission may not be reliable. Further, relying solely on the same clock signal source may not satisfy the clock signal requirements of the serially connected arithmetic units with different operating voltage levels.
  • a signal conversion unit may be inserted between the two arithmetic units having different operating voltage levels to convert the signal voltage level of the sender into a voltage range that meets the requirement of the receiver.
  • crystal oscillators may be added at suitable intervals and locations to provide additional clock signal to certain arithmetic units. Embodiments of the present disclosure thus may ensure optimized operation and data communication of the arithmetic units connected in series, and improve the calculation speed of the computational integrated circuit chip in a mining machine by using customized parallel computing.
  • an electronic apparatus comprises one or more computational systems in the forgoing descriptions.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
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Abstract

L'invention concerne un système informatique et un appareil électronique, l'appareil électronique comprenant un ou plusieurs systèmes informatiques. Le systèmes informatiques comprend un dispositif informatique et un dispositif de commande. Le dispositif de commande comprend une interface d'entrée/sortie de données reliant le dispositif de commande à des dispositifs externes et un composant d'entrée de données de dispositif de commande reliant le dispositif de commande au dispositif informatique. Le dispositif informatique comprend une pluralité d'unités arithmétiques connectées en série, chaque unité arithmétique comprenant un composant d'entrée de données d'unité arithmétique, un composant de sortie de données d'unité arithmétique et une interface d'entrée de signal d'horloge. Une unité arithmétique de premier étage parmi la pluralité d'unités arithmétiques est connectée au dispositif de commande. Le composant d'entrée de données d'unité arithmétique de l'unité arithmétique de premier étage est connecté au composant de sortie de données d'unité arithmétique d'une unité arithmétique de second étage parmi la pluralité d'unités arithmétiques, et est configuré pour recevoir des données traitées par l'unité arithmétique de second étage. Le composant de sortie de données d'unité arithmétique de l'unité arithmétique de premier étage est connecté au composant d'entrée de données de dispositif de commande du dispositif de commande, et est configuré pour transmettre des données traitées par le dispositif informatique au dispositif de commande.
PCT/CN2018/117588 2017-11-28 2018-11-27 Système informatique et appareil électronique correspondant Ceased WO2019105331A1 (fr)

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CN201721617831.9U CN207503225U (zh) 2017-11-28 2017-11-28 一种运算系统及相应的电子设备
CN201721617831.9 2017-11-28

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207503225U (zh) * 2017-11-28 2018-06-15 北京比特大陆科技有限公司 一种运算系统及相应的电子设备
WO2019105332A1 (fr) * 2017-11-28 2019-06-06 Bitmain Technologies Inc. Puce de circuit intégré de calcul et carte à circuit imprimé correspondant
WO2020107460A1 (fr) * 2018-11-30 2020-06-04 北京比特大陆科技有限公司 Procédé informatique, puce, et système, support d'informations lisible, et produit programme d'ordinateur
WO2024103394A1 (fr) * 2022-11-18 2024-05-23 Ge Yang Théorie de jetons financiers et de jetons web3

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090187615A1 (en) * 2005-12-16 2009-07-23 Matsushita Electric Industrial Co., Ltd. Digital filter
CN106407008A (zh) * 2016-08-31 2017-02-15 北京比特大陆科技有限公司 挖矿业务处理方法、装置和系统
CN207503225U (zh) * 2017-11-28 2018-06-15 北京比特大陆科技有限公司 一种运算系统及相应的电子设备

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090187615A1 (en) * 2005-12-16 2009-07-23 Matsushita Electric Industrial Co., Ltd. Digital filter
CN106407008A (zh) * 2016-08-31 2017-02-15 北京比特大陆科技有限公司 挖矿业务处理方法、装置和系统
CN207503225U (zh) * 2017-11-28 2018-06-15 北京比特大陆科技有限公司 一种运算系统及相应的电子设备

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