WO2020001145A1 - 平板探测器及其制备方法 - Google Patents

平板探测器及其制备方法 Download PDF

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Publication number
WO2020001145A1
WO2020001145A1 PCT/CN2019/084055 CN2019084055W WO2020001145A1 WO 2020001145 A1 WO2020001145 A1 WO 2020001145A1 CN 2019084055 W CN2019084055 W CN 2019084055W WO 2020001145 A1 WO2020001145 A1 WO 2020001145A1
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WIPO (PCT)
Prior art keywords
substrate
conductive layer
transparent conductive
panel detector
flat panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/084055
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English (en)
French (fr)
Inventor
张勇
华刚
薛艳娜
林坚
包智颖
米磊
白璐
方浩博
王景棚
张丽敏
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Filing date
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/609,978 priority Critical patent/US11404469B2/en
Priority to KR1020207018739A priority patent/KR102435880B1/ko
Priority to JP2019564142A priority patent/JP7515255B2/ja
Priority to EP19825780.0A priority patent/EP3817052B1/en
Publication of WO2020001145A1 publication Critical patent/WO2020001145A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/189—X-ray, gamma-ray or corpuscular radiation imagers
    • H10F39/1898—Indirect radiation image sensors, e.g. using luminescent members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/016—Manufacture or treatment of image sensors covered by group H10F39/12 of thin-film-based image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/024—Manufacture or treatment of image sensors covered by group H10F39/12 of coatings or optical elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/189—X-ray, gamma-ray or corpuscular radiation imagers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/805—Coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections

Definitions

  • the present disclosure relates to the field of ray detection technology, and in particular, to a flat panel detector.
  • X-ray flat panel detector is an X-ray detector with photoelectric conversion array as the core. Under X-ray irradiation, the scintillator or phosphor layer of the detector converts X-ray photons into visible light, and then changes from an array with photoelectric conversion to an image electrical signal. It is digitized through transmission of peripheral circuits and analog-to-digital conversion. image.
  • a flat panel detector includes a substrate, and a plurality of photodiodes disposed on the substrate.
  • the flat panel detector further includes a first transparent conductive layer disposed on a side of the plurality of photodiodes away from the substrate, an orthographic projection of the first transparent conductive layer on the substrate and the plurality of photodiodes.
  • the orthographic projections of the individual photodiodes on the substrate on the substrate at least partially overlap.
  • the orthographic projection of the first transparent conductive layer on the substrate covers the orthographic projections of the plurality of photodiodes on the substrate.
  • the first transparent conductive layer is configured to be electrically connected to a fixed potential.
  • the flat panel detector further includes a signal line connected to the photodiode to provide an operating voltage to the photodiode.
  • the signal line is disposed between the first transparent conductive layer and the photodiode.
  • a passivation layer is disposed between the first transparent conductive layer and the signal line.
  • the first transparent conductive layer is in direct contact with the signal line.
  • the first transparent conductive layer includes a plurality of conductive patterns, and the plurality of conductive patterns are connected by a conductive connection portion.
  • a plurality of gate scan lines and a plurality of data lines are further provided on the substrate, and the plurality of gate scan lines and the plurality of data lines intersect to form a plurality of arrays.
  • Photosensitive areas, the plurality of conductive patterns are respectively located in the plurality of photosensitive areas, and each photosensitive area includes at least one photodiode; the orthographic projection of each conductive pattern on the substrate and the corresponding photosensitive area The orthographic projection of the at least one photodiode on the substrate at least partially overlaps.
  • a thin film transistor electrically connected to the gate scan line, the data line, and the photodiode is further disposed on the substrate, and the thin film transistor is located outside the photosensitive region.
  • the orthographic projection of the signal line on the substrate covers the orthographic projection of the active layer of the thin film transistor on the substrate.
  • the first transparent conductive layer is made of a transparent conductive material.
  • the substrate includes a binding region
  • the flat panel detector further includes a conductive pattern disposed in the binding region, the conductive pattern and the first transparent conductive layer being formed of the same material On the same floor.
  • the first transparent conductive layer is a continuous planar conductive layer, which covers the entire photosensitive area of the flat panel detector.
  • a plurality of gate scan lines and a plurality of data lines are further provided on the substrate, and the substrate is further provided with the gate scan lines, the data lines, and the photodiodes, respectively.
  • Electrically connected thin film transistor Electrically connected thin film transistor.
  • the first transparent conductive layer has an opening corresponding to the thin film transistor, and an orthographic projection of the opening on the substrate overlaps an orthographic projection of the thin film transistor on the substrate.
  • the flat panel detector further includes a second transparent conductive layer on each side of each of the plurality of photodiodes near the signal line, and the second transparent conductive layer is on the substrate.
  • the orthographic projection is located within the orthographic projection of the photodiode on the substrate.
  • Another embodiment of the present disclosure provides a method for preparing a flat panel detector, including:
  • a photodiode is formed on the substrate; a first transparent conductive layer is formed on the substrate on which the photodiode is formed, and the orthographic projection of the first transparent conductive layer on the substrate and the orthographic projection of the photodiode on the substrate are at least Partial overlap.
  • the preparation method further includes: forming a signal line connected to the photodiode on the substrate, the signal line is used to provide an operating voltage to the photodiode; and forming on the signal line The first transparent conductive layer.
  • the signal line is in direct contact with the first transparent conductive layer.
  • the preparation method further includes: before forming the first transparent conductive layer, forming a passivation layer on the signal line.
  • the substrate includes a binding region
  • the preparation method further includes: while forming the first transparent conductive layer, using the same material as the first transparent conductive layer in the The binding region forms a conductive pattern.
  • FIG. 1 is a schematic structural diagram of a flat panel detector according to an embodiment of the present disclosure
  • FIG. 2 is a schematic partial cross-sectional view of a flat panel detector according to an embodiment of the present disclosure
  • FIG. 3 is a schematic partial cross-sectional view of a flat panel detector according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic plan view of a flat panel detector provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic partial cross-sectional view of a flat panel detector according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic partial cross-sectional view of a flat panel detector according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic partial plan view of a flat panel detector according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic partial plan view of a flat panel detector according to another embodiment of the present disclosure.
  • FIG. 9 schematically illustrates a partial cross-sectional view of a flat panel detector according to another embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view schematically illustrating a binding region of a flat panel detector according to an embodiment of the present disclosure
  • 11 and 12 are partial top views of a flat panel detector according to another embodiment of the present disclosure.
  • FIG. 13 is a flowchart of a method for manufacturing a flat panel detector according to an embodiment of the present disclosure.
  • FIG. 1 schematically illustrates a structure of a flat panel detector provided according to an embodiment of the present disclosure.
  • each photosensitive area of the flat panel detector (the area surrounded by the gate scanning lines 13 and the data lines 14 is similar to the pixel area of a liquid crystal display) includes a photodiode 11 and a thin film transistor 12.
  • the gate is connected to the gate scanning line 13 of the flat panel detector
  • the drain of the thin film transistor 12 is connected to the data line 14 of the flat panel detector
  • the source of the thin film transistor 12 is connected to the photodiode 11
  • one end of the data line 14 is electrically connected to ⁇ ⁇ ⁇ 15 ⁇ Data driving circuit 15.
  • the flat panel detector controls the switching state of the thin film transistor 12 by scanning the driving circuit 16.
  • the photocurrent signal generated by the photodiode 11 is read by the data driving circuit 15 through the data line 14 connected to the thin film transistor 12. Out.
  • the photoelectric signal acquisition is completed by controlling the signal timing on the gate scanning line 13, that is, the photocurrent signal generated by the photodiode 11 is completed by controlling the switching state of the thin film transistor 12.
  • FIG. 2 is a schematic partial cross-sectional view of an amorphous silicon type flat panel detector provided according to an example of the present disclosure.
  • the main structure of the flat panel detector includes a substrate 10, a photodiode 11 and a thin film transistor 12 disposed on the substrate 10, a flat layer 17 covering the photodiode 11 and the thin film transistor 12, and a flat layer 17 disposed on the flat layer 17. Flashing layer 18.
  • the photodiode 11 may include an N-type semiconductor layer, an intrinsic semiconductor layer, and a P-type semiconductor layer.
  • the thin film transistor 12 includes a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode, a drain electrode of the thin film transistor, and a photodiode.
  • N-type semiconductor layers are connected.
  • X-rays are modulated by a detection object.
  • the modulated X-rays are converted into visible light by the scintillation layer 18, and the visible light is absorbed by the photodiode 11 and converted into charge carriers.
  • the charge carriers can be stored in a storage capacitor or the photodiode's own capacitance.
  • a charge image is formed.
  • the scan driving circuit 16 can sequentially turn on each row of thin film transistors 11 and output the charge image to the data driving circuit 15 in a row-by-row manner.
  • the charge image transmitted through each thin film transistor 12 corresponds to the amount of incident X-rays, and the amount of X-rays received in each photosensitive region can be determined by determining the amount of charge in each photosensitive region.
  • the inventors of the present application have realized that the flat panel detector described above does not have a box substrate, and only a thin passivation layer on the top layer serves as a protective layer. Therefore, such a flat-panel detector is extremely susceptible to external static electricity, resulting in abnormal images.
  • a flat panel detector includes a substrate and a plurality of photodiodes disposed on the substrate.
  • the flat panel detector further includes a first transparent conductive layer disposed on a side of the photodiode away from the substrate, an orthographic projection of the first transparent conductive layer on the substrate, and each photodiode of the plurality of photodiodes.
  • the orthographic projections on the substrate overlap at least partially. That is, at least a part of the first transparent conductive layer is located directly above the photodiode in the thickness direction (vertical direction) of the flat panel detector.
  • the first transparent conductive layer When the flat panel detector is in a working state, the first transparent conductive layer may be electrically connected to a fixed potential (for example, a reference potential, etc.).
  • the electrostatic charge above the photodiode can be conducted or transferred via the first transparent conductive layer, so as to prevent the electrostatic charge from affecting the photodiode and affecting the accuracy of the flat panel detector detection.
  • the first transparent conductive layer since the first transparent conductive layer is transparent, it does not affect the transmission of light to the photodiode.
  • the flat panel detector provided in the foregoing embodiment will be specifically described below through a specific example.
  • the flat panel detector includes a substrate 10, a plurality of photodiodes 11 disposed on the substrate 10, and a side of the photodiode 11 away from the substrate 10 and connected to the photodiode.
  • the signal line 19 connected to 11 also includes a first transparent conductive layer 20 disposed on the side of the photodiode 11 away from the substrate 10.
  • the orthographic projection of the first transparent conductive layer 20 on the substrate 10 and the photodiode 11 on the substrate 10 The orthographic projections at least overlap.
  • the signal line 19 is used to provide a bias voltage signal to the photodiode 11, for example, a negative constant voltage source to which the signal line 19 is electrically connected.
  • a second transparent conductive layer 21 is provided on the side of the photodiode 11 near the signal line 19 to increase the signal line 19 and the photodiode 11 of contact area.
  • the first transparent conductive layer 20 and the signal line 19 are both disposed on the side of the photodiode 11 away from the substrate 10, but the relative positions of the first transparent conductive layer 20 and the signal line 19 are not limited. .
  • the first transparent conductive layer 20 is disposed on the signal line 19 side away from the photodiode 11, or the signal line 19 is disposed on the side of the first transparent conductive layer 20 away from the photodiode 11.
  • the first transparent conductive layer 20 and the signal line 19 may be directly connected, and there may also be an interlayer insulating layer therebetween.
  • the structure of FIG. 3 is only an example.
  • the orthographic projection of the first transparent conductive layer 20 on the substrate 10 and the orthographic projection of the single photodiode 11 on the substrate 10 at least partially overlap. That is, the orthographic projection of the first transparent conductive layer 20 on the substrate 10 and the orthographic projection of the photodiode 11 on the substrate 10 partially overlap, or the orthographic projection of the first transparent conductive layer 20 on the substrate 10 may be partially overlapped.
  • the projection includes an orthographic projection of the photodiode 11 on the substrate 10.
  • the orthographic projection of the photodiode 11 on the substrate 10 may also include an orthographic projection of the first transparent conductive layer 20 on the substrate 10.
  • a conductive material with a light transmittance of 50% or more in the PIN operating band may be selected.
  • a transparent conductive material may be selected.
  • IZO Indium Zinc Oxide
  • ITO Indium Tin Oxide
  • AZO Al Zinc Oxide, aluminum zinc oxide
  • IFO Indium Oxide, indium fluoride oxide
  • the first transparent conductive layer 20 may include a plurality of conductive patterns respectively corresponding to the plurality of photodiodes, and an orthographic projection of each conductive pattern on the substrate and the plurality of photoelectric The corresponding one of the photodiodes has an orthographic projection on the substrate at least partially overlapping.
  • the first transparent conductive layer 20 may be a planar whole, corresponding to all the photodiodes 11.
  • the first transparent conductive layer 20 is provided on the side of the photodiode 11 away from the substrate 10, so that during the working process of the flat panel detector, the first transparent conductive layer 20 carrying a voltage can be Isolates external static electricity from the photodiode 11 and does not affect visible light on the photodiode 11, thereby mitigating the impact of external static electricity on the photodiode 11, improving the anti-static ability of the flat panel detector, and ensuring the yield of the obtained picture .
  • the orthographic projection of the first transparent conductive layer 20 on the substrate 10 Covers the orthographic projection of the photodiode 11 on the substrate 10.
  • the signal line 19 may be electrically connected to the photodiode 11 through the first transparent conductive layer 20.
  • the signal line 19 is disposed between the first transparent conductive layer 20 and the photodiode 11. That is, the first transparent conductive layer 20 is disposed on the side of the signal line 19 away from the photodiode 11, and other interlayer structures may be provided therebetween, and the two may also be in direct contact.
  • the first transparent conductive layer 20 can protect the signal line 19, On the other hand, it is not necessary to form a via hole in the first transparent conductive layer 20, which is beneficial to the first transparent conductive layer 20 to completely cover the photodiode 11.
  • a passivation layer 22 is disposed between the first transparent conductive layer 20 and the signal line 19.
  • the signal line can be fully protected, and the surface of the flat-panel detector is also facilitated.
  • the first transparent conductive layer 20 is directly disposed on the surface of the signal line 19. That is, after the signal line 19 is prepared, the first transparent conductive layer 20 is directly prepared without preparing the passivation layer 22, which can avoid the influence of process fluctuations in the preparation of the passivation layer 22 and cause the signal line 19 to be over-etched.
  • the first transparent conductive layer 20 is disposed on the surface of the signal line 19.
  • each of the signal lines 19 used in the photodiodes in different columns and rows can be electrically connected to each other through the first transparent conductive layer 20.
  • the total impedance of the signal line of the flat panel detector can be reduced, thereby reducing the voltage drop on the signal line, and reducing the difference between the working voltages received by the photodiodes at different positions in the flat panel detector.
  • the compensation of the working voltage signal can protect the signal line 19, so that the signal stability on the signal line 19 can be improved.
  • the potential of the first transparent conductive layer is the same as the potential of the signal line 19, and therefore, a separate signal source is not required to provide a signal to the first transparent conductive layer 20, which simplifies Structure of a flat panel detector.
  • the first transparent conductive layer 20 includes a plurality of conductive patterns 201, and each conductive pattern 201 corresponds to a photodiode 11; the conductive patterns 201 are connected between the plurality of conductive patterns 201. connection.
  • FIG. 8 schematically illustrates a structural diagram of a flat panel detector when the first transparent conductive layer 20 is not provided
  • FIG. 7 schematically illustrates a structural diagram of a flat panel detector provided with the first transparent conductive layer 20.
  • one conductive pattern 201 corresponds to one photodiode 11.
  • one conductive pattern 201 may correspond to multiple photodiodes 11.
  • the coverage area of the conductive connection portion 23 intersects with the coverage area of the gate scan line 13 or the data line 14.
  • the conductive connection portion 23 connects a plurality of conductive patterns 201 in the flat panel detector as a whole. As shown in FIG. 7, it is not necessary to provide a conductive connection portion 23 between any two adjacent conductive patterns 201. It is sufficient to set the number so that a plurality of conductive patterns 201 in the flat panel detector can communicate with each other. Of course, in order to ensure the stability of the connection, more conductive connection portions 23 may be provided.
  • the shape and installation position of the conductive connection portion 23 illustrated in FIG. 7 are only schematic, and do not limit the present application in any way.
  • the plurality of conductive patterns 201 are connected through the conductive connection portion 23.
  • the conductive patterns 201 in the entire flat panel detector can receive the same voltage signal.
  • a plurality of the conductive patterns 201 are in different columns and different rows.
  • the signal lines 19 are electrically connected to each other through the conductive pattern 201. As mentioned above, this can compensate for the voltage signal on the signal line 19, improve the uniformity of the signal on the signal line 19 at different positions of the flat panel detector, and thus improve The quality of the captured picture.
  • the substrate 10 is further provided with a thin film transistor 12 connected to the photodiode 11 and a gate scan line 13 and a data line 14 connected to the thin film transistor 12.
  • the plurality of gate scanning lines 13 and the plurality of data lines 14 intersect to form a plurality of photosensitive regions arranged in an array, and the conductive pattern 201 is located in the photosensitive regions.
  • a bottom-gate thin film transistor is taken as an example for illustration, but this does not limit the protection scope of the present application.
  • one conductive pattern 201 corresponds to one photodiode 11, and the conductive pattern 201 is located in the photosensitive region.
  • the conductive pattern does not overlap with the gate scan line 13 and the data line 14.
  • the thin film transistor 12 includes a gate electrode 121, a source electrode 122, and a drain electrode 123; an orthographic projection of the gate electrode 121 on the substrate 10 and an orthographic projection of the source electrode 122 on the substrate 10 Both the projection and the orthographic projection of the drain electrode 123 on the substrate 10 do not overlap with the orthographic projection of the conductive pattern 201 on the substrate 10. That is, the thin film transistor 12 is located outside the photosensitive region. As shown in FIG. 5, along the thickness direction of the flat panel detector, the first transparent conductive layer 20 is not provided directly above the gate 121, the source electrode 122, and the drain electrode 123 of the thin film transistor 12, that is, the conductive pattern 201 is not provided. .
  • the influence of the conductive pattern 201 on the performance of the thin film transistor 12 can be avoided or reduced, that is, the orthographic projection of the conductive pattern 201 on the substrate 10 covers the orthographic projection of the photodiode 11 on the substrate 10 and does not cover the thin film transistor.
  • the signal line 19 does not shield the active layer of the thin film transistor 12 to simplify the layout of the signal line 19.
  • the orthographic projection of the signal line 19 on the substrate 10 covers the orthographic projection of the active layer 124 of the thin film transistor 12 on the substrate 10 so that the signal line 19
  • the active layer 124 has a shielding effect and prevents the active layer 124 from generating light carriers due to light.
  • the signal line 19 does not block the active layer of the thin film transistor 12, and the flat panel detector includes a light shielding layer 25.
  • the light shielding layer 25 is disposed above the active layer 124 to prevent The source layer 124 generates light carriers due to light.
  • a second transparent conductive layer 21 is provided on the side of the photodiode 11 near the signal line 19, and the second transparent conductive layer 21 exposes a part of the photodiode 11, that is, the orthographic projection of the second transparent conductive layer 21 on the substrate 10. It is located within the orthographic projection of the photodiode 11 on the substrate, thereby reducing or avoiding the edge leakage current of the photodiode.
  • the substrate 10 of the flat panel detector includes a binding region.
  • the flat panel detector further includes a conductive pattern disposed in the bonding region.
  • the conductive pattern and the first transparent conductive layer 20 may be formed on the same layer.
  • the related data signal transmission lines (for example, gate lines, data lines) in the flat panel detector can be electrically connected to external circuits (for example, integrated circuit chips) via the bonding area, thereby providing necessary electrical components on the substrate 10 Control signals and analyze and process the electrical signals collected by the flat panel detector.
  • the aforementioned data signal transmission line may be extended to a binding area, and the binding area may include a conductive pattern corresponding to the aforementioned data signal transmission line, and the conductive pattern may be formed above the data signal transmission line and electrically connected thereto.
  • the conductive pattern of the binding region can be exposed to the outside.
  • the external circuit can be conveniently connected to the conductive pattern, thereby also connecting the external circuit to the data signal transmission line.
  • the conductive pattern is provided to protect the data signal transmission line.
  • FIG. 10 is based on FIG. 9, and an example of a schematic cross-sectional view of a binding area is added.
  • a gate line 26 electrically connected to the gate of the thin film transistor is formed on the binding region of the base substrate 10.
  • An insulating layer and a conductive pattern 25 are formed above the gate line 26. Connect to the gate line.
  • the external circuit can be electrically connected to the grid lines in the flat panel detector via the conductive pattern 25 to provide control signals to the grid lines.
  • the conductive patterns of the first transparent conductive layer 20 and the binding region are formed using the same material, and therefore, the conductive patterns of the first transparent conductive layer 20 and the binding region can be formed in the same patterning process.
  • the number of mask processes is not increased, and only the pattern of the mask plate needs to be changed, thereby simplifying the manufacturing process of the flat panel detector.
  • the first transparent conductive layer may be a continuous planar conductive layer, which covers the entire photosensitive area of the flat panel detector.
  • FIG. 11 schematically illustrates an example in which the first transparent conductive layer 20 covers the entire photosensitive area of the flat panel detector.
  • a plurality of openings corresponding to each thin film transistor may be formed on the continuous planar conductive layer. For example, as shown in FIG. 12, the orthographic projection of the opening 202 corresponding to each thin film transistor on the substrate and The orthographic projections of the corresponding thin film transistors on the substrate overlap.
  • Another embodiment of the present disclosure also provides a method for preparing a flat panel detector. As shown in FIG. 13, the method includes the following steps:
  • a photodiode 11 is formed on the substrate 10.
  • a first transparent conductive layer 20 is formed on the substrate 10 on which the photodiode 11 is formed.
  • the orthographic projection of the first transparent conductive layer 20 on the substrate 10 and the orthographic projection of the photodiode 11 on the substrate 10 at least partially overlap. .
  • step S20 includes:
  • a signal line 19 connected to the photodiode 11 is formed on the substrate 10 on which the photodiode 11 is formed, and the signal line 19 is used to provide an operating voltage to the photodiode.
  • a first transparent conductive layer 20 is formed on the substrate 10 on which the signal lines 19 are formed.
  • a signal line 19 is formed first, and then a first transparent conductive layer 20 is formed.
  • the orthographic projection of the first transparent conductive layer 20 on the substrate 10 covers the orthographic projection of the photodiode 11 on the substrate 10.
  • the first transparent conductive layer 20 is formed after the passivation layer 22 is formed on the substrate 10 on which the signal lines 19 are formed.
  • the substrate further includes a binding region.
  • a conductive pattern located in the binding region is formed in the same patterning process. That is, the conductive patterns of the first transparent conductive layer 20 and the binding region are formed simultaneously.
  • the process of preparing the flat panel detector shown in FIG. 5 may include the following steps:
  • a thin film transistor 12 is formed on a substrate 10.
  • step S100 includes: S110, forming a gate on the substrate 10.
  • S120 A gate insulating layer is formed on the substrate 10 on which the gate is formed.
  • S120. An active layer is formed on the substrate 10 on which the gate insulating layer is formed.
  • S120. A source electrode and a drain electrode are formed on the substrate 10 on which the active layer is formed.
  • S200. A photodiode 11 is formed on the substrate 10 on which the thin film transistor 12 is formed.
  • step S200 includes: S210, forming an N-type semiconductor layer on the substrate 10 on which the thin film transistor 12 is formed.
  • An intrinsic semiconductor layer is formed on the substrate 10 on which the N-type semiconductor layer is formed.
  • a P-type semiconductor layer is formed on the substrate 10 on which the intrinsic semiconductor layer is formed.
  • a flat layer 17 is formed on the substrate 10 on which the photodiode 11 is formed.
  • S400, a signal line 19 is formed on the substrate 10 on which the flat layer 17 is formed.
  • a passivation layer 22 is formed on the substrate 10 on which the signal lines 19 are formed.
  • a first transparent conductive layer 20 is formed on the substrate 10 on which the passivation layer 22 is formed.
  • the orthographic projection of the first transparent conductive layer 20 on the substrate 10 covers the orthographic projection of the photodiode 11 on the substrate 10.
  • a scintillation layer 18 is formed on the substrate 10 on which the first
  • the preparation of the flat-panel detector shown in FIG. 6 may include the following steps:
  • a thin film transistor 12 is formed on a substrate 10.
  • a photodiode 11 is formed on the substrate 10 on which the thin film transistor 12 is formed.
  • a flat layer 17 is formed on the substrate 10 on which the photodiode 11 is formed.
  • a signal line 19 is formed on the substrate 10 on which the flat layer 17 is formed.
  • a first transparent conductive layer 20 is formed on the substrate 10 on which the signal lines 19 are formed.
  • the orthographic projection of the first transparent conductive layer 20 on the substrate 10 covers the orthographic projection of the photodiode 11 on the substrate 10.
  • a first transparent conductive layer 20 and a conductive pattern are simultaneously formed on the substrate 10 on which the signal lines 19 are formed.
  • the orthographic projection of the first transparent conductive layer 20 on the substrate 10 covers the photodiode 11 on the substrate 10 Orthographic projection, the first transparent conductive layer 20 is located in the photosensitive area, and the conductive pattern is located in the binding area.
  • a scintillation layer 18 is formed on the substrate 10 on which the first transparent conductive layer 20 is formed.
  • an insulation layer or a passivation layer can also be added between the layers as needed.

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Abstract

提供了一种平板探测器，其包括衬底、设置在衬底上的多个光电二极管；还包括设置在光电二极管远离所述衬底一侧的第一透明导电层，第一透明导电层在衬底上的正投影与多个光电二极管的各个光电二极管在衬底上的正投影至少部分重叠。该平板探测器可以缓解或降低外部静电的影响，提升工作稳定性。

Description

平板探测器及其制备方法
相关申请的交叉引用
本申请要求于2018年6月29日向中国专利局提交的专利申请201810712771.1的优先权利益，并且在此通过引用的方式将该在先申请的内容并入本文。
技术领域
本公开涉及射线探测技术领域，尤其涉及一种平板探测器。
背景技术
X射线平板探测器是一种以光电转换阵列为核心的X射线探测器。在X射线照射下，探测器的闪烁体或荧光体层将X射线光子转换为可见光，而后由具有光电转换作用的阵列变为图像电信号，通过外围电路的传输及模拟数字转换，从而获得数字化图像。
发明内容
根据本公开的实施例提供的平板探测器，其包括衬底、设置在所述衬底上的多个光电二极管。该平板探测器还包括设置在所述多个光电二极管远离所述衬底一侧的第一透明导电层，所述第一透明导电层在所述衬底上的正投影与所述多个光电二极管中的各个光电二极管在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述第一透明导电层在所述衬底上的正投影覆盖所述多个光电二极管在所述衬底上的正投影。
在一些实施例中，第一透明导电层被配置成电连接至固定电位。
在一些实施例中，所述平板探测器还包括与所述光电二极管连接以向所述光电二极管提供工作电压的信号线。
在一些实施例中，所述信号线设置在所述第一透明导电层与所述光电二极管之间。
在一些实施例中，所述第一透明导电层与所述信号线之间设置有钝化层。
在一些实施例中，所述第一透明导电层与所述信号线直接接触。
在一些实施例中，所述第一透明导电层包括多个导电图案，所述多个导电图案之间通过导电连接部连接。
在一些实施例中，所述衬底上还设置有多条栅极扫描线和多条数 据线，所述多条栅极扫描线和所述多条数据线交叉形成呈阵列排布的多个感光区，所述多个导电图案分别位于所述多个感光区内，每个感光区内包括至少一个光电二极管，每个导电图案在所述衬底上的正投影与对应的感光区内的所述至少一个光电二极管在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述衬底上还设置有分别与所述栅极扫描线、所述数据线以及所述光电二极管电连接的薄膜晶体管，所述薄膜晶体管位于所述感光区之外。
在一些实施例中，所述信号线在所述衬底上的正投影覆盖所述薄膜晶体管的有源层在所述衬底上的正投影。
在一些实施例中，所述第一透明导电层由透明导电材料制成。
在一些实施例中，所述衬底包括绑定区，所述平板探测器还包括设置在所述绑定区的传导图案，所述传导图案与所述第一透明导电层由相同的材料形成在同一层。
在一些实施例中，第一透明导电层是一个连续的面状导电层，其覆盖所述平板探测器的全部感光区。
在一些实施例中，衬底上还设置有多条栅极扫描线和多条数据线，所述衬底上还设置有分别与所述栅极扫描线、所述数据线以及所述光电二极管电连接的薄膜晶体管。所述第一透明导电层具有与所述薄膜晶体管对应的开口，所述开口在所述衬底上的正投影与所述薄膜晶体管在所述衬底上的正投影重叠。
在一些实施例中，平板探测器还包括处于所述多个光电二极管中的每个光电二极管靠近所述信号线一侧的第二透明导电层，所述第二透明导电层在衬底的上的正投影位于所述光电二极管在衬底上的正投影之内。
本公开的另外的实施例提供了一种平板探测器的制备方法，包括：
在衬底上形成光电二极管；形成有光电二极管的衬底上形成第一透明导电层，所述第一透明导电层在衬底上的正投影与所述光电二极管在衬底上的正投影至少部分重叠。
在一些实施例中，制备方法还包括：在所述衬底上形成与所述光电二极管连接的信号线，所述信号线用于向所述光电二极管提供工作电压；在所述信号线上形成所述第一透明导电层。
在一些实施例中，所述信号线与所述第一透明导电层直接接触。
在一些实施例中，所述制备方法还包括：在形成所述第一透明导电层之前，在所述信号线上形成钝化层。
在一些实施例中，所述衬底包括绑定区，所述制备方法还包括：在形成所述第一透明导电层的同时，采用与形成所述第一透明导电层相同的材料在所述绑定区形成传导图案。
以上概述了本公开的一些实施例，在没有矛盾和冲突的情况下，上述实施例以及这些实施例中的各个特征可以以不同的方式组合，而得到不同的另外的实施例，这些另外的实施例也属于本申请的保护范围。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的平板探测器的结构示意图；
图2为本公开实施例提供的平板探测器的示意性局部剖视图；
图3为本公开另一实施例提供的平板探测器的示意性局部剖视图；
图4为本公开一个实施例提供的平板探测器的示意性俯视图；
图5为本公开另一实施例提供的平板探测器的示意性局部剖视图；
图6为本公开另一实施例提供的平板探测器的示意性局部剖视图；
图7为本公开的又一实施例提供的平板探测器的示意性局部俯视图；
图8为本公开的再一实施例提供的平板探测器的示意性局部俯视图；
图9示意性地示出了根据本公开的另一实施例的平板探测器的局部截面图；
图10用于示意性地示出根据本公开实施例的平板探测器的绑定区的截面图；
图11和12分别为本公开的另外的实施例提供的平板探测器局部俯视图；
图13为本公开的一个实施例提供的平板探测器的制备方法的流程 图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1示意性地示出了根据本公开的一个实施例提供的平板探测器的结构。如图1所示，平板探测器的每个感光区(栅极扫描线13和数据线14围成的区域，类似于液晶显示器的像素区)包括光电二极管11和薄膜晶体管12，薄膜晶体管12的栅极与平板探测器的栅极扫描线13连接，薄膜晶体管12的漏极与平板探测器的数据线14连接，薄膜晶体管12的源极与光电二极管11连接，数据线14的一端电连接至数据驱动电路15。
平板探测器通过扫描驱动电路16来控制薄膜晶体管12的开关状态，当薄膜晶体管12被打开时，光电二极管11产生的光电流信号通过与薄膜晶体管12连接的数据线14而由数据驱动电路15读出。通过控制栅极扫描线13上的信号时序来完成光电信号的采集，即，通过控制薄膜晶体管12的开关状态来完成对光电二极管11产生的光电流信号的采集。
图2是根据本公开的一个示例提供的非晶硅型平板探测器的部分截面示意图。如图2所示，平板探测器的主体结构包括基底10，设置在基底10上的光电二极管11和薄膜晶体管12，覆盖光电二极管11和薄膜晶体管12的平坦层17以及设置在平坦层17上的闪烁层18。光电二极管11可包括N型半导体层、本征半导体层、P型半导体层，薄膜晶体管12包括栅极、栅绝缘层、有源层、源电极和漏电极，薄膜晶体管的漏电极和光电二极管的N型半导体层连接。X射线经过一检测对象被调制，调制后的X射线由闪烁层18转换为可见光，可见光被光电二极管11吸收并转换成电荷载流子，电荷载流子可存储在存储电容或者光电二极管自身电容中，形成电荷图像。扫描驱动电路16可顺序接通每一行薄膜晶体管11，以逐行的方式将电荷图像输出到数据驱动电路15。经每一薄膜晶体管12传输的电荷图像对应于入射X射线的剂 量，据此可通过确定每一感光区的电荷量来确定每一感光区所接收到的X射线剂量。
对于本公开的上述实施例，本申请的发明人意识到，上述的平板探测器没有对盒基板，其顶层仅有一层较薄的钝化层作为保护层。因此，这种平板探测器极易受到外部静电的影响，从而导致获取的图像异常。
鉴于此，根据本公开的另一实施例提供的平板探测器，其包括衬底、以及设置在衬底上的多个光电二极管。该平板探测器还包括设置在光电二极管远离所述衬底一侧的第一透明导电层，第一透明导电层在所述衬底上的正投影与所述多个光电二极管中的各个光电二极管在所述衬底上的正投影至少部分重叠。也就是说，沿平板探测器的厚度方向(竖直方向)，第一透明导电层至少有一部分是位于光电二极管的正上方。当平板探测器处于工作状态时，可让该第一透明导电层电连接至固定电位(例如，参考电位等)。光电二极管上方的静电电荷可经由该第一透明导电层被传导或转移，从而防止静电电荷影响光电二极管而影响平板探测器检测的准确性。另外，由于第一透明导电层是透光的，因此，其不会影响光线透射到光电二极管。下面通过具体的示例对上述实施例提供的平板探测器进行具体说明。
根据本公开实施例提供的平板探测器，如图3所示，包括衬底10、设置在衬底10上的多个光电二极管11以及设置在光电二极管11远离衬底10一侧且与光电二极管11连接的信号线19，还包括设置在光电二极管11远离衬底10一侧的第一透明导电层20，第一透明导电层20在衬底10上的正投影与光电二极管11在衬底10上的正投影至少部分重叠。
在实施例中，信号线19用于向光电二极管11提供偏置电压信号，例如，信号线19电连接至的负的恒压源。在一些实施例中，为了提升光电二极管11的光信号接收效果，如图3所示，在光电二极管11靠近信号线19一侧设置第二透明导电层21，以增大信号线19与光电二极管11的接触面积。
在图3的实施例中，第一透明导电层20和信号线19均设置在光电二极管11远离衬底10一侧，但第一透明导电层20和信号线19二者的相对位置不做限定。可以如图3所示，第一透明导电层20设置在 信号线19远离光电二极管11一侧，也可以是信号线19设置在第一透明导电层20远离光电二极管11一侧。第一透明导电层20和信号线19可以直接连接，二者之间也可以存在层间绝缘层，图3的结构仅为一种示例。
根据本公开的实施例，第一透明导电层20在衬底10上的正投影与单个光电二极管11在衬底10上的正投影至少部分重叠。即，可以是第一透明导电层20在衬底10上的正投影与光电二极管11在衬底10上的正投影有部分重叠，也可以是第一透明导电层20在衬底10上的正投影包含光电二极管11在衬底10上的正投影，还可以是光电二极管11在衬底10上的正投影包含第一透明导电层20在衬底10上的正投影。
在确定第一透明导电层20的材料时，例如可以选取PIN工作波段的光的透过率达到50％以上的导电材料，例如可以选取透明导电材料，示例性的，可以为IZO(Indium Zinc Oxide，铟锌氧化物)、ITO(Indium Tin Oxide，铟锡氧化物)、AZO(Al Zinc Oxide，铝锌氧化物)、IFO(Indium F Oxide，铟氟氧化物)等。
在一些实施例中，第一透明导电层20可以包括分别与所述多个光电二极管一一对应的多个导电图案，每个导电图案在所述衬底上的正投影与所述多个光电二极管中对应的一个光电二极管所述衬底上的正投影至少部分重叠。替代性地，在另外的实施例中，第一透明导电层20可以为一个面状整体，对应所有的光电二极管11。对于本公开实施例提供的平板探测器，通过在光电二极管11远离衬底10一侧设置第一透明导电层20，使得在平板探测器的工作过程中，携带电压的第一透明导电层20可将外界静电与光电二极管11隔离开，并且不会影响可见光照射到光电二极管11上，从而可以缓解外部静电对光电二极管11的影响，提升平板探测器的防静电能力，保证获取的画面的良率。
在一些实施例中，为了使第一透明导电层20能够尽可能完全的阻隔外部静电对光电二极管11产生的影响，如图4所示，第一透明导电层20在衬底10上的正投影覆盖光电二极管11在衬底10上的正投影。在第一透明导电层20设置在信号线19与光电二极管11之间的情形中，信号线19可通过第一透明导电层20与光电二极管11电连接。
在一些实施例中，如图4和图5所示，信号线19设置在第一透明 导电层20与光电二极管11之间。也就是说，第一透明导电层20设置在信号线19远离光电二极管11一侧，两者之间可以设置其他层间结构，二者也可以直接接触。在图5或图3的实施例中，通过将信号线19设置在第一透明导电层20与光电二极管11之间，一方面可以使第一透明导电层20对信号线19起到保护作用，另一方面无需在第一透明导电层20上形成过孔，有利于第一透明导电层20完全覆盖光电二极管11。
在一些实施例中，如图5所示，第一透明导电层20与信号线19之间设置有钝化层22。通过在第一透明导电层20与信号线19之间设置钝化层22，可以对信号线起到全面的保护作用，另外也有利于平板探测器的表面的平坦化。在一些实施例中，如图6或图3所示，第一透明导电层20直接设置在信号线19的表面。也就是说，在制备完信号线19后，直接制备第一透明导电层20，而不制备钝化层22，可以避免在制备钝化层22时受工艺波动影响，造成信号线19过刻，从而出现因信号线19上的信号波动影响画面品质的问题。此外，第一透明导电层20设置在信号线19的表面，一方面使用于不同列、不同行的光电二极管的各条信号线19之间可通过第一透明导电层20而彼此电连接，这样使得平板探测器的信号线的总阻抗得以降低，从而降低信号线上的压降，减小平板探测器中的不同位置的光电二极管接收到的工作电压之间的差异，实现了对信号线19上的工作电压信号的补偿。另一方面，第一透明导电层20可以起到对信号线19的保护作用，从而可以提高信号线19上信号的稳定性。此外，由于第一透明导电层20直接与信号线19接触，第一透明导电层的电位与信号线19的电位相同，因此，无需单独的信号源向第一透明导电层20提供信号，简化了平板探测器的结构。
在一些实施例中，如图7所示，第一透明导电层20包括多个导电图案201，每个导电图案201对应于一个光电二极管11；这些多个导电图案201之间通过导电连接部23连接。
图8示意性地示出了未设置第一透明导电层20时平板探测器的结构图，图7示意性地示出了设置第一透明导电层20的平板探测器的结构图。在图7的示例中，一个导电图案201对应一个光电二极管11，在另外的实施例中，一个导电图案201可对应多个光电二极管11。如 图7所示，导电连接部23的覆盖区域与栅极扫描线13或数据线14的覆盖区域存在交叉，为了避免导电连接部23与栅极扫描线13或数据线14之间形成寄生电容，从而影响光电二极管11中信号的准确性，应在确保导电图案201之间连接的基础上尽可能的缩小导电连接部23与栅极扫描线13或数据线14的重叠面积。
导电连接部23使平板探测器中的多个导电图案201连接为一个整体，如图7所示，并不是任何相邻两个导电图案201之间必须设置导电连接部23，导电连接部23的设置数量能使平板探测器中的多个导电图案201连通即可。当然，为了确保连接的稳定性，可以多设置一些导电连接部23。图7中示意的导电连接部23的形状和设置位置仅为一种示意，不对本申请构成任何限定。
多个导电图案201通过导电连接部23连接，整个平板探测器中的导电图案201可以接收到相同的电压信号，当导电图案201设置在信号线19表面时，多条处于不同列和不同行上的信号线19经过导电图案201而彼此电连接，如前所述，这可对信号线19上的电压信号进行补偿，提高平板探测器不同位置处的信号线19上信号的均一性，从而提升获取的画面的品质。
在一些实施例中，如图7所示，衬底10上还设置有与光电二极管11连接的薄膜晶体管12以及与薄膜晶体管12连接的栅极扫描线13和数据线14。多条栅极扫描线13和多条数据线14交叉形成呈阵列排布的多个感光区，导电图案201位于感光区内。图7中，以底栅型薄膜晶体管为例进行了示意说明，但这并不限定本申请的保护范围。
在一些实施例中，一个导电图案201对应一个光电二极管11，且导电图案201位于感光区内，导电图案与栅极扫描线13和数据线14不存在重叠。
在一些实施例中，如图5所示，薄膜晶体管12包括栅极121、源电极122和漏电极123；栅极121在衬底10上的正投影、源电极122在衬底10上的正投影以及漏电极123在衬底10上的正投影均与导电图案201在衬底10上的正投影无重叠。也就是说，薄膜晶体管12位于所述感光区之外。如图5所示，沿平板探测器的厚度方向，薄膜晶体管12的栅极121、源电极122和漏电极123的正上方不设置有第一透明导电层20，也就是不设置有导电图案201。由此，可避免或降低 导电图案201对薄膜晶体管12的性能的影响，即，导电图案201在衬底10上的正投影覆盖光电二极管11在衬底10上的正投影，且不覆盖薄膜晶体管12中的栅极121、源电极122以及漏电极123在衬底10上的正投影。
在一些实施例中，如图3所示，信号线19未遮挡薄膜晶体管12的有源层，以简化信号线19的布局。替代性地，在一些实施例中，如图5所示，信号线19在衬底10上的正投影覆盖薄膜晶体管12的有源层124在衬底10上的正投影，以使信号线19对有源层124起到遮挡作用，防止有源层124因光照而产生光照载流子。
根据本公开的另外的实施例，信号线19不遮挡薄膜晶体管12的有源层，平板探测器包括遮光层25，如图9所示，遮光层25布置在有源层124的上方，防止有源层124因光照而产生光照载流子。而且，光电二极管11靠近信号线19一侧设置第二透明导电层21，第二透明导电层21暴露出光电二极管11的一部分，即，第二透明导电层21在衬底10的上的正投影位于光电二极管11在衬底上的正投影之内，从而降低或避免光电二极管的边缘漏电流。在一些实施例中，平板探测器的衬底10包括绑定区，平板探测器还包括设置在绑定区的传导图案，传导图案与第一透明导电层20可由相同的材料形成在同一层。平板探测器中的相关的数据信号传输线(例如，栅线、数据线)等可经由绑定区电连接至外部电路(例如，集成电路芯片)，从而为衬底10上的电气元件提供必要的控制信号以及对平板探测器采集到的电信号进行分析和处理。前述的数据信号传输线可延伸至绑定区，绑定区可包括与前述的数据信号传输线相对应的传导图案，传导图案可形成在数据信号传输线的上方并与其电连接。绑定区的传导图案可暴露在外，这样，外部电路可方便地与传导图案连接，由此也实现了外部电路与数据信号传输线的连接。此外，传导图案的设置还可为数据信号传输线提供保护。例如，图10在图9的基础上，增加了绑定区的示意性截面图的示例。如图10所示，衬底基板10的绑定区上形成电连接至薄膜晶体管的栅极的栅线26，栅线26上方形成有绝缘层和传导图案25，传导图案25经由过孔24电连接至栅线。由此，外部电路可经由传导图案25电连接至平板探测器中的栅线，为栅线提供控制信号。
在本公开实施例中，第一透明导电层20与绑定区的传导图案采用 相同的材料形成，因此，可以在相同的构图工艺中形成第一透明导电层20与绑定区的传导图案，不增加mask(掩膜)工艺的次数，仅需改变掩膜板的图案，从而可以简化平板探测器的制备工艺。
如前所述，在一些实施例中，第一透明导电层可以是一个连续的面状导电层，其覆盖所述平板探测器的全部感光区。图11示意性地示出了这样的示例，第一透明导电层20覆盖平板探测器的全部感光区。在另外的实施例中，可以在连续面状导电层上形成与各薄膜晶体管对应的多个开口，例如，如图12所示，与各薄膜晶体管对应的开口202在衬底上的正投影与相应的薄膜晶体管在所述衬底上的正投影重叠。
本公开的另一实施例还提供一种平板探测器的制备方法，如图13所示，包括如下步骤：
S10、在衬底10上形成光电二极管11。
S20、在形成有光电二极管11的衬底10上形成第一透明导电层20，第一透明导电层20在衬底10上的正投影与光电二极管11在衬底10上的正投影至少部分重叠。
在一些实施例中，步骤S20包括：
S201、在形成有光电二极管11的衬底10上形成与光电二极管11连接的信号线19，信号线19用于向所述光电二极管提供工作电压。
S202、在形成有信号线19的衬底10上形成第一透明导电层20。
也就是说，形成光电二极管11后，先形成信号线19，再形成第一透明导电层20。
在一些实施例中，第一透明导电层20在衬底10上的正投影覆盖光电二极管11在衬底10上的正投影。
在一些实施例中，在形成有信号线19的衬底10上形成钝化层22后再形成第一透明导电层20。
为了进一步简化制备工艺，在一些实施例中，衬底还包括绑定区，在形成有第一透明导电层20时，在同一构图工艺中形成位于绑定区的传导图案。也就是说，第一透明导电层20和绑定区的传导图案同步形成。
以下，以具体的示例对本公开实施例提供的平板探测器的制备方法进行说明。
制备如图5所示的平板探测器的过程可包括如下步骤：
S100、在衬底10上形成薄膜晶体管12。
示例性的，步骤S100包括：S110、在衬底10上形成栅极。S120、在形成有栅极的衬底10上形成栅绝缘层。S120、在形成有栅绝缘层的衬底10上形成有源层。S120、在形成有有源层的衬底10上形成源电极和漏电极。S200、在形成有薄膜晶体管12的衬底10上形成光电二极管11。
示例性的，步骤S200包括：S210、在形成有薄膜晶体管12的衬底10上形成N型半导体层。S220、在形成有N型半导体层的衬底10上形成本征半导体层。S230、在形成有本征半导体层的衬底10上形成P型半导体层。S300、在形成有光电二极管11的衬底10上形成平坦层17。S400、在形成有平坦层17的衬底10上形成信号线19。S500、在形成有信号线19的衬底10上形成钝化层22。S600、在形成有钝化层22的衬底10上形成第一透明导电层20，第一透明导电层20在衬底10上的正投影覆盖光电二极管11在衬底10上的正投影。S700、在形成有第一透明导电层20的衬底10上形成闪烁层18。
制备如图6所示的平板探测器可包如下步骤：
S100、在衬底10上形成薄膜晶体管12。
S200、在形成有薄膜晶体管12的衬底10上形成光电二极管11。
S300、在形成有光电二极管11的衬底10上形成平坦层17。
S400、在形成有平坦层17的衬底10上形成信号线19。
S500、在形成有信号线19的衬底10上第一透明导电层20，第一透明导电层20在衬底10上的正投影覆盖光电二极管11在衬底10上的正投影。
或者S500′、在形成有信号线19的衬底10上同步形成第一透明导电层20和传导图案，第一透明导电层20在衬底10上的正投影覆盖光电二极管11在衬底10上的正投影，第一透明导电层20位于感光区，传导图案位于绑定区。
S600、在形成有第一透明导电层20的衬底10上形成闪烁层18。
当然，还可以根据需要在层与层之间增加绝缘层或钝化层。
以上所述，仅为本公开的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范 围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种平板探测器，包括衬底、设置在所述衬底上的多个光电二极管，
    其中所述平板探测器还包括设置在所述多个光电二极管远离所述衬底一侧的第一透明导电层，所述第一透明导电层在所述衬底上的正投影与所述多个光电二极管中的各个光电二极管在所述衬底上的正投影至少部分重叠。
  2. 根据权利要求1所述的平板探测器，其中所述第一透明导电层在所述衬底上的正投影覆盖所述多个光电二极管在所述衬底上的正投影。
  3. 根据权利要求1所述的平板探测器，其中所述第一透明导电层被配置成电连接至恒压源。
  4. 根据权利要求1所述的平板探测器，其中所述平板探测器还包括与所述光电二极管连接以向所述光电二极管提供偏置电压的信号线。
  5. 根据权利要求4所述的平板探测器，其中所述信号线设置在所述第一透明导电层与所述光电二极管之间。
  6. 根据权利要求5所述的平板探测器，其中所述第一透明导电层与所述信号线之间设置有钝化层。
  7. 根据权利要求5所述的平板探测器，其中所述第一透明导电层与所述信号线直接接触。
  8. 根据权利要求1所述的平板探测器，其中所述第一透明导电层包括多个导电图案，所述多个导电图案之间通过导电连接部连接。
  9. 根据权利要求8所述的平板探测器，其中所述衬底上还设置有多条栅极扫描线和多条数据线，所述多条栅极扫描线和所述多条数据线交叉形成呈阵列排布的多个感光区，所述多个导电图案分别位于所述多个感光区内，每个感光区内包括至少一个光电二极管，每个导电图案在所述衬底上的正投影与对应的感光区内的所述至少一个光电二极管在所述衬底上的正投影至少部分重叠。
  10. 根据权利要求9所述的平板探测器，其中所述衬底上还设置有分别与所述栅极扫描线、所述数据线以及所述光电二极管电连接的薄 膜晶体管，其中所述信号线在所述衬底上的正投影覆盖所述薄膜晶体管的有源层在所述衬底上的正投影。
  11. 根据权利要求1所述的平板探测器，其中所述第一透明导电层是一个连续的面状导电层，其覆盖所述平板探测器的全部感光区。
  12. 根据权利要求1所述的平板探测器，其中所述衬底上还设置有多条栅极扫描线和多条数据线，所述衬底上还设置有分别与所述栅极扫描线、所述数据线以及所述光电二极管电连接的薄膜晶体管，
    其中所述第一透明导电层具有与所述薄膜晶体管对应的开口，所述开口在所述衬底上的正投影与所述薄膜晶体管在所述衬底上的正投影重叠。
  13. 根据权利要求4所述的平板探测器，其中所述平板探测器还包括处于所述多个光电二极管中的每个光电二极管靠近所述信号线一侧的第二透明导电层，所述第二透明导电层在衬底的上的正投影位于所述光电二极管在衬底上的正投影之内。
  14. 根据权利要求1-13中任一项所述的平板探测器，其中所述衬底包括绑定区，
    所述平板探测器还包括设置在所述绑定区的传导图案，所述传导图案与所述第一透明导电层由相同的材料形成在同一层。
  15. 一种平板探测器的制备方法，包括：
    在衬底上形成光电二极管；
    形成有光电二极管的衬底上形成第一透明导电层，所述第一透明导电层在衬底上的正投影与所述光电二极管在衬底上的正投影至少部分重叠。
  16. 根据权利要求15所述的制备方法，还包括：
    在所述衬底上形成与所述光电二极管连接的信号线，所述信号线用于向所述光电二极管提供工作电压；
    在所述信号线上形成所述第一透明导电层。
  17. 根据权利要求16所述的制备方法，其中所述信号线与所述第一透明导电层直接接触。
  18. 根据权利要求16所述的制备方法，其中所述制备方法还包括：在形成所述第一透明导电层之前，在所述信号线上形成钝化层。
  19. 根据权利要求15-18中任一项所述的制备方法，其中所述衬底 包括绑定区，所述制备方法还包括：
    通过一次构图工艺，形成所述第一透明导电层和在所述绑定区形成传导图案。
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