WO2020002560A3 - Vorrichtung mit elektrischer kontaktstruktur - Google Patents

Vorrichtung mit elektrischer kontaktstruktur Download PDF

Info

Publication number
WO2020002560A3
WO2020002560A3 PCT/EP2019/067258 EP2019067258W WO2020002560A3 WO 2020002560 A3 WO2020002560 A3 WO 2020002560A3 EP 2019067258 W EP2019067258 W EP 2019067258W WO 2020002560 A3 WO2020002560 A3 WO 2020002560A3
Authority
WO
WIPO (PCT)
Prior art keywords
electrically conductive
contact structure
contact holes
electrical contact
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2019/067258
Other languages
English (en)
French (fr)
Other versions
WO2020002560A2 (de
Inventor
Tobias Dyck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
4JET Microtech GmbH
Original Assignee
4JET Microtech GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 4JET Microtech GmbH filed Critical 4JET Microtech GmbH
Priority to DE112019003306.9T priority Critical patent/DE112019003306A5/de
Publication of WO2020002560A2 publication Critical patent/WO2020002560A2/de
Publication of WO2020002560A3 publication Critical patent/WO2020002560A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/42—Printed circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/38—Removing material by boring or cutting
    • B23K26/382—Removing material by boring or cutting by boring
    • B23K26/386—Removing material by boring or cutting by boring of blind holes

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Multi-Conductor Connections (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Eine Vorrichtung weist eine Schichtanordnung und eine Kontaktstruktur auf. Die Schichtanordnung weist eine elektrisch leitende Schicht und eine Vielzahl von Kontaktlöchern auf. Die Kontaktstruktur weist ein elektrisch leitendes Material auf, wobei die Kontaktlöcher mindestens teilweise mit dem elektrisch leitenden Material gefüllt sind, um die elektrisch leitende Schicht elektrisch zu kontaktieren und wobei das elektrisch leitende Material in einem der Kontaktlöcher mit dem elektrisch leitenden Material in den übrigen Kontaktlöchern der Vielzahl von Kontaktlöchern elektrisch leitend verbunden ist.
PCT/EP2019/067258 2018-06-29 2019-06-27 Vorrichtung mit elektrischer kontaktstruktur Ceased WO2020002560A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112019003306.9T DE112019003306A5 (de) 2018-06-29 2019-06-27 Vorrichtung mit elektrischer kontaktstruktur

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE202018103749.8 2018-06-29
DE202018103749.8U DE202018103749U1 (de) 2018-06-29 2018-06-29 Vorrichtung mit elektrischer Kontaktstruktur

Publications (2)

Publication Number Publication Date
WO2020002560A2 WO2020002560A2 (de) 2020-01-02
WO2020002560A3 true WO2020002560A3 (de) 2020-02-20

Family

ID=62983027

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2019/067258 Ceased WO2020002560A2 (de) 2018-06-29 2019-06-27 Vorrichtung mit elektrischer kontaktstruktur

Country Status (2)

Country Link
DE (2) DE202018103749U1 (de)
WO (1) WO2020002560A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021013333A1 (en) * 2019-07-22 2021-01-28 Technische Hochschule Aschaffenburg Electrical connection pad with enhanced solderability and corresponding method for laser treating an electrical connection pad

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005062932A1 (de) * 2005-12-29 2007-07-12 Infineon Technologies Ag Chip-Träger mit reduzierter Störsignalempfindlichkeit
DE102006049562A1 (de) * 2006-10-20 2008-04-24 Qimonda Ag Substrat mit Durchführung und Verfahren zur Herstellung desselben
US20180074118A1 (en) * 2016-09-15 2018-03-15 Texas Instruments Incorporated Heatable interposer for temperature-controlled testing of semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005062932A1 (de) * 2005-12-29 2007-07-12 Infineon Technologies Ag Chip-Träger mit reduzierter Störsignalempfindlichkeit
DE102006049562A1 (de) * 2006-10-20 2008-04-24 Qimonda Ag Substrat mit Durchführung und Verfahren zur Herstellung desselben
US20180074118A1 (en) * 2016-09-15 2018-03-15 Texas Instruments Incorporated Heatable interposer for temperature-controlled testing of semiconductor devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TOBIAS DYCK: "Functional Surfaces by Laser Interference", LASER TECHNIK JOURNAL, 1 April 2017 (2017-04-01), pages 16 - 19, XP055653050, Retrieved from the Internet <URL:https://onlinelibrary.wiley.com/doi/pdf/10.1002/latj.201700007> [retrieved on 20191216], DOI: 10.1002/latj.201700007 *

Also Published As

Publication number Publication date
DE112019003306A5 (de) 2021-03-18
WO2020002560A2 (de) 2020-01-02
DE202018103749U1 (de) 2018-07-06

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