WO2020003183A1 - Division d'unités zéro - Google Patents

Division d'unités zéro Download PDF

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Publication number
WO2020003183A1
WO2020003183A1 PCT/IB2019/055433 IB2019055433W WO2020003183A1 WO 2020003183 A1 WO2020003183 A1 WO 2020003183A1 IB 2019055433 W IB2019055433 W IB 2019055433W WO 2020003183 A1 WO2020003183 A1 WO 2020003183A1
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Prior art keywords
block
units
dimensions
unit
video data
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Kai Zhang
Li Zhang
Hongbin Liu
Hsiao Chiang Chuang
Yue Wang
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Beijing ByteDance Network Technology Co Ltd
ByteDance Inc
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Beijing ByteDance Network Technology Co Ltd
ByteDance Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/157—Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/119—Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/157—Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
    • H04N19/159—Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/513—Processing of motion vectors
    • H04N19/517—Processing of motion vectors by encoding
    • H04N19/52—Processing of motion vectors by encoding by predictive encoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/96—Tree coding, e.g. quad-tree coding

Definitions

  • This patent document is directed generally to image and video coding technologies.
  • CU specialized coding unit
  • CTU coding tree unit
  • the presently disclosed technology discloses provides the zero-unit that enhances, in an example, the processing of sub blocks that are located at the borders of a block of video data (e.g., in a picture, slice, tile and the like).
  • the described methods may be applied to both the existing video coding standards (e.g., High Efficiency Video Coding (HEVC)) and future video coding standards or video codecs.
  • HEVC High Efficiency Video Coding
  • the disclosed technology may be used to provide a method for video coding, which may be implemented in a video encoder.
  • This method includes determining that a block of video data is to be coded as a zero unit (ZU) block, due to the block of video data having dimensions SxT at least one of S and T being a non-power-of two number; partitioning the ZU block into one of two units, three units, or four units; and generating a bitstream by coding the units.
  • ZU zero unit
  • another method of video processing includes receiving a bitstream corresponding to a block of video data coded as a zero unit (ZU) block partitioned into two units, three units or four units, the block of video data having dimensions SxT; and generating the block of video data by decoding the bitstream.
  • ZU zero unit
  • another method of video processing includes determining that a block of video data is to be coded as a zero unit (ZU) block due to the block having a height or a width that is a non-power-of-two number; partitioning the block of video data using a partitioning scheme, wherein the partitioning scheme partitions the block of video data into one of two units, three units, or four units; generating a bitstream by coding the block of video data, wherein the partitioning scheme is signaled using a syntax that is identical to that used for signaling partitioning of another block of video data that is a non-zero unit block.
  • ZU zero unit
  • another method of video processing includes receiving a bitstream corresponding to a block of video data that is coded as a zero unit (ZU) block due to the block of video data having dimensions SxT, at least one of S and T being a non-power-of two number, wherein the block of video data is partitioned using a partitioning scheme that partitions the block of video data into one of two units, three units, or four units, and wherein the partitioning scheme is signaled in the bitstream using a syntax that is identical to that used for signaling partitioning of a non-zero unit block; decoding, based on the signaling, the bitstream to generate the block of video data.
  • ZU zero unit
  • another method of video processing includes determining that a block of video data is to be coded as a zero unit (ZU) block due to the block of video data having dimensions SxT, at least one of S and T being a non- power-of two number; partitioning the ZU block into one of two units, three units, or four units using a partitioning scheme selected from a set of ZU block partitioning schemes; coding the units; and signaling the coded units in a bitstream.
  • the set of ZU block partitioning schemes is a subset of a set of partitioning schemes available for splitting a coding unit (CU).
  • another method of video processing is disclosed.
  • the method includes receiving a bitstream corresponding to a block of video data, the block of video data having dimensions; receiving signaling indicating that the block of video data is partitioned as a zero unit (ZU) block due to the block of video data having dimensions SxT, at least one of S and T being a non-power-of two number, the block being partitioned using a partitioning scheme selected from a set of ZU block partitioning schemes; and decoding, based on the signaling, the bitstream corresponding to the units to reconstruct the block of video data.
  • the set of ZU block partitioning schemes is a subset of a set of partitioning schemes available for splitting a coding unit (CU).
  • another method of video processing includes determining that a block of video data is to be coded as a zero unit (ZU) block due to the block of video data having dimensions, at least one of which is a non-power-of two number; partitioning the ZU block into one of two, three or four units upon determining that the ZU block is located in an I-slice or an intra-coded picture; coding the units; and signaling the coded units in a bitstream.
  • ZU zero unit
  • another method of video processing includes receiving a bitstream corresponding to a block of video data, the block of video data having dimensions; receiving signaling indicating that the block of video data includes units partitioned from a zero unit (ZU) block that has at least a height or a width that is a non-power- of-two number and is coded without a transform and a residual coding, the partitioned ZU block being located in an I-slice or an intra-coded picture; and decoding, based on the signaling, the bitstream corresponding to the units to reconstruct the block of video data.
  • ZU zero unit
  • the above-described method is embodied in the form of processor-executable code and stored in a computer-readable program medium.
  • the device may include a processor that is
  • a video decoder apparatus may implement a method as described herein.
  • FIG. 1 shows an example block diagram of a typical High Efficiency Video Coding (HE VC) video encoder and decoder.
  • HE VC High Efficiency Video Coding
  • FIG. 2 shows examples of macroblock (MB) partitions in H.264/AVC.
  • FIG. 3 shows examples of splitting coding blocks (CBs) into prediction blocks (PBs).
  • FIGS. 4A and 4B show an example of the subdivision of a coding tree block (CTB) into CBs and transform blocks (TBs), and the corresponding quadtree, respectively.
  • CB coding tree block
  • TBs transform blocks
  • FIG. 5 shows an example of a partition structure of one frame.
  • FIGS. 6A and 6B show the subdivisions and signaling methods, respectively, of a CTB highlighted in the exemplary frame in FIG. 5.
  • FIGS. 7A and 7B show an example of the subdivisions and a corresponding QTBT (quadtree plus binary tree) for a largest coding unit (ECU).
  • QTBT quadtree plus binary tree
  • FIGS. 8A-8E show examples of partitioning a coding block.
  • FIG. 9 shows an example subdivision of a CB based on a QTBT.
  • FIGS. 10A-10I show examples of the partitions of a CB supported the multi-tree type (MTT), which is a generalization of the QTBT.
  • MTT multi-tree type
  • FIG. 11 shows an example of tree-type signaling.
  • FIGS. 12A-12C show examples of CTBs crossing picture borders.
  • FIG. 13 shows an example of a zero-unit at a picture border.
  • FIG. 14 shows a flowchart of an example method for video encoding in accordance with the presently disclosed technology.
  • FIG. 15 shows a flowchart of another example method for video decoding in accordance with the presently disclosed technology.
  • FIG. 16 is a block diagram illustrating an example of the architecture for a computer system or other control device that can be utilized to implement various portions of the presently disclosed technology.
  • FIG. 17 shows a block diagram of an example embodiment of a mobile device that can be utilized to implement various portions of the presently disclosed technology.
  • FIG. 18 is a flowchart for an example method of video processing.
  • FIG. 19 is a flowchart for an example method of video processing. DETAILED DESCRIPTION
  • Video codecs typically include an electronic circuit or software that compresses or decompresses digital video, and are continually being improved to provide higher coding efficiency.
  • a video codec converts uncompressed video to a compressed format or vice versa.
  • the compressed format usually conforms to a standard video compression specification, e.g., the High Efficiency Video Coding (HEVC) standard (also known as H.265 or MPEG-H Part 2), the Versatile Video Coding standard to be finalized, or other current and/or future video coding standards.
  • HEVC High Efficiency Video Coding
  • MPEG-H Part 2 the Versatile Video Coding standard to be finalized, or other current and/or future video coding standards.
  • Embodiments of the disclosed technology may be applied to existing video coding standards (e.g., HEVC, H.265) and future standards to improve compression performance.
  • existing video coding standards e.g., HEVC, H.265
  • future standards e.g., HEVC, H.265
  • Section headings are used in the present document to facilitate ease of understanding and do not limit the embodiments disclosed in a section to only that section.
  • certain embodiments are described with reference to Versatile Video Coding or other specific video codecs, the disclosed techniques are applicable to other video coding technologies also.
  • video processing encompasses video coding or compression, video decoding or decompression and video transcoding in which video pixels are represented from one compressed format into another compressed format or at a different compressed bitrate.
  • FIG. 1 shows an example block diagram of a typical HEVC video encoder and decoder.
  • An encoding algorithm producing an HEVC compliant bitstream would typically proceed as follows. Each picture is split into block-shaped regions, with the exact block partitioning being conveyed to the decoder. The first picture of a video sequence (and the first picture at each clean random access point into a video sequence) is coded using only intra picture prediction (that uses some prediction of data spatially from region-to-region within the same picture, but has no dependence on other pictures). For all remaining pictures of a sequence or between random access points, inter-picture temporally predictive coding modes are typically used for most blocks.
  • the encoding process for inter-picture prediction consists of choosing motion data comprising the selected reference picture and motion vector (MV) to be applied for predicting the samples of each block.
  • the encoder and decoder generate identical inter-picture prediction signals by applying motion compensation (MC) using the MV and mode decision data, which are transmitted as side information.
  • MC motion compensation
  • the residual signal of the intra- or inter-picture prediction which is the difference between the original block and its prediction, is transformed by a linear spatial transform.
  • the transform coefficients are then scaled, quantized, entropy coded, and transmitted together with the prediction information.
  • the encoder duplicates the decoder processing loop (see gray-shaded boxes in FIG.
  • the quantized transform coefficients are constructed by inverse scaling and are then inverse transformed to duplicate the decoded approximation of the residual signal.
  • the residual is then added to the prediction, and the result of that addition may then be fed into one or two loop filters to smooth out artifacts induced by block-wise processing and quantization.
  • the final picture representation (that is a duplicate of the output of the decoder) is stored in a decoded picture buffer to be used for the prediction of subsequent pictures.
  • the order of encoding or decoding processing of pictures often differs from the order in which they arrive from the source;
  • decoding order i.e., bitstream order
  • output order i.e., display order
  • Video material to be encoded by HEVC is generally expected to be input as progressive scan imagery (either due to the source video originating in that format or resulting from deinterlacing prior to encoding).
  • No explicit coding features are present in the HEVC design to support the use of interlaced scanning, as interlaced scanning is no longer used for displays and is becoming substantially less common for distribution.
  • a metadata syntax has been provided in HEVC to allow an encoder to indicate that interlace-scanned video has been sent by coding each field (i.e., the even or odd numbered lines of each video frame) of interlaced video as a separate picture or that it has been sent by coding each interlaced frame as an HEVC coded picture. This provides an efficient method of coding interlaced video without burdening decoders with a need to support a special decoding process for it.
  • the core of the coding layer in previous standards was the macroblock, containing a 16x 16 block of luma samples and, in the usual case of 4:2:0 color sampling, two corresponding 8x8 blocks of chroma samples.
  • An intra-coded block uses spatial prediction to exploit spatial correlation among pixels. Two partitions are defined: 16x16 and 4x4.
  • An inter-coded block uses temporal prediction, instead of spatial prediction, by estimating motion among pictures.
  • Motion can be estimated independently for either 16x16 macroblock or any of its sub-macroblock partitions: 16x8, 8x16, 8x8, 8x4, 4x8, 4x4, as shown in FIG. 2. Only one motion vector (MV) per sub-macroblock partition is allowed.
  • a coding tree unit (CTU) is split into coding units (CUs) by using a quadtree structure denoted as coding tree to adapt to various local characteristics.
  • the decision whether to code a picture area using inter-picture (temporal) or intra-picture (spatial) prediction is made at the CU level.
  • Each CU can be further split into one, two or four prediction units (PUs) according to the PU splitting type. Inside one PU, the same prediction process is applied and the relevant information is transmitted to the decoder on a PU basis.
  • a CU After obtaining the residual block by applying the prediction process based on the PU splitting type, a CU can be partitioned into transform units (TUs) according to another quadtree structure similar to the coding tree for the CU.
  • transform units transform units
  • One of key feature of the HEVC structure is that it has the multiple partition conceptions including CU, PU, and TU.
  • Certain features involved in hybrid video coding using HEVC include:
  • Coding tree units and coding tree block (CTB) structure
  • the analogous structure in HEVC is the coding tree unit (CTU), which has a size selected by the encoder and can be larger than a traditional macroblock.
  • the CTU consists of a luma CTB and the corresponding chroma CTBs and syntax elements.
  • HEVC then supports a partitioning of the CTBs into smaller blocks using a tree structure and quadtree-like signaling.
  • Coding units CUsf and coding blocks (CBsf:
  • the quadtree syntax of the CTU specifies the size and positions of its luma and chroma CBs.
  • the root of the quadtree is associated with the CTU.
  • the size of the luma CTB is the largest supported size for a luma CB.
  • the splitting of a CTU into luma and chroma CBs is signaled jointly.
  • a CTB may contain only one CU or may be split to form multiple CUs, and each CU has an associated partitioning into prediction units (PUs) and a tree of transform units (TUs).
  • PUs prediction units
  • TUs tree of transform units
  • PBsj The decision whether to code a picture area using inter picture or intra picture prediction is made at the CU level.
  • a PU partitioning structure has its root at the CU level.
  • the luma and chroma CBs can then be further split in size and predicted from luma and chroma prediction blocks (PBs).
  • HEVC supports variable PB sizes from 64x64 down to 4x4 samples.
  • FIG. 3 shows examples of allowed PBs for an MxM CU.
  • Transform units (Tusj and transform blocks:
  • the prediction residual is coded using block transforms.
  • a TU tree structure has its root at the CU level.
  • the luma CB residual may be identical to the luma transform block (TB) or may be further split into smaller luma TBs. The same applies to the chroma TBs.
  • Integer basis functions similar to those of a discrete cosine transform (DCT) are defined for the square TB sizes 4x4, 8x8, 16x16, and 32x32.
  • DCT discrete cosine transform
  • an integer transform derived from a form of discrete sine transform (DST) is alternatively specified.
  • a CB can be recursively partitioned into transform blocks (TBs).
  • the partitioning is signaled by a residual quadtree. Only square CB and TB partitioning is specified, where a block can be recursively split into quadrants, as illustrated in FIG. 4.
  • a flag signals whether it is split into four blocks of size M/2xM/2. If further splitting is possible, as signaled by a maximum depth of the residual quadtree indicated in the SPS, each quadrant is assigned a flag that indicates whether it is split into four quadrants.
  • the leaf node blocks resulting from the residual quadtree are the transform blocks that are further processed by transform coding.
  • the encoder indicates the maximum and minimum luma TB sizes that it will use. Splitting is implicit when the CB size is larger than the maximum TB size. Not splitting is implicit when splitting would result in a luma TB size smaller than the indicated minimum.
  • the chroma TB size is half the luma TB size in each dimension, except when the luma TB size is 4x4, in which case a single 4x4 chroma TB is used for the region covered by four 4x4 luma TBs.
  • intra-picture-predicted CUs the decoded samples of the nearest-neighboring TBs (within or outside the CB) are used as reference data for intra picture prediction.
  • the HEVC design allows a TB to span across multiple PBs for inter-picture predicted CUs to maximize the potential coding efficiency benefits of the quadtree-structured TB partitioning.
  • the borders of the picture are defined in units of the minimally allowed luma CB size.
  • some CTUs may cover regions that are partly outside the borders of the picture. This condition is detected by the decoder, and the CTU quadtree is implicitly split as necessary to reduce the CB size to the point where the entire CB will fit into the picture.
  • FIG. 5 shows an example of a partition structure of one frame, with a resolution of 416x240 pixels and dimensions 7 CTBs x 4 CTBs, wherein the size of a CTB is 64x64.
  • the CTBs that are partially outside the right and bottom border have implied splits (dashed lines, indicated as 502), and the CUs that fall outside completely are simply skipped (not coded).
  • the highlighted CTB (504), with row CTB index equal to 2 and column CTB index equal to 3, has 64x48 pixels within the current picture, and doesn’t fit a 64x64 CTB. Therefore, it is forced to be split to 32x32 without the split flag signaled. For the top-left 32x32, it is fully covered by the frame. When it chooses to be coded in smaller blocks (8x8 for the top-left 16x16, and the remaining are coded in 16x16) according to rate-distortion cost, several split flags need to be coded.
  • FIGS. 6A and 6B show the subdivisions and signaling methods, respectively, of the highlighted CTB (504) in FIG. 5.
  • log2_min_luma_coding_block_size_minus3 plus 3 specifies the minimum luma coding block size
  • log2_diff_max_min_luma_coding_block_size specifies the difference between the maximum and minimum luma coding block size.
  • PicWidthlnMinCbsY PicWidthlnCtbsY, PicHeightlnMinCbsY, PicHeightlnCtbsY,
  • PicSizelnMinCbsY PicSizelnCtbsY, PicSizelnSamplesY, PicWidthlnSamplesC and
  • PicHeightlnSamplesC are derived as follows:
  • MinCbLog2SizeY log2_min_luma_coding_block_size_minus3 + 3
  • PicWidthlnMinCbsY pic width in luma samples / MinCbSizeY
  • PicWidthlnCtbsY Ceil( pic width in luma samples ⁇ CtbSizeY )
  • PicHeightlnMinCbsY pic height in luma samples / MinCbSizeY
  • PicHeightlnCtbsY Ceil( pic height in luma samples ⁇ CtbSizeY )
  • PicSizelnMinCbsY PicWidthlnMinCbsY * PicHeightlnMinCbsY
  • PicSizelnCtbsY PicWidthlnCtbsY * PicHeightlnCtbsY
  • PicSizelnSamplesY pic width in luma samples * pic height in luma samples
  • PicWidthlnSamplesC pic width in luma samples / SubWidthC
  • PicHeightlnSamplesC pic height in luma samples / SubHeightC
  • chroma format idc is equal to 0 (monochrome) or separate_colour_plane_flag is equal to 1, CtbWidthC and CtbHeightC are both equal to 0;
  • CtbWidthC and CtbHeightC are derived as follows:
  • CtbWidthC CtbSizeY / SubWidthC
  • CtbHeightC CtbSizeY / SubHeightC
  • JEM Joint Exploration Model
  • QTBT quadtree plus binary tree
  • TT ternary tree
  • the QTBT structure removes the concepts of multiple partition types, i.e. it removes the separation of the CU, PU and TU concepts, and supports more flexibility for CU partition shapes.
  • a CU can have either a square or rectangular shape.
  • a coding tree unit (CTU) is first partitioned by a quadtree structure.
  • the quadtree leaf nodes are further partitioned by a binary tree structure.
  • the binary tree leaf nodes are called coding units (CUs), and that segmentation is used for prediction and transform processing without any further partitioning.
  • a CU sometimes consists of coding blocks (CBs) of different colour components, e.g. one CU contains one luma CB and two chroma CBs in the case of P and B slices of the 4:2:0 chroma format and sometimes consists of a CB of a single component, e.g., one CU contains only one luma CB or just two chroma CBs in the case of I slices.
  • CBs coding blocks
  • CTU size the root node size of a quadtree, the same concept as in HEVC
  • MinQTSize the minimally allowed quadtree leaf node size
  • MaxBTSize the maximally allowed binary tree root node size
  • MaxBTDepth the maximally allowed binary tree depth
  • MinBTSize the minimally allowed binary tree leaf node size
  • the CTU size is set as 128x 128 luma samples with two corresponding 64x64 blocks of chroma samples
  • theMinQTSize is set as 16x
  • t e MaxBTSize is set as 64x64
  • the MinBTSize (for both width and height) is set as 4x4
  • the MaxBTDepth is set as 4.
  • the quadtree partitioning is applied to the CTU first to generate quadtree leaf nodes.
  • the quadtree leaf nodes may have a size from 16x 16 (i.e., the MinQTSize) to 128x128 (i.e., the CTU size).
  • the quadtree leaf node is also the root node for the binary tree and it has the binary tree depth as 0.
  • MaxBTDepth i.e., 4
  • no further splitting is considered.
  • MinBTSize i.e. 4
  • no further horizontal splitting is considered.
  • the binary tree node has height equal to MinBTSize
  • no further vertical splitting is considered.
  • the leaf nodes of the binary tree are further processed by prediction and transform processing without any further partitioning. In the JEM, the maximum CTU size is 256x256 luma samples.
  • FIG. 7A shows an example of block partitioning by using QTBT
  • FIG. 7B shows the corresponding tree representation.
  • the solid lines indicate quadtree splitting and dotted lines indicate binary tree splitting.
  • each splitting (i.e., non-leaf) node of the binary tree one flag is signalled to indicate which splitting type (i.e., horizontal or vertical) is used, where 0 indicates horizontal splitting and 1 indicates vertical splitting.
  • the quadtree splitting there is no need to indicate the splitting type since quadtree splitting always splits a block both horizontally and vertically to produce 4 sub-blocks with an equal size.
  • the QTBT scheme supports the ability for the luma and chroma to have a separate QTBT structure.
  • the luma and chroma CTBs in one CTU share the same QTBT structure.
  • the luma CTB is partitioned into CUs by a QTBT structure
  • the chroma CTBs are partitioned into chroma CUs by another QTBT structure. This means that a CU in an I slice consists of a coding block of the luma component or coding blocks of two chroma components, and a CU in a P or B slice consists of coding blocks of all three colour components.
  • inter prediction for small blocks is restricted to reduce the memory access of motion compensation, such that bi-prediction is not supported for 4x8 and 8x4 blocks, and inter prediction is not supported for 4x4 blocks. In the QTBT of the JEM, these restrictions are removed.
  • FIG. 8 A shows an example of quad-tree (QT) partitioning
  • FIGS. 8B and 8C show examples of the vertical and horizontal binary-tree (BT) partitioning, respectively.
  • BT binary-tree
  • ternary tree (TT) partitions e.g., horizontal and vertical center-side ternary- trees (as shown in FIGS. 8D and 8E) are supported.
  • region tree quad-tree
  • prediction tree binary-tree or ternary-tree
  • a CTU is firstly partitioned by region tree (RT).
  • a RT leaf may be further split with prediction tree (PT).
  • PT leaf may also be further split with PT until max PT depth is reached.
  • a PT leaf is the basic coding unit. It is still called CU for convenience.
  • a CU cannot be further split.
  • Prediction and transform are both applied on CU in the same way as JEM.
  • the whole partition structure is named‘multiple-type-tree’.
  • a tree structure called a Multi-Tree Type which is a generalization of the QTBT, is supported.
  • MTT Multi-Tree Type
  • a Coding Tree Unit CTU
  • the quad-tree leaf nodes are further partitioned by a binary-tree structure.
  • the structure of the MTT constitutes of two types of tree nodes: Region Tree (RT) and Prediction Tree (PT), supporting nine types of partitions, as shown in FIG. 10A to 101.
  • a region tree can recursively split a CTU into square blocks down to a 4x4 size region tree leaf node.
  • a prediction tree can be formed from one of three tree types: Binary Tree, Ternary Tree, and Asymmetric Binary Tree.
  • a PT split it is prohibited to have a quadtree partition in branches of the prediction tree.
  • JEM the luma tree and the chroma tree are separated in I slices.
  • RT signaling is same as QT signaling in JEM with exception of the context derivation.
  • up to 4 additional bins are required, as shown in FIG. 11.
  • the first bin indicates whether the PT is further split or not.
  • the context for this bin is calculated based on the observation that the likelihood of further split is highly correlated to the relative size of the current block to its neighbors.
  • the second bin indicates whether it is a horizontal partitioning or vertical partitioning.
  • the presence of the center sided triple tree and the asymmetric binary trees (ABTs) increase the occurrence of“tall” or “wide” blocks.
  • the third bin indicates the tree-type of the partition, i.e., whether it is a binary- tree/triple-tree, or an asymmetric binary tree.
  • the fourth bin indicates the type of the tree.
  • the four bin indicates up or down type for horizontally partitioned trees and right or left type for vertically partitioned trees. 1.5.1. Examples of restrictions at picture borders
  • K x L samples are within picture border.
  • the CU splitting rules on the picture bottom and right borders may apply to any of the coding tree configuration QTBT+TT, QTBT+ABT or QTBT+TT+ABT. They include the two following aspects:
  • the ternary tree split is allowed in case the first or the second border between resulting sub-CU exactly lies on the border of the picture.
  • the asymmetric binary tree splitting is allowed if a splitting line (border between two sub-CU resulting from the split) exactly matches the picture border.
  • the width or the height of a CTU or a CU may be not equal to 2 n , where N is a positive integer. These cases are difficult to handle. Specifically, may be difficult to design a transform with integer-operations excluding division, if the number of rows or columns is not in a form of 2 N .
  • the CTU or CU are forced to be split into smaller ones, until both the width and height are in the form of 2 N or by padding or using transform skip.
  • the coding gain may be further improved if treating those blocks in a more flexible way.
  • transforms are defined for CUs with the width or the height not in the form of 2 N . Such transforms are not desirable in practical video coding applications.
  • Embodiments of the presently disclosed technology overcome the drawbacks of existing implementations, thereby providing video coding with higher efficiencies.
  • the zero-unit block is proposed as a special CU/CTU, and a block is interpreted as a zero-unit if and only if its height and/or width are not of the form 2 N .
  • Example A can be further split into two (BT or ABT), three (TT, FTT) or four (QT, EQT) units.
  • a split unit split from a zero-unit can be a zero-unit, or it can be a normal CU with its width or height in the form of 2 N .
  • a zero-unit Z is with the size SxT.
  • Z can be split with BT into two units both with the size as
  • Z can be split with BT into two units both with the size as
  • Z can be split with BT into two units with the size as Sx2 N and Sx(T-2 N ), or Sx(T-2 N ) and Sx2 N .
  • Z can be split with TT into three units with the size as S/4xT,
  • Z can be split with TT into three units with the size as SxT/4,
  • Z can be split with TT into three units with the size as 2 x ' xT, 2 xx xT and (S-2 N )xT, or 2 x ' xT, (S-2 N )xT and 2 x ' xT, or (S-2 N )xT, 2 N 1 xT and 2 N 1 xT.
  • Z can be split with TT into three units with the size as Sx2 N 1 , Sx2 N 1 and Sx(T-2 N ), or Sx2 N 1 , Sx(T-2 N ) and Sx2 N 1 , or Sx(T-2 N ),
  • Z can be split with QT into four units both with the size as
  • Z can be split with QT into four units with the size as 2 N xT/2, 2 N xT/2, (S-2 N )xT/2 and (S-2 N )xT/2, or (S-2 N )xT/2, (S-2 N )xT/2, 2 N xT/2 and 2 N XT/2.
  • Z can be split with QT into four units with the size as S/2x2 N , S/2x2 N , S/2x(T-2 N ) and S/2x(T-2 N ), or S/2x(T-2 N ), S/2x(T-2 N ), S/2x2 N and S/2X2 n .
  • Z can be split with QT into four units with the size as 2 N x2 M , 2 N x2 M , (S-2 N )x(T-2 M ) and (S-2 N )x(T-2 M ), or (S-2 N )x(T- 2 m ), (S-2 N )X(T-2 m ), 2 N X2 M and 2 N x2 M , or 2 N x(T-2 M ), 2 N x(T-2 M ), (S-2 N )x 2 M and (S-2 N )x 2 M , or (S-2 N )X 2 m , (S-2 N )X 2 m , 2 N X(T-2 m ) and 2 N x(T-2 M ).
  • the width/height of all split units shall be even. If one partition structure results in a unit with either width or height to be odd, such a partition structure is automatically disallowed.
  • Z can be split with TT into three units.
  • the width and/or height of all split units shall be in a form of
  • K*M where M is the minimum width and/or height of allowed coding units/prediction units, such as 4; K is an integer larger than 0. If one partition structure results in a unit with either width or height not in such a form that partition structure is automatically disallowed.
  • width and/or height of all split non-ZUs shall be in a form of K*M, where M is the minimum width and/or height of allowed coding units/prediction units, such as 4. In this case, if a split zero unit doesn’t follow this restriction but non-ZUs follow this restriction, the partition structure is still allowed.
  • Example B The splitting signaling method of a ZU is the same to that of a normal CU.
  • splitting methods of a normal CU are allowed for a ZU.
  • the sub-set of splitting methods of a normal CU allowed for a ZU is determined by the ZU size, and/or picture/slice/tile boundary positions (bottom, right, bottom-right etc. al), and/or slice type.
  • the splitting signaling method of a ZU is still kept the same to that of a normal CU, however, the context for indications of TT (or other kinds of partition structures) may further depend on whether the current block is a ZU or not.
  • Example C In one embodiment, a ZU must be split in an I-slice or intra-coded picture.
  • the width or height of the ZU is not in the form of 2 N .
  • the CU is treated as a ZU if
  • TO and/or Tl is an integer such as 128 or 256.
  • Tl is an integer such as 128 or 256.
  • T is an integer such as 16384 or 65536.
  • FIG. 14 shows a flowchart of an exemplary method for video coding, which may be implemented in a video encoder.
  • the method 1400 includes, at step 1410, determining dimensions of a block of video data.
  • the method 1400 includes, at step 1420, signaling, upon determining that at least one of the dimensions is a non-power-of-two, the block of video data as a zero unit (ZU) block, which is untransformable.
  • ZU zero unit
  • a non-power-of-two is any non-zero number that cannot be represented in the form 2 N .
  • the integers excluding the powers of two e.g., 1, 3, 5,
  • untransformable may be defined in the context of Example 2, such that no transform, inverse-transform, quantization and de-quantization operations are invoked for a zero-unit.
  • the untransformable property of a zero-unit is that it is inferred to be coded with the skip mode, and thus, the skip mode need not be explicitly signaled.
  • untransformable may be defined in the context of Example 3, such that although there may be non-zero residuals, there are no transform and inverse-transform operations defined for a zero-unit.
  • FIG. 15 shows a flowchart of another exemplary method for video coding, which may be implemented in a video decoder.
  • This flowchart includes some features and/or steps that are similar to those shown in FIG. 14, and described above. At least some of these features and/or steps may not be separately described in this section.
  • the method 1500 includes, at step 1510, receiving a bitstream corresponding to a block of video data.
  • the method 1500 includes, at step 1520, receiving signaling indicating that the block of video data is a zero unit (ZU) block, which is untransformable, and has at least one dimension that is a non-power-of-two.
  • ZU zero unit
  • the method 1500 includes, at step 1530, decoding, based on the signaling, the bitstream to reconstruct the block of video data.
  • the signaling may exclude a merge index or a skip flag, and/or exclude a prediction mode flag, and/or include a maximum or minimum value for at least one of the dimensions of the ZU block.
  • the signaling is in a Video Parameter Set (VPS), a Sequence Parameter Set (SPS), a Picture Parameter Set (PPS), a slice header, a coding tree unit (CTU) or a coding unit (CU).
  • motion information of the ZU block is inherited from motion information of a neighboring block of size 2 N x2 M .
  • the ZU block is split into two or more units.
  • at least one of the two or more units is a zero unit.
  • at least one of the two or more units is a coding unit (CU) with dimensions
  • FIG. 16 is a block diagram illustrating an example of the architecture for a computer system or other control device 1600 that can be utilized to implement various portions of the presently disclosed technology, including (but not limited to) methods 1400 and 1500.
  • the computer system 1600 includes one or more processors 1605 and memory 1610 connected via an interconnect 1625.
  • the interconnect 1625 may represent any one or more separate physical buses, point to point connections, or both, connected by appropriate bridges, adapters, or controllers.
  • the interconnect 1625 may include, for example, a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), IIC (I2C) bus, or an Institute of Electrical and Electronics Engineers (IEEE) standard 674 bus, sometimes referred to as“Firewire.”
  • PCI Peripheral Component Interconnect
  • ISA HyperTransport or industry standard architecture
  • SCSI small computer system interface
  • USB universal serial bus
  • I2C IIC
  • IEEE Institute of Electrical and Electronics Engineers
  • the processor(s) 1605 may be, or may include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.
  • DSPs digital signal processors
  • ASICs application specific integrated circuits
  • PLDs programmable logic devices
  • the memory 1610 can be or include the main memory of the computer system.
  • the memory 1610 represents any suitable form of random access memory (RAM), read-only memory (ROM), flash memory, or the like, or a combination of such devices.
  • RAM random access memory
  • ROM read-only memory
  • flash memory or the like, or a combination of such devices.
  • the memory 1610 may contain, among other things, a set of machine instructions which, when executed by processor 1605, causes the processor 1605 to perform operations to implement embodiments of the presently disclosed technology.
  • the network adapter 1615 provides the computer system 1600 with the ability to communicate with remote devices, such as the storage clients, and/or other storage servers, and may be, for example, an Ethernet adapter or Fiber Channel adapter.
  • FIG. 17 shows a block diagram of an example embodiment of a mobile device 1700 that can be utilized to implement various portions of the presently disclosed technology, including (but not limited to) methods 1400 and 1500.
  • the mobile device 1700 can be a laptop, a smartphone, a tablet, a camcorder, or other types of devices that are capable of processing videos.
  • the mobile device 1700 includes a processor or controller 1701 to process data, and memory 1702 in communication with the processor 1701 to store and/or buffer data.
  • the processor 1701 can include a central processing unit (CPU) or a microcontroller unit (MCU).
  • the processor 1701 can include a field-programmable gate-array (FPGA).
  • FPGA field-programmable gate-array
  • the mobile device 1700 includes or is in communication with a graphics processing unit (GPU), video processing unit (VPU) and/or wireless communications unit for various visual and/or communications data processing functions of the smartphone device.
  • the memory 1702 can include and store processor-executable code, which when executed by the processor 1701, configures the mobile device 1700 to perform various operations, e.g., such as receiving information, commands, and/or data, processing information and data, and transmitting or providing processed information/data to another device, such as an actuator or external display.
  • the memory 1702 can store information and data, such as instructions, software, values, images, and other data processed or referenced by the processor 1701.
  • various types of Random Access Memory (RAM) devices, Read Only Memory (ROM) devices, Flash Memory devices, and other suitable storage media can be used to implement storage functions of the memory 1702.
  • the mobile device 1700 includes an input/output (I/O) unit 1703 to interface the processor 1701 and/or memory 1702 to other modules, units or devices.
  • the I/O unit 1703 can interface the processor 1701 and memory 1702 with to utilize various types of wireless interfaces compatible with typical data communication standards, e.g., such as between the one or more computers in the cloud and the user device.
  • the mobile device 1700 can interface with other devices using a wired connection via the I/O unit 1703.
  • the mobile device 1700 can also interface with other external interfaces, such as data storage, and/or visual or audio display devices 1704, to retrieve and transfer data and information that can be processed by the processor, stored in the memory, or exhibited on an output unit of a display device 1704 or an external device.
  • the display device 1704 can display a video frame that includes a block (a CU, PU or TU) that applies the intra-block copy based on whether the block is encoded using a motion compensation algorithm, and in accordance with the disclosed technology.
  • a video decoder apparatus may implement a method of using zero-units as described herein is used for video decoding.
  • the various features of the method may be similar to the various methods described herein.
  • the video decoding methods may be implemented using a decoding apparatus that is implemented on a hardware platform as described with respect to FIG. 16 and FIG. 17.
  • a method for video encoding (e.g., method 1800 depicted in FIG. 18), comprising: determining (1802) that a block of video data is to be coded as a zero unit (ZU) block, the block of video data having dimensions SxT; partitioning (1804) the ZU block into one of two units, three units, or four units; and generating (1806) a bitstream by coding the units.
  • ZU zero unit
  • a method of video decoding comprising: receiving (1902) a bitstream corresponding to a block of video data coded as a zero unit (ZU) block partitioned into two units, three units or four units, the block of video data having dimensions SxT; and generating (1904) the block of video data by decoding the bitstream.
  • ZU zero unit
  • K*M being a minimum height or a minimum width of allowed coding units and the units being partitioned from a non-ZU block.
  • a method for video encoding comprising: determining that a block of video data is to be coded as a zero unit (ZU) block; partitioning the block of video data using a partitioning scheme, wherein the partitioning scheme partitions the block of video data into one of two units, three units, or four units; generating a bitstream by coding the block of video data, wherein the partitioning scheme is signaled using a syntax that is identical to that used for signaling partitioning of another block of video data that is a non-zero unit block.
  • ZU zero unit
  • a method of video decoding comprising: receiving a bitstream corresponding to a block of video data that is coded as a zero unit (ZU) block, wherein the block of video data is partitioned using a partitioning scheme that partitions the block of video data into one of two units, three units, or four units, and wherein the partitioning scheme is signaled in the bitstream using a syntax that is identical to that used for signaling partitioning of a non-zero unit block; decoding, based on the signaling, the bitstream to generate the block of video data.
  • ZU zero unit
  • a method for video encoding comprising: determining that a block of video data is to be coded as a zero unit (ZU) block, the block of video data having dimensions; partitioning the ZU block into one of two units, three units, or four units using a partitioning scheme selected from a set of ZU block partitioning schemes; coding the units; and signaling the coded units in a bitstream.
  • the set of ZU block partitioning schemes is a subset of a set of partitioning schemes available for splitting a coding unit (CU).
  • a method of video decoding comprising: receiving a bitstream corresponding to a block of video data, the block of video data having dimensions; receiving signaling indicating that the block of video data includes units partitioned from a zero unit (ZU) block, the partitioned ZU block being partitioned using a partitioning scheme selected from a set of ZU block partitioning schemes; and decoding, based on the signaling, the bitstream corresponding to the units to reconstruct the block of video data.
  • the set of ZU block partitioning schemes is a subset of a set of partitioning schemes available for splitting a coding unit (CU).
  • [00182] 30 The method of solution 28 or 29, wherein the set of ZU block partitioning schemes is based on one of a size of the ZU block or a position of the ZU block in relation to one of a picture, a slice, a tile or a slice type.
  • a method for video encoding comprising: determining that a block of video data is to be coded as a zero unit (ZU) block, the block of video data having dimensions; partitioning the ZU block into one of two, three or four units upon determining that the ZU block is located in an I-slice or an intra-coded picture; coding the units; and signaling the coded units in a bitstream.
  • ZU zero unit
  • a method of video decoding comprising: receiving a bitstream corresponding to a block of video data, the block of video data having dimensions; receiving signaling indicating that the block of video data includes units partitioned from a zero unit (ZU) block, the partitioned ZU block being located in an I-slice or an intra-coded picture; and decoding, based on the signaling, the bitstream corresponding to the units to reconstruct the block of video data.
  • ZU zero unit
  • An apparatus in a video system comprising a processor and a non- transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to implement the method in any one of solutions 1 to 37.
  • Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.
  • Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus.
  • the computer readable medium can be a machine- readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them.
  • the term“data processing unit” or“data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a
  • the apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
  • a computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.
  • a computer program does not necessarily correspond to a file in a file system.
  • a program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code).
  • a computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
  • processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer.
  • a processor will receive instructions and data from a read only memory or a random access memory or both.
  • the essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data.
  • a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks.
  • mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks.
  • a computer need not have such devices.
  • Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices.
  • semiconductor memory devices e.g., EPROM, EEPROM, and flash memory devices.
  • the processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

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Abstract

Selon l'invention, des unités zéro (ZU) servent au codage ou au décodage vidéo. Un procédé de traitement vidéo donné à titre d'exemple comprend les étapes qui consistent : à déterminer qu'un bloc de données vidéo doit être codé sous la forme d'un bloc de ZU car ledit bloc de données vidéo a des dimensions S × T, S et/ou T étant des nombres qui ne sont pas à la puissance deux ; à diviser le bloc de ZU en deux, trois ou quatre unités ; et à générer un train de bits par codage des unités.
PCT/IB2019/055433 2018-06-29 2019-06-27 Division d'unités zéro Ceased WO2020003183A1 (fr)

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