WO2020015493A1 - 静电保护电路、阵列基板及显示装置 - Google Patents

静电保护电路、阵列基板及显示装置 Download PDF

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Publication number
WO2020015493A1
WO2020015493A1 PCT/CN2019/091600 CN2019091600W WO2020015493A1 WO 2020015493 A1 WO2020015493 A1 WO 2020015493A1 CN 2019091600 W CN2019091600 W CN 2019091600W WO 2020015493 A1 WO2020015493 A1 WO 2020015493A1
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Prior art keywords
transistor
electrostatic protection
line
gate
protection circuit
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English (en)
French (fr)
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龙春平
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to EP19816491.5A priority Critical patent/EP3826056B1/en
Priority to US16/609,422 priority patent/US11562997B2/en
Publication of WO2020015493A1 publication Critical patent/WO2020015493A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/206—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of combinations of capacitors and resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an electrostatic protection circuit, an array substrate, and a display device.
  • an electrostatic protection device connected to the signal lines is provided on the array substrate.
  • This electrostatic protection device is also commonly referred to as an Electro-Static Discharge (ESD) device.
  • the electrostatic protection device in the related art generally includes a transistor and an electrostatic protection line.
  • the source of the transistor can be connected to the signal line, and the gate and the drain can be connected to the electrostatic protection line.
  • the transistor can release the static electricity generated on the signal line to the electrostatic protection line in time.
  • the present disclosure provides an electrostatic protection circuit, an array substrate, and a display device.
  • the technical scheme is as follows:
  • an electrostatic protection circuit which includes: at least one first transistor, at least one second transistor, at least one resistor, and an electrostatic protection line;
  • the gate and the second pole of each of the first transistors are connected to the electrostatic protection line, and the first pole of each of the first transistors is connected to a signal line;
  • the gate and the second pole of each of the second transistors are connected to the signal line, and the first pole of each of the second transistors is connected to the electrostatic protection line;
  • one of the resistors is connected in series between a gate and a second electrode of the at least one transistor.
  • the electrostatic protection circuit includes: at least two of the resistors. Wherein, one of the resistors is connected in series between the gate of the at least one first transistor and a second electrode, and one of the resistors is connected in series between the gate of the at least one second transistor and a second electrode.
  • the electrostatic protection circuit includes: two of the first transistors, two of the second transistors, and two of the resistors.
  • One of the resistors is connected in series between a gate of the first transistor and a second electrode; another of the resistors is connected in series between a gate of the second transistor and a second electrode.
  • two of the first transistors are disposed on both sides of the signal line, and two of the second transistors are disposed on both sides of the signal line.
  • the electrostatic protection circuit includes: two of the first transistor, two of the second transistor, and four of the resistor.
  • a resistor is connected in series between the gate and the second electrode of each transistor.
  • the electrostatic protection line includes a first discharge line and a second discharge line.
  • the potentials of the signals provided by the first discharge line and the second discharge line are different, and the gate and the second electrode of each of the first transistors are connected to the first discharge line, and each of the second A first electrode of the transistor is connected to the second discharge line.
  • a potential of a signal provided by the first discharge line is higher than a potential of a signal provided by the second discharge line, and each of the transistors is a P-type transistor.
  • the potential of the signal provided by the first discharge line is lower than the potential of the signal provided by the second discharge line, and each of the transistors is an N-type transistor.
  • the electrostatic protection line is a common electrode line.
  • each transistor is a thin film transistor, and each of the resistors is disposed on the same layer as the active layer of the thin film transistor.
  • each of the resistor and the active layer is made of a polysilicon material.
  • each of the resistors is in a serpentine shape, a zigzag shape, or an arc shape.
  • the signal line is a data line; a first pole and a second pole of each transistor are disposed on the same layer as the signal line.
  • the gate of each transistor is disposed on the same layer as the electrostatic protection line; the second pole of each first transistor is connected to the electrostatic protection line through a via, and the first pole of each second transistor is passed through A via is connected to the electrostatic protection line, and each of the resistors is respectively connected to a gate and a second electrode of the transistor through the via.
  • the signal line is a gate line; the gate of each transistor is disposed on the same layer as the signal line, and the first and second electrodes of each transistor are disposed on the same layer as the electrostatic protection line.
  • the electrostatic protection line includes: a first discharge line and a second discharge line, and the potentials of signals provided by the first discharge line and the second discharge line are different;
  • the gate and the second pole of each of the first transistors are connected to the first discharge line, and the first pole of each of the second transistors is connected to the second discharge line.
  • Each transistor is a thin film transistor, and each of the resistors is disposed on the same layer as the active layer of the thin film transistor, and each of the resistors and the active layer is made of a polysilicon material, and each of the resistors One of serpentine, zigzag and arc;
  • the signal line is a data line; a first pole and a second pole of each transistor are provided on the same layer as the signal line, a gate of each transistor is provided on the same layer as the electrostatic protection line, and each of the first The second pole of the transistor is connected to the electrostatic protection line through a via, the first pole of each second transistor is connected to the electrostatic protection line through a via, and each of the resistors is respectively connected to the transistor through a via.
  • the gate is connected to the second electrode.
  • an array substrate in another aspect, includes: a signal line, and the electrostatic protection circuit according to the above aspect connected to the signal line.
  • the display device includes the array substrate according to the above aspect.
  • FIG. 1 is an equivalent circuit diagram of an electrostatic protection circuit according to an embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 3 is an equivalent circuit diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 4 is an equivalent circuit diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a top view of an electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a cross-sectional view taken along the AA direction of FIG. 5;
  • FIG. 7 is a schematic diagram of an optional shape of a resistor provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may be all thin film transistors. According to the function in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Because the source and drain of the switching transistor used here are symmetrical, the source and drain of the switching transistor are interchangeable.
  • the source electrode may be referred to as a first electrode and the drain electrode may be referred to as a second electrode; or the source electrode may be referred to as a second electrode and the drain electrode may be referred to as a first electrode.
  • the middle end of the transistor is specified as the gate, the signal input end is the source, and the signal output end is the drain.
  • FIG. 1 is an equivalent circuit diagram of an electrostatic protection circuit according to an embodiment of the present disclosure.
  • the electrostatic protection circuit may include at least one first transistor M1, at least one second transistor M2, at least one resistor R, and an electrostatic protection line L.
  • each first transistor M1 The gate and the second pole of each first transistor M1 are connected to the electrostatic protection line L, and the first pole of each first transistor M1 is connected to the signal line S.
  • each second transistor M2 The gate and the second pole of each second transistor M2 are connected to the signal line, and the first pole of each second transistor M2 is connected to the electrostatic protection line L.
  • a resistor R is connected in series between the gate and the second pole of the at least one first transistor M1 and the at least one second transistor M2.
  • the electrostatic protection circuit shown in FIG. 1 includes a first transistor M1, a second transistor M2, and two resistors R, and a resistor R is connected in series between a gate and a second electrode of each transistor.
  • the signal line S may be any signal line on the array substrate.
  • the signal line S may be any signal line used to drive a display device, such as a data line, a gate line, or a clock signal line of a gate driving circuit.
  • the signal line may also be a test line or a maintenance line in the array substrate.
  • the electrostatic protection line L may be a discharge line for providing a reference power signal.
  • the electrostatic protection line L may be a common electrode (Vcom) line, and the common electrode line is used to provide a common electrode signal with a potential of about 0 volts (V) or about 0V.
  • Vcom common electrode
  • the at least one first transistor M1 or the at least one second transistor M2 can be turned on, so that the signal line S can be communicated with the electrostatic protection line L, so that the static electricity generated on the signal line S Can be discharged to the electrostatic protection line L.
  • a resistor R is connected in series between the gate of the at least one transistor and the second electrode of the at least one first transistor M1 and the at least one second transistor M2.
  • the resistor R can effectively reduce the current flowing between the gate and the second electrode of the transistor, avoid the transistor from being burned, reduce the probability of failure of the electrostatic protection circuit, and improve the reliability of the electrostatic protection circuit. Sex.
  • the resistor R can also function as a bleeder resistor to protect the gate and drain (ie, the second electrode) of the transistor. Because the resistance between the gate and the drain of the transistor is large, a small amount of static electricity will cause a high voltage across the equivalent capacitance between the gate and the drain. If these small amounts of static electricity are not discharged in time, the high voltage across the equivalent capacitor may cause the transistor to malfunction, and may even break down the gate and drain of the transistor.
  • a resistor R is connected in series between the gate and the drain, and the resistor R can discharge the above-mentioned static electricity, thereby protecting the transistor.
  • the electrostatic protection circuit when the electrostatic protection circuit includes a first transistor M1 and a second transistor M2, the structure of the electrostatic protection circuit is relatively simple and the occupied area is small.
  • the electrostatic protection circuit includes a plurality of first transistors M1 and a plurality of second transistors M2, when a certain first transistor M1 or a certain second transistor M2 fails, other transistors can also ensure that the electrostatic protection circuit works normally. Therefore, the reliability of the electrostatic protection circuit can be effectively improved.
  • the number of the first transistors M1 and the second transistors M2 in the electrostatic protection circuit may be flexibly selected according to application requirements, which is not limited in the embodiments of the present disclosure.
  • the embodiment of the present disclosure provides an electrostatic protection circuit.
  • a resistor is connected in series between the gate of the at least one transistor and the second electrode in the electrostatic protection circuit. Therefore, when a large current is generated on the signal line, the The resistor can effectively reduce the magnitude of the current flowing between the gate and the second electrode of the transistor, avoiding the transistor to be burned out, thereby effectively reducing the probability of failure of the electrostatic protection circuit and improving the reliability of the electrostatic protection circuit.
  • the electrostatic protection circuit may include: at least two resistors R.
  • a resistor R is connected in series between the gate of the at least one first transistor M1 and the second electrode; and a resistor R is connected in series between the gate of the at least one second transistor M2 and the second electrode.
  • the electrostatic protection circuit may include two resistors R, one of which is connected in series between the gate of the first transistor M1 and the second electrode, and the other is connected in series with the second transistor M2 Between the gate and the second electrode.
  • each transistor included in the electrostatic protection circuit is a P-type transistor
  • the gate potential of the first transistor M1 is smaller than the first electrode potential.
  • the first transistor M1 is turned on, and the signal line S and the electrostatic protection line L are conducted, and the signal line S can be discharged to the electrostatic protection line L through the first transistor M1.
  • the gate potential of the second transistor M2 is smaller than the potential of the first electrode.
  • the second transistor M2 is turned on, and the signal line S and the electrostatic protection line L are conducted.
  • the signal line S can be discharged to the electrostatic protection line L through the second transistor M2.
  • FIG. 2 is an equivalent circuit diagram of another electrostatic protection circuit provided by an embodiment of the present disclosure.
  • the electrostatic protection circuit may include two first transistors M1, two second transistors M2, and two resistors R.
  • one resistor R is connected in series between a gate of a first transistor M1 and a second electrode, and the other resistor R is connected in series between a gate of a second transistor M2 and a second electrode.
  • FIG. 3 is an equivalent circuit diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure. Comparing FIG. 2 and FIG. 3, it can be seen that among the two first transistors M1, the first transistor M1 with a resistor in series and the first transistor M1 without a series resistor may be respectively disposed on both sides of the signal line S, for example, in series The first transistor M1 with a resistor may be disposed on the left side of the signal line S, and the first transistor M1 without a series resistor may be disposed on the right side of the signal line S. Similarly, the second transistor M2 with a resistor in series and the second transistor M2 without a resistor in series may be respectively disposed on both sides of the signal line S.
  • the second transistor M2 with a resistor in series may be disposed on the right side of the signal line S.
  • a second transistor M2 without a series resistance may be disposed on the left side of the signal line S.
  • the embodiment of the present disclosure does not limit the orientation of the transistor.
  • FIG. 4 is an equivalent circuit diagram of still another electrostatic protection circuit provided by an embodiment of the present disclosure.
  • the electrostatic protection circuit may include two first transistors M1, two second transistors M2, and four resistors R.
  • a resistor R may be connected in series between the gate and the second electrode of each transistor.
  • the electrostatic protection line L may include a first discharge line L1 and a second discharge line L2.
  • the first discharge line L1 and the second discharge line L2 provide The potentials of the signals are different.
  • each first transistor M1 As shown in FIG. 2 to FIG. 4, the gate and the second pole of each first transistor M1 are connected to the first discharge line L1, and the first pole of each second transistor M2 is connected to the second discharge line L2 connection.
  • each transistor may be a P-type transistor.
  • the signal provided by the first discharge line L1 may be a VGH signal
  • the signal provided by the second discharge line L2 may be a VGL signal
  • the potential of the VGH signal may be about 10V
  • the potential of the VGL signal may be -10V. about.
  • Vgs Vg-Vs (that is, the difference between the gate potential Vg and the source potential Vs).
  • the P-type transistor can be turned on when the gate potential Vg is less than the first electrode potential Vs. Therefore, when high voltage static electricity is generated on the signal line S, each first transistor M1 is turned on, and the signal line S and the first discharge line L1 are turned on. At this time, the signal line S can discharge static electricity to the first discharge line L1. When low-voltage static electricity is generated on the signal line S, each second transistor M2 is turned on, and the signal line S and the second discharge line L2 are turned on. At this time, the signal line S can discharge static electricity to the second discharge line L2.
  • each transistor is an N-type transistor.
  • the signal provided by the first discharge line L1 may be a VGL signal
  • the signal provided by the second discharge line L2 may be a VGH signal.
  • Vgs> Vth the transistor is turned on. Since the Vth of the N-type transistor is generally greater than or equal to 0, the N-type transistor can be turned on when the gate potential Vg is greater than the first electrode potential Vs. Therefore, when high voltage static electricity is generated on the signal line S, each second transistor M2 is turned on, and the signal line S and the second discharge line L2 are turned on. At this time, the signal line S can discharge static electricity to the second discharge line L2. When low-voltage static electricity is generated on the signal line S, each first transistor M1 is turned on, and the signal line S and the first discharge line L1 are turned on. At this time, the signal line S can discharge static electricity to the first discharge line L1.
  • the electrostatic protection line L may also be a common electrode line.
  • the common electrode line can provide a common electrode signal with a potential of 0V or about 0V.
  • each transistor in the electrostatic protection circuit may be a P-type transistor, or may be an N-type transistor.
  • each transistor when high voltage static electricity is generated on the signal line S, each first transistor M1 can be turned on; when low voltage static electricity is generated on the signal line S, each second transistor The transistor M2 can be turned on. If each transistor is an N-type transistor, when high voltage static electricity is generated on the signal line S, each second transistor M2 may be turned on; when low voltage static electricity is generated on the signal line S, each first transistor M1 may be turned on.
  • FIG. 5 is a top view of an electrostatic protection circuit according to an embodiment of the present disclosure
  • FIG. 6 is a cross-sectional view in the direction of AA of FIG. 5.
  • each transistor in the electrostatic protection circuit may be a thin film transistor formed on a substrate.
  • Each resistor R may be disposed in the same layer as the active layer ACT of the thin film transistor.
  • each resistor R and the active layer may be made of a polysilicon material, for example, may be made of a low-temperature polysilicon material.
  • the polysilicon material has moderate resistance, that is, it can resist the impact of large currents, and can ensure the rapid discharge of static electricity.
  • each resistor may be made of undoped polysilicon material, or may be made of doped polysilicon material.
  • the active layer of each transistor can be made of doped polysilicon material.
  • the material doped in polysilicon may be phosphorus, arsenic, antimony, sulfur, selenium, or tellurium, and the commonly used ones are generally phosphorus, arsenic, or selenium.
  • the material doped in polysilicon may be boron, aluminum, gallium, or beryllium, and boron is generally used.
  • the signal line S is a data line for transmitting a data signal in the array substrate
  • the first pole d1 and the second pole d2 of each transistor may be It is provided in the same layer as the signal line S.
  • the gate G of each transistor may be provided in the same layer as the electrostatic protection line (for example, the first discharge line L1 and the second discharge line L2 shown in the figure). It can also be seen from FIG. 5 that the first electrode d1 of the first transistor M1 and the second electrode d2 of the second transistor M2 may share the same electrode.
  • the second electrode d2 of each first transistor may be connected to the electrostatic protection line L (for example, the first discharge line L1) through a via.
  • the first electrode d1 of each second transistor may also be connected to the electrostatic protection line L (for example, the second discharge line L2) through a via.
  • Each resistor R may be connected to the gate G and the second electrode d2 of the transistor through a via, respectively.
  • the gate G of each transistor may be disposed on the same layer as the signal line S, and the first and second electrodes d1 and d2 of each transistor may be connected to the signal line S. They are arranged in different layers and can be connected to the signal line S through vias, respectively.
  • the ESD protection line L may be disposed on the same layer as the first electrode d1 and the second electrode d2 of the transistor.
  • the electrostatic protection circuit can be disposed on the base substrate 00 on which the buffer layer 01 is formed.
  • a gate insulating layer 02 is disposed on a side of the active layer ACT of the thin film transistor remote from the substrate substrate 00, and a gate G of the thin film transistor and an electrostatic protection line may be disposed on a side of the gate insulating layer 02 remote from the substrate substrate 00.
  • the gate G and the ESD line are further provided with an interlayer dielectric layer 03 on a side remote from the substrate substrate 00.
  • the first electrode d1, the second electrode d2, and the signal line S of the thin film transistor may be disposed in the interlayer dielectric.
  • the layer 03 is away from the side of the base substrate 00.
  • FIG. 7 is a schematic diagram of an optional shape of a resistor provided by an embodiment of the present disclosure.
  • each resistor R in the electrostatic protection circuit may have a shape such as a serpentine shape, a zigzag shape, or an arc shape. This can increase the resistance value of each resistor R as much as possible within the limited wiring space.
  • the shape of the resistor may refer to the shape of the orthographic projection of the resistor on the substrate.
  • the embodiment of the present disclosure provides an electrostatic protection circuit.
  • a resistor is connected in series between the gate of the at least one transistor and the second electrode in the electrostatic protection circuit. Therefore, when a large current is generated on the signal line, the The resistor can effectively reduce the magnitude of the current flowing between the gate and the second electrode of the transistor, avoiding the transistor to be burned out, thereby effectively reducing the probability of failure of the electrostatic protection circuit and improving the reliability of the electrostatic protection circuit.
  • the embodiment of the present disclosure provides a method for manufacturing an electrostatic protection circuit, and the method can be used for manufacturing the electrostatic protection circuit provided by the foregoing embodiment.
  • the method may include:
  • Step 101 Form at least one first transistor, at least one second transistor, at least one resistor, and an electrostatic protection line on a base substrate.
  • each first transistor is connected to the electrostatic protection line, and the first pole of each first transistor is connected to the signal line.
  • the gate and the second pole of each second transistor are connected to the signal line, and the first pole of each second transistor is connected to the electrostatic protection line.
  • a resistor is connected in series between the gate and the second pole of the at least one first transistor and the at least one second transistor.
  • a resistor when forming a resistor on the base substrate, at least two resistors may be formed, and a resistor may be connected in series between the gate of the at least one first transistor and the second electrode, and the gate of the at least one second transistor and A resistor is connected in series between the second poles.
  • two first transistors, two second transistors, and two resistors can be formed.
  • one of the two resistors may be connected in series between the gate of the first transistor and the second electrode, and the other resistor may be connected in series between the gate of the second transistor and the second electrode.
  • a transistor and a resistor are formed on the substrate, two first transistors, two second transistors, and four resistors can be formed.
  • a resistor may be connected in series between the gate and the second electrode of each transistor.
  • the ESD protection line formed on the base substrate may include a first discharge line and a second discharge line, and the potentials of signals provided by the first discharge line and the second discharge line are different.
  • the gate and the second electrode of each first transistor are connected to the first discharge line, and the first electrode of each second transistor is connected to the second discharge line.
  • a potential of a signal provided by the first discharge line may be a high potential relative to a potential of a signal provided by the second discharge line, and each transistor may be a P-type transistor.
  • a potential of a signal provided by the first discharge line may be a low potential relative to a potential of a signal provided by the second discharge line, and each transistor may be an N-type transistor.
  • the ESD protection line formed on the base substrate may be a common electrode line.
  • each transistor formed on the base substrate may be a thin film transistor.
  • the at least one resistor may be formed with the active layer of the thin film transistor through a patterning process. As a result, it is possible to avoid increasing the process complexity during the manufacture of the electrostatic protection circuit.
  • the gate of each transistor and the electrostatic protection line can be formed by a patterning process, and the first of each transistor can be formed by a patterning process.
  • Pole, the second pole, and the signal line can be connected to the electrostatic protection line through a via
  • the first pole of each second transistor can be connected to the electrostatic protection line through a via
  • each resistor can be connected through the via. Connected to the gate and the second electrode of the transistor, respectively.
  • the one-time patterning process may include processes such as photoresist coating, exposure, development, etching, and photoresist glass.
  • the gate, the first electrode, the second electrode, and the ESD protection line of the transistor may be formed of a metal material.
  • the metallic material may include any one of copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), molybdenum-niobium alloy (MoNb), and aluminum-neodymium alloy (AlNd).
  • a metal thin film can be deposited on the surface of the substrate first by using a magnetron sputtering process; The patterning process is performed on the metal thin film in a patterning process to obtain a corresponding component.
  • a polysilicon thin film may be formed on the surface of the base substrate first; thereafter, the polysilicon thin film may be patterned by a patterning process to obtain the resistor and the active layer.
  • the process for forming a polysilicon film may include: firstly depositing an amorphous silicon film by plasma enhanced chemical vapor deposition (PECVD) process, and then using excimer laser annealing (ELA) An amorphous silicon thin film is processed to obtain a polysilicon thin film.
  • PECVD plasma enhanced chemical vapor deposition
  • EVA excimer laser annealing
  • An amorphous silicon thin film is processed to obtain a polysilicon thin film.
  • LPCVD low-pressure vapor deposition
  • LPCVD Low Pressure Chemical Deposition
  • FIG. 8 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate may include a signal line S and an electrostatic protection circuit 00 connected to the signal line S.
  • the electrostatic protection circuit 00 may be an electrostatic protection circuit as shown in any one of FIGS. 1 to 6.
  • the array substrate may include a plurality of signal lines S, wherein each signal line S may be connected to an electrostatic protection circuit 00 as shown in any one of FIGS. 1 to 6.
  • the ESD protection circuits 00 connected to the signal lines S may all be disposed in a non-display area around the array substrate.
  • An embodiment of the present disclosure further provides a display device, which may include an array substrate as shown in FIG. 8.
  • the display device may be any liquid crystal panel, electronic paper, OLED panel, AMOLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc., which have any display function or component.

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Abstract

提供了一种静电保护电路、阵列基板及显示装置，属于显示领域。该静电保护电路包括：至少一个第一晶体管和至少一个第二晶体管。每个第一晶体管的栅极和第二极均与静电防护线连接，每个第一晶体管的第一极与信号线连接，每个第二晶体管的栅极和第二极均与信号线连接，每个第二晶体管的第一极与静电防护线连接。该静电保护电路中至少一个晶体管的栅极和第二极之间串联有一个电阻，因此当信号线上产生大电流时，该电阻可以有效降低流过晶体管栅极和第二极之间的电流的大小，避免晶体管被烧坏，从而有效提高了静电保护电路的可靠性。

Description

静电保护电路、阵列基板及显示装置
本公开要求于2018年7月20日提交的申请号为201821161486.7、发明名称为“静电保护电路、阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种静电保护电路、阵列基板及显示装置。
背景技术
在阵列基板制造过程，由于等离子体沉积、膜层刻蚀和摩擦等工艺容易产生静电，因此阵列基板上形成的信号线可能发生静电击穿和静电损伤，导致阵列基板不良。为了保证各种信号线的正常工作，阵列基板上会设置与信号线连接的静电保护器件。该静电保护器件通常也称为静电释放(Electro-Static discharge，ESD)器件。
相关技术中的静电保护器件一般包括晶体管和静电防护线，该晶体管的源极可以与信号线连接，栅极和漏极可以均与静电防护线连接。该晶体管可以将信号线上产生的静电及时释放至该静电防护线。
实用新型内容
本公开提供了一种静电保护电路、阵列基板及显示装置。技术方案如下：
一方面，提供了一种静电保护电路，所述静电保护电路包括：至少一个第一晶体管、至少一个第二晶体管、至少一个电阻和静电防护线；
每个所述第一晶体管的栅极和第二极均与所述静电防护线连接，每个所述第一晶体管的第一极与信号线连接；
每个所述第二晶体管的栅极和第二极均与所述信号线连接，每个所述第二晶体管的第一极与所述静电防护线连接；
所述至少一个第一晶体管和所述至少一个第二晶体管中，至少一个晶体管 的栅极和第二极之间串联有一个所述电阻。
可选的，所述静电保护电路包括：至少两个所述电阻。其中，至少一个所述第一晶体管的栅极和第二极之间串联一个所述电阻，至少一个所述第二晶体管的栅极和第二极之间串联一个所述电阻。
可选的，所述静电保护电路包括：两个所述第一晶体管，两个所述第二晶体管以及两个所述电阻。一个所述第一晶体管的栅极和第二极之间串联一个所述电阻；一个所述第二晶体管的栅极和第二极之间串联另一个所述电阻。
可选的，两个所述第一晶体管分别设置在所述信号线的两侧；两个所述第二晶体管分别设置在所述信号线的两侧。
可选的，所述静电保护电路包括：两个所述第一晶体管，两个所述第二晶体管，以及四个所述电阻。每个晶体管的栅极和第二极之间串联一个所述电阻。
可选的，所述静电防护线包括：第一放电线和第二放电线。所述第一放电线和所述第二放电线提供的信号的电位不同，每个所述第一晶体管的栅极和第二极均与所述第一放电线连接，每个所述第二晶体管的第一极与所述第二放电线连接。
可选的，所述第一放电线提供的信号的电位相对于所述第二放电线提供的信号的电位为高电位，每个所述晶体管均为P型晶体管。
可选的，所述第一放电线提供的信号的电位相对于所述第二放电线提供的信号的电位为低电位，每个所述晶体管均为N型晶体管。
可选的，所述静电防护线为公共电极线。
可选的，每个晶体管均为薄膜晶体管，每个所述电阻与所述薄膜晶体管的有源层同层设置。
可选的，每个所述电阻和所述有源层均由多晶硅材料制成。
可选的，每个所述电阻呈蛇形、锯齿形或者弧形。
可选的，所述信号线为数据线；每个晶体管的第一极和第二极与所述信号线同层设置。
可选的，每个晶体管的栅极与所述静电防护线同层设置；每个第一晶体管的第二极通过过孔与所述静电防护线连接，每个第二晶体管的第一极通过过孔与所述静电防护线连接，每个所述电阻通过过孔分别与晶体管的栅极和第二极连接。
可选的，所述信号线为栅线；每个晶体管的栅极与所述信号线同层设置，每个晶体管的第一极和第二极与所述静电防护线同层设置。
可选的，所述静电防护线包括：第一放电线和第二放电线，所述第一放电线和所述第二放电线提供的信号的电位不同；
每个所述第一晶体管的栅极和第二极均与所述第一放电线连接，每个所述第二晶体管的第一极与所述第二放电线连接。
每个晶体管均为薄膜晶体管，每个所述电阻与所述薄膜晶体管的有源层同层设置，且每个所述电阻和所述有源层均由多晶硅材料制成，每个所述电阻呈蛇形、锯齿形和弧形中的一种；
所述信号线为数据线；每个晶体管的第一极和第二极与所述信号线同层设置，每个晶体管的栅极与所述静电防护线同层设置，每个所述第一晶体管的第二极通过过孔与所述静电防护线连接，每个所述第二晶体管的第一极通过过孔与所述静电防护线连接，每个所述电阻通过过孔分别与晶体管的栅极和第二极连接。
另一方面，提供了一种阵列基板，所述阵列基板包括：信号线，以及与所述信号线连接的如上述方面所述的静电保护电路。
可选的，所述显示装置包括：如上述方面所述的阵列基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种静电保护电路的等效电路图；
图2是本公开实施例提供的另一种静电保护电路的等效电路图；
图3是本公开实施例提供的又一种静电保护电路的等效电路图；
图4是本公开实施例提供的再一种静电保护电路的等效电路图；
图5是本公开实施例提供的一种静电保护电路的俯视图；
图6是图5在AA方向的截面图；
图7是本公开实施例提供的一种电阻的可选形状的示意图；
图8是本公开实施例提供的一种阵列基板的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开实施例中采用的晶体管可以均为薄膜晶体管，根据在电路中的作用本公开实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，可以将其中源极称为第一极，漏极称为第二极；或者也可以将其中源极称为第二极，漏极称为第一极。按附图中的形态规定晶体管的中间端为栅极，信号输入端为源极，信号输出端为漏极。
图1是本公开实施例提供的一种静电保护电路的等效电路图。参考图1，该静电保护电路可以包括：至少一个第一晶体管M1、至少一个第二晶体管M2、至少一个电阻R以及静电防护线L。
每个第一晶体管M1的栅极和第二极均与该静电防护线L连接，每个第一晶体管M1的第一极与信号线S连接。
每个第二晶体管M2的栅极和第二极均与该信号线连接，每个第二晶体管M2的第一极与该静电防护线L连接。
该至少一个第一晶体管M1和该至少一个第二晶体管M2中，至少一个晶体管的栅极和第二极之间串联有一个电阻R。
示例的，图1所示的静电保护电路中包括一个第一晶体管M1、一个第二晶体管M2以及两个电阻R，且每个晶体管的栅极和第二极之间串联一个电阻R。
其中，该信号线S可以为阵列基板上的任一条信号线，例如可以为数据线、栅线或栅极驱动电路的时钟信号线等任一用于驱动显示装置的信号线。或者，该信号线还可以为阵列基板中的测试线或维修线等。
该静电防护线L可以为用于提供基准电源信号的放电线。例如该静电防护线L可以为公共电极(Vcom)线，该公共电极线用于提供电位为0伏特(V)或0V左右的公共电极信号。当该信号线S上产生静电时，该至少一个第一晶体管M1或者该至少一个第二晶体管M2可以开启，从而可以将该信号线S与静电 防护线L连通，使得信号线S上产生的静电能够释放至静电防护线L上。
由于在本公开实施例中，该至少一个第一晶体管M1和该至少一个第二晶体管M2中，至少一个晶体管的栅极和第二极之间串联有一个电阻R，因此当信号线S上瞬时电荷积累较多时，该电阻R可以有效降低流过晶体管的栅极和第二极之间的电流的大小，避免晶体管被烧坏，降低了静电保护电路失效的概率，提高了静电保护电路的可靠性。
在本公开实施例中，该电阻R还可以起到泄放电阻的作用，保护晶体管的栅极和漏极(即第二极)。由于晶体管的栅极和漏极间的电阻值较大，因此只要有少量的静电就会使栅极和漏极之间的等效电容两端产生很高的电压。如果不及时将这些少量的静电泄放掉，等效电容两端的高压就有可能使晶体管产生误动作，甚至有可能击穿晶体管的栅极和漏极。由于在本公开实施例中，栅极与漏极之间串联有电阻R，该电阻R能够将上述静电泄放掉，从而起到了保护晶体管的作用。
需要说明的是，当静电保护电路中包括一个第一晶体管M1和一个第二晶体管M2时，该静电保护电路的结构较为简单，占用面积较小。当静电保护电路中包括多个第一晶体管M1和多个第二晶体管M2时，当某个第一晶体管M1或者某个第二晶体管M2失效时，其他晶体管还可以保证该静电保护电路正常工作，因此可以有效提高该静电保护电路的可靠性。在本公开实施例中，可以根据应用需求，灵活选择静电保护电路中第一晶体管M1和第二晶体管M2的数量，本公开实施例对此不做限定。
综上所述，本公开实施例提供了一种静电保护电路，该静电保护电路中至少一个晶体管的栅极和第二极之间串联有一个电阻，因此当信号线上产生大电流时，该电阻可以有效降低流过晶体管栅极和第二极之间的电流的大小，避免晶体管被烧坏，从而有效降低了静电保护电路失效的概率，提高了静电保护电路的可靠性。
可选的，该静电保护电路可以包括：至少两个电阻R。
至少一个第一晶体管M1的栅极和第二极之间串联一个电阻R；且至少一个第二晶体管M2的栅极和第二极之间串联一个电阻R。
示例的，如图1所示，该静电保护电路可以包括两个电阻R，其中一个电阻R串联在第一晶体管M1的栅极和第二极之间，另一个电阻R串联在第二晶体 管M2的栅极和第二极之间。
假设该静电保护电路中包括的各晶体管均为P型晶体管，则当该信号线S上产生高压静电时，第一晶体管M1的栅极电位小于第一极电位。此时第一晶体管M1开启，将信号线S与静电防护线L导通，信号线S可以通过该第一晶体管M1向静电防护线L放电。该信号线S上产生低压静电时，第二晶体管M2的栅极电位小于第一极电位。此时第二晶体管M2开启，将信号线S与静电防护线L导通。信号线S可以通过第二晶体管M2向静电防护线L放电。
根据上述分析可知，通过在至少一个第一晶体管M1的栅极和第二极之间串联一个电阻R，并在至少一个第二晶体管M2的栅极和第二极之间串联一个电阻R，可以使得无论该信号线上产生的是高压静电还是低压静电，处于开启状态的晶体管均可以通过串联的电阻来降低流过晶体管的电流的大小，避免晶体管被烧毁，进一步提高了该静电保护电路的可靠性。
可选的，图2是本公开实施例提供的另一种静电保护电路的等效电路图。如图2所示，该静电保护电路可以包括：两个第一晶体管M1，两个第二晶体管M2以及两个电阻R。
该两个电阻R中，一个电阻R串联在一个第一晶体管M1的栅极和第二极之间，另一个电阻R串联在一个第二晶体管M2的栅极和第二极之间。
在图2所示的结构中，两个第一晶体管M1中，一个第一晶体管M1的栅极和第二极之间未串联电阻。两个第二晶体管M2中，一个第二晶体管M2的栅极和第二极之间未串联电阻。当信号线S上产生的静电的相对电压较小时，即该信号线S上产生的瞬时电流较小时，该未串联电阻的晶体管能够实现静电的快速放电，即能够快速释放信号线在小电压下积累的静电电荷。
图3是本公开实施例提供的又一种静电保护电路的等效电路图。对比图2和图3可以看出，该两个第一晶体管M1中，串联有电阻的第一晶体管M1以及未串联电阻的第一晶体管M1可以分别设置在信号线S的两侧，例如，串联有电阻的第一晶体管M1可以设置在信号线S的左侧，未串联电阻的第一晶体管M1可以设置在信号线S的右侧。同样地，串联有电阻的第二晶体管M2以及未串联电阻的第二晶体管M2也可以分别设置在信号线S的两侧，例如，串联有电阻的第二晶体管M2可以设置在信号线S的右侧，未串联电阻的第二晶体管M2可以设置在信号线S的左侧。本公开实施例对晶体管的设置方位不做限定。
可选的，图4是本公开实施例提供的再一种静电保护电路的等效电路图。如图4所示，该静电保护电路可以包括：两个第一晶体管M1，两个第二晶体管M2，以及四个电阻R。其中，每个晶体管的栅极和第二极之间可以均串联一个电阻R。
通过在静电保护电路中设置两个第一晶体管M1和两个第二晶体管M2，并在每个晶体管的栅极和第二极之间均串联一个电阻R，可以避免当某个晶体管或某个电阻失效时，导致静电保护电路无法正常工作的问题，提高了该静电保护电路的可靠性，确保了该静电保护电路的抗静电性能。
在一种可选的实现方式中，参考图2至图4，该静电防护线L可以包括：第一放电线L1和第二放电线L2，该第一放电线L1和第二放电线L2提供的信号的电位不同。
如图2至图4所示，每个第一晶体管M1的栅极和第二极均与该第一放电线L1连接，每个第二晶体管M2的第一极均与该第二放电线L2连接。
可选的，若该第一放电线L1提供的信号的电位相对于该第二放电线L2提供的信号的电位为高电位，则每个晶体管可以均为P型晶体管。
示例的，该第一放电线L1提供的信号可以为VGH信号，该第二放电线L2提供的信号可以为VGL信号，该VGH信号的电位可以为10V左右，该VGL信号的电位可以为-10V左右。晶体管的栅源电位差Vgs(也可以称为栅源电压)满足：Vgs＝Vg-Vs(即栅极电位Vg与源极电位Vs的差值)。对于P型晶体管，当Vgs＜Vth时，晶体管导通，其中Vth为晶体管的阈值电压。由于P型晶体管的Vth一般小于等于0，故P型晶体管可以在栅极电位Vg小于第一极电位Vs时导通。因此当该信号线S上产生高压静电时，每个第一晶体管M1开启，将信号线S与第一放电线L1导通。此时，信号线S可以将静电释放至第一放电线L1。当该信号线S上产生低压静电时，每个第二晶体管M2开启，将信号线S与第二放电线L2导通。此时，信号线S可以将静电释放至第二放电线L2。
可选的，若该第一放电线L1提供的信号的电位相对于该第二放电线L2提供的信号的电位为低电位，则每个晶体管均为N型晶体管。
示例的，该第一放电线L1提供的信号可以为VGL信号，该第二放电线L2提供的信号可以为VGH信号。对于N型晶体管，当Vgs>Vth时，晶体管导通。由于N型晶体管的Vth一般大于等于0，故N型晶体管可以在栅极电位Vg大于 第一极电位Vs时导通。因此当该信号线S上产生高压静电时，每个第二晶体管M2开启，将信号线S与第二放电线L2导通。此时，信号线S可以将静电释放至第二放电线L2。当该信号线S上产生低压静电时，每个第一晶体管M1开启，将信号线S与第一放电线L1导通。此时，信号线S可以将静电释放至第一放电线L1。
在另一种可选的实现方式中，参考图1，该静电防护线L也可以为一条公共电极线。该公共电极线可以提供电位为0V或0V左右的的公共电极信号。此时，该静电保护电路中的各个晶体管可以均为P型晶体管，或者也可以均为N型晶体管。
如前文所述，若各个晶体管均为P型晶体管，则当该信号线S上产生高压静电时，每个第一晶体管M1可以开启；当该信号线S上产生低压静电时，每个第二晶体管M2可以开启。若各个晶体管均为N型晶体管，则当该信号线S上产生高压静电时，每个第二晶体管M2可以开启；当该信号线S上产生低压静电时，每个第一晶体管M1可以开启。
图5是本公开实施例提供的一种静电保护电路的俯视图，图6是图5在AA方向的截面图。参考图5和图6，该静电保护电路中的每个晶体管可以均为形成在衬底基板上的薄膜晶体管。每个电阻R可以与该薄膜晶体管的有源层ACT同层设置。
可选的，每个电阻R与该有源层均可以由多晶硅材料制成，例如可以由低温多晶硅材料制成。该多晶硅材料的电阻适中，即可以抵抗大电流的冲击，又可以保证静电的快速释放。
示例的，每个电阻可以由无掺杂的多晶硅材料制成，或者也可以由掺杂的多晶硅材料制成。每个晶体管的有源层可以采用掺杂的多晶硅材料制成。当该静电保护电路中采用的晶体管为N型晶体管时，多晶硅中掺杂的材料可以是磷、砷、锑、硫、硒或碲等，常用的一般为磷、砷或硒。当该静电保护电路中采用的晶体管为P型晶体管时，多晶硅中掺杂的材料可以是硼、铝、镓或铍等，常用的一般为硼。
在本公开实施例中，若信号线S为阵列基板中用于传输数据(Data)信号的数据线，则结合图5和图6可知，每个晶体管的第一极d1和第二极d2可以与该信号线S同层设置。并且，每个晶体管的栅极G可以与该静电防护线(例 如图中所示的第一放电线L1和第二放电线L2)同层设置。从图5还可以看出，第一晶体管M1的第一极d1与第二晶体管M2的第二极d2可以共用同一电极。
参考图5，每个第一晶体管的第二极d2可以通过过孔与静电防护线L(例如第一放电线L1)连接。每个第二晶体管的第一极d1也可以通过过孔与该静电防护线L(例如第二放电线L2)连接。每个电阻R可以通过过孔分别与晶体管的栅极G和第二极d2连接。
可选的，若该信号线S为栅线，则每个晶体管的栅极G可以与该信号线S同层设置，每个晶体管的第一极d1和第二极d2可以与该信号线S异层设置，且可以分别通过过孔与该信号线S连接。
需要说明的是，若信号线S为栅线，则静电防护线L可以与晶体管的第一极d1和第二极d2同层设置。
参考图6还可以看出，该静电保护电路可以设置在形成有缓冲层01的衬底基板00上。薄膜晶体管的有源层ACT远离衬底基板00的一侧设置有栅绝缘层02，薄膜晶体管的栅极G以及静电防护线可以设置在该栅绝缘层02远离衬底基板00的一侧。该栅极G以及静电防护线远离衬底基板00的一侧还设置有层间介电层03，薄膜晶体管的第一极d1、第二极d2以及信号线S可以设置在该层间介电层03远离衬底基板00的一侧。
图7是本公开实施例提供的一种电阻的可选形状的示意图，参考图7，该静电保护电路中的每个电阻R可以为蛇形、锯齿形或者弧形等形状。由此可以在有限的布线空间内，尽量增大每个电阻R的阻值。其中，电阻的形状可以是指电阻在衬底基板上的正投影的形状。
综上所述，本公开实施例提供了一种静电保护电路，该静电保护电路中至少一个晶体管的栅极和第二极之间串联有一个电阻，因此当信号线上产生大电流时，该电阻可以有效降低流过晶体管栅极和第二极之间的电流的大小，避免晶体管被烧坏，从而有效降低了静电保护电路失效的概率，提高了静电保护电路的可靠性。
本公开实施例提供了一种静电保护电路的制造方法，该方法可以用于制造上述实施例提供的静电保护电路。该方法可以包括：
步骤101、在衬底基板上形成至少一个第一晶体管、至少一个第二晶体管、 至少一个电阻和静电防护线。
其中，每个第一晶体管的栅极和第二极均与该静电防护线连接，每个第一晶体管的第一极与信号线连接。每个第二晶体管的栅极和第二极均与该信号线连接，每个第二晶体管的第一极与该静电防护线连接。并且，该至少一个第一晶体管和该至少一个第二晶体管中，至少一个晶体管的栅极和第二极之间串联有一个电阻。
可选的，在衬底基板上形成电阻时，可以形成至少两个电阻，并可以使得至少一个第一晶体管的栅极和第二极之间串联一个电阻，至少一个第二晶体管的栅极和第二极之间串联一个电阻。
可选的，在衬底基板上形成晶体管和电阻时，可以形成两个第一晶体管，两个第二晶体管以及两个电阻。并且，该两个电阻中，一个电阻可以串联在一个第一晶体管的栅极和第二极之间，另一个电阻则可以串联在一个第二晶体管的栅极和第二极之间。
可选的，在衬底基板上形成晶体管和电阻时，可以形成两个第一晶体管，两个第二晶体管，以及四个电阻。并且，每个晶体管的栅极和第二极之间可以均串联一个电阻。
作为一种可选的实现方式，该衬底基板上形成的静电防护线可以包括：第一放电线和第二放电线，该第一放电线和该第二放电线提供的信号的电位不同。其中，每个第一晶体管的栅极和第二极均与该第一放电线连接，每个第二晶体管的第一极与该第二放电线连接。
可选的，该第一放电线提供的信号的电位相对于该第二放电线提供的信号的电位可以为高电位，每个晶体管可以均为P型晶体管。或者，该第一放电线提供的信号的电位相对于该第二放电线提供的信号的电位可以为低电位，每个晶体管可以均为N型晶体管。
作为另一种可选的实现方式，该衬底基板上形成的静电防护线可以为公共电极线。
在本公开实施例中，该衬底基板上形成的每个晶体管可以均为薄膜晶体管。在衬底基板上形成该至少一个电阻时，该至少一个电阻以可以与薄膜晶体管的有源层通过一次构图工艺形成。由此可以避免增加静电保护电路制造时的工艺复杂度。
可选的，若该信号线为数据线，则在上述步骤101中，可以通过一次构图工艺形成每个晶体管的栅极和该静电防护线，并可以通过一次构图工艺形成每个晶体管的第一极、第二极以及该信号线。相应的，每个第一晶体管的第二极可以通过过孔与该静电防护线连接，每个第二晶体管的第一极可以通过过孔与该静电防护线连接，每个电阻可以通过过孔分别与晶体管的栅极和第二极连接。
其中，该一次构图工艺可以包括光刻胶涂覆、曝光、显影、刻蚀和光刻胶玻璃等工艺。
在本公开实施例中，晶体管的栅极、第一极、第二极以及静电防护线均可以由金属材料形成。该金属材料可以包括铜(Cu)、铝(Al)、钛(Ti)、钼(Mo)、钼铌合金(MoNb)和铝钕合金(AlNd)中的任一种。并且，在形成晶体管的栅极、第一极、第二极以及静电防护线中的任一元件时，可以先采用磁控溅射工艺在衬底基板的表面沉积一层金属薄膜；之后可以采用一次构图工艺对该金属薄膜进行图形化处理，从而得到对应的元件。
此外，在形成电阻以及晶体管的有源层时，可以先在衬底基板的表面形成一层多晶硅薄膜；之后可以采用一次构图工艺对该多晶硅薄膜进行图形化处理，从而得到电阻以及有源层。
其中，形成多晶硅薄膜的工艺可以包括：先采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺沉积一层非晶硅薄膜，然后采用准分子激光晶化(Excimer Laser Annealing，ELA)法对非晶硅薄膜进行处理得到多晶硅薄膜。或者，也可以采用低压气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)工艺在900度以上的高温环境直接形成多晶硅薄膜。
图8是本公开实施例提供的一种阵列基板的结构示意图，参考图8，该阵列基板可以包括：信号线S，以及与该信号线S连接的静电保护电路00。该静电保护电路00可以为如图1至图6任一所示的静电保护电路。
可选的，参考图8可以看出，该阵列基板可以包括多条信号线S，其中每条信号线S可以均连接有一个如图1至图6任一所示的静电保护电路00。
在本公开实施例中，各信号线S所连接的静电保护电路00可以均设置在阵列基板周边的非显示区域。
本公开实施例还提供一种显示装置，该显示装置可以包括如图8所示的阵列基板。该显示装置可以为：液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (18)

  1. 一种静电保护电路，所述静电保护电路包括：至少一个第一晶体管、至少一个第二晶体管、至少一个电阻和静电防护线；
    每个所述第一晶体管的栅极和第二极均与所述静电防护线连接，每个所述第一晶体管的第一极与信号线连接；
    每个所述第二晶体管的栅极和第二极均与所述信号线连接，每个所述第二晶体管的第一极与所述静电防护线连接；
    所述至少一个第一晶体管和所述至少一个第二晶体管中，至少一个晶体管的栅极和第二极之间串联有一个所述电阻。
  2. 根据权利要求1所述的静电保护电路，所述静电保护电路包括：至少两个所述电阻；
    至少一个所述第一晶体管的栅极和第二极之间串联一个所述电阻；
    至少一个所述第二晶体管的栅极和第二极之间串联一个所述电阻。
  3. 根据权利要求2所述的静电保护电路，所述静电保护电路包括：两个所述第一晶体管，两个所述第二晶体管以及两个所述电阻；
    一个所述第一晶体管的栅极和第二极之间串联一个所述电阻；
    一个所述第二晶体管的栅极和第二极之间串联另一个所述电阻。
  4. 根据权利要求3所述的静电保护电路，两个所述第一晶体管分别设置在所述信号线的两侧；
    两个所述第二晶体管分别设置在所述信号线的两侧。
  5. 根据权利要求2所述的静电保护电路，所述静电保护电路包括：两个所述第一晶体管，两个所述第二晶体管，以及四个所述电阻；
    每个晶体管的栅极和第二极之间均串联一个所述电阻。
  6. 根据权利要求1至5任一所述的静电保护电路，所述静电防护线包括： 第一放电线和第二放电线，所述第一放电线和所述第二放电线提供的信号的电位不同；
    每个所述第一晶体管的栅极和第二极均与所述第一放电线连接，每个所述第二晶体管的第一极与所述第二放电线连接。
  7. 根据权利要求6所述的静电保护电路，
    所述第一放电线提供的信号的电位相对于所述第二放电线提供的信号的电位为高电位，每个所述晶体管均为P型晶体管。
  8. 根据权利要求6所述的静电保护电路，
    所述第一放电线提供的信号的电位相对于所述第二放电线提供的信号的电位为低电位，每个所述晶体管均为N型晶体管。
  9. 根据权利要求1至5任一所述的静电保护电路，所述静电防护线为公共电极线。
  10. 根据权利要求1至9任一所述的静电保护电路，每个晶体管均为薄膜晶体管；
    每个所述电阻与所述薄膜晶体管的有源层同层设置。
  11. 根据权利要求10所述的静电保护电路，
    每个所述电阻和所述有源层均由多晶硅材料制成。
  12. 根据权利要求10或11所述的静电保护电路，
    每个所述电阻呈蛇形、锯齿形和弧形中的一种。
  13. 根据权利要求1至12任一所述的静电保护电路，所述信号线为数据线；
    每个晶体管的第一极和第二极与所述信号线同层设置。
  14. 根据权利要求13所述的静电保护电路，每个晶体管的栅极与所述静电 防护线同层设置；
    每个所述第一晶体管的第二极通过过孔与所述静电防护线连接，每个所述第二晶体管的第一极通过过孔与所述静电防护线连接。
  15. 根据权利要求1至12任一所述的静电保护电路，所述信号线为栅线；
    每个晶体管的栅极与所述信号线同层设置，每个晶体管的第一极和第二极与所述静电防护线同层设置。
  16. 根据权利要求4所述的静电保护电路，所述静电防护线包括：第一放电线和第二放电线，所述第一放电线和所述第二放电线提供的信号的电位不同；
    每个所述第一晶体管的栅极和第二极均与所述第一放电线连接，每个所述第二晶体管的第一极与所述第二放电线连接。
    每个晶体管均为薄膜晶体管，每个所述电阻与所述薄膜晶体管的有源层同层设置，且每个所述电阻和所述有源层均由多晶硅材料制成，每个所述电阻呈蛇形、锯齿形和弧形中的一种；
    所述信号线为数据线；每个晶体管的第一极和第二极与所述信号线同层设置，每个晶体管的栅极与所述静电防护线同层设置，每个所述第一晶体管的第二极通过过孔与所述静电防护线连接，每个所述第二晶体管的第一极通过过孔与所述静电防护线连接，每个所述电阻通过过孔分别与晶体管的栅极和第二极连接。
  17. 一种阵列基板，所述阵列基板包括：
    信号线，以及与所述信号线连接的如权利要求1至16任一所述的静电保护电路。
  18. 一种显示装置，所述显示装置包括：如权利要求17所述的阵列基板。
PCT/CN2019/091600 2018-07-20 2019-06-17 静电保护电路、阵列基板及显示装置 Ceased WO2020015493A1 (zh)

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US20200144247A1 (en) 2020-05-07
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