WO2020034525A1 - Procédé de test pour circuit d'attaque de substrat matriciel, et panneau d'affichage - Google Patents

Procédé de test pour circuit d'attaque de substrat matriciel, et panneau d'affichage Download PDF

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Publication number
WO2020034525A1
WO2020034525A1 PCT/CN2018/122615 CN2018122615W WO2020034525A1 WO 2020034525 A1 WO2020034525 A1 WO 2020034525A1 CN 2018122615 W CN2018122615 W CN 2018122615W WO 2020034525 A1 WO2020034525 A1 WO 2020034525A1
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WO
WIPO (PCT)
Prior art keywords
test
signal line
drive signal
terminal
driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/122615
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English (en)
Chinese (zh)
Inventor
宋乔乔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2020034525A1 publication Critical patent/WO2020034525A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the present application relates to the field of display technology, and in particular, to a test method for an array substrate driving circuit and a display panel.
  • GOA Gate-driver On Array
  • the inventor of the present application has found in long-term research and development that the implementation of the scanning signal output of the existing GOA products requires multiple sets of signals and circuits to be completed together; because the output of the scanning signals requires multiple sets of GOA signals, the detection process in the array substrate process needs Add multiple test terminals to provide input signals to the display panel for testing; however, as the requirements for products become higher and higher, GOA signals are gradually increasing, which makes the array substrate test need to design multiple sets of test terminals. Pins increase, which greatly increases the cost of the array substrate test fixture.
  • the test of the array substrate requires designing multiple sets of test terminals, and the pins of the machine test fixture increase, which greatly increases the cost of the array substrate test fixture.
  • the main problem solved by this application is to provide a test method and display panel for an array substrate drive circuit, which can complete the test of the drive circuit by using fewer test terminals than the number of drive signal lines, saving test terminals and production costs.
  • the technical solution adopted in the present application is to provide a test method for an array substrate driving circuit.
  • the method includes: connecting one driving signal to one of a plurality of test signal lines drawn from the test terminals of the array substrate. Input signal to the test terminal for testing; disconnect the recently tested test signal cable from the drive signal cable; connect another test signal cable to another drive signal cable and input a signal to the test terminal for testing; return The step of disconnecting the recently tested test signal line from the drive signal line until the test is completed; at least one of the connection structures between the test signal line and the drive signal line is a welded structure, and / or at least There is a blown or cut structure between the test signal line and the driving signal line.
  • another technical solution adopted in the present application is to provide a test method for an array substrate driving circuit, the method comprising: connecting one of a plurality of test signal lines drawn from the test terminals of the array substrate to one Drive the signal line to input signals to the test terminal for testing; disconnect the recently tested test signal line from the drive signal line; connect another test signal line to another drive signal line and input signals to the test terminal for testing ; Return to the step of disconnecting the recently tested test signal line from the drive signal line until the test is completed.
  • a display panel which includes: a substrate, a pixel circuit, a plurality of driving signal lines, and a plurality of test signal lines; the pixel circuit is located in a display area on a side of the substrate; The driving signal line is located on the substrate on the same side as the pixel circuit and extends from the non-display area to the display area on the periphery of the substrate. The driving signal line is connected to the pixel circuit; the test signal line is located on the substrate on the same side as the pixel circuit.
  • the signal line is designed to be connected to a driving signal line to test the pixel circuit;
  • the connection structure between at least one test signal line and the driving signal line is a soldering structure, and / or at least one test signal line and the driving signal There are blown or cut structures between the lines.
  • the beneficial effect of the present application is that the test terminals of the array substrate in the present application are connected to a plurality of test signal lines.
  • one of the plurality of test signal lines connected to the test terminal is connected to a driving signal line, and an external
  • the test probe inputs signals to the test terminals for testing; and then repeats: disconnect the test signal line that has been recently tested from the drive signal line, and connect another test signal line to another drive signal line.
  • the test terminal inputs signals for the test operation until the test is completed; the test of the drive circuit is completed by using fewer test terminals than the number of drive signal lines, saving test terminals and production costs.
  • FIG. 1 is a schematic diagram of a connection between a signal line and a test terminal in the prior art.
  • FIG. 2 is a schematic flowchart of a first embodiment of a test method for an array substrate driving circuit provided by the present application.
  • FIG. 3 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to step 21 in FIG. 2.
  • FIG. 4 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to steps 22 and 23 in FIG. 2.
  • FIG. 5 is a schematic flowchart of a second embodiment of a test method for an array substrate driving circuit provided by the present application.
  • FIG. 6 is a schematic diagram of a connection between a driving signal line and a test terminal when a high vertical alignment curing process is performed in a second embodiment of a test method for an array substrate driving circuit provided in the present application.
  • FIG. 7 is a schematic diagram of a connection between a driving signal line and a test terminal after a high vertical alignment curing process is completed in a second embodiment of a test method for an array substrate driving circuit provided in the present application.
  • FIG. 8 is a schematic flowchart of a third embodiment of a test method for an array substrate driving circuit provided by the present application.
  • FIG. 9 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to step 81 in FIG. 8.
  • FIG. 10 is a timing chart of driving signals in a third embodiment of a test method of an array substrate driving circuit provided by the present application.
  • FIG. 11 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to steps 82 and 83 in FIG. 8.
  • FIG. 12 is a schematic flowchart of a fourth embodiment of a test method for an array substrate driving circuit provided by the present application.
  • FIG. 13 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to step 121 in FIG. 12.
  • FIG. 14 is a schematic diagram of a connection between a driving signal line and a test terminal corresponding to steps 122 and 123 in FIG. 12.
  • FIG. 15 is a schematic structural diagram of an embodiment of a display panel provided in the present application.
  • FIG. 16 is another schematic structural diagram of a display panel in an embodiment of a display panel provided by the present application.
  • the signals of the existing product array substrate test mainly include data signals (Blue, Green, and Red), GOA signals, and common signals (ACOM and CFCOM); GOA signals mainly include multiple sets of high-frequency clock signals; VSS It is a low-potential DC signal.
  • LC1 and LC2 are a set of low-frequency AC signals. They are input source signals and realize the output of scanning signals under the action of the GOA circuit. In order to improve the charging capacity of the gate, increase the continuous transmission of the gate.
  • the clock signal gradually increases, from 2CK to 4CK (Clock, clock), 6CK, 8CK, or 12CK, etc., resulting in the number of array substrate test terminals gradually increased; take 6CK as an example, at least 16 test terminals, this requires The number of test fixtures for array substrates has increased, which has greatly increased costs.
  • FIG. 2 is a schematic flowchart of a first embodiment of a test method for an array substrate driving circuit provided by the present application. The method includes:
  • Step 21 One of the plurality of test signal lines 32 drawn from the test terminals 31 of the array substrate is connected to a drive signal line 33, and a signal is input to the test terminals 31 for testing.
  • the driving signal line 33 may be a clock signal line, and the driving circuit may be a GOA circuit 34. As shown in FIG. 3, there are four clock signal lines (CK1, CK2, CK3, and CK4). In order to save the test terminal 31, multiple test signals are provided.
  • the line 32 is connected to the same test terminal 31. When a test is performed, one of the test signal lines 32 is connected to the drive signal line 33 (CK1).
  • the driving signal line 33 is connected to the GOA circuit 34, and the external jig probe 35 is connected to the test terminal 31 to input a desired signal to the GOA circuit 34, so that the output scanning signal in the GOA circuit 34 is used to light up the display panel and pass the analysis A defective position is detected on the screen of the display panel.
  • Step 22 Disconnect the test signal line 32 and the drive signal line 33 that have been recently tested.
  • test signal lines 32 are connected to the same test terminal 31, when testing whether the GOA circuit 34 connected to another drive signal line 33 is working normally, it is necessary to firstly test the test signal line 32 and the drive signal line 33 that have been recently tested. Disconnected to avoid duplicate testing.
  • Step 23 Connect another test signal line 32 to another drive signal line 33, and input a signal to the test terminal 31 for testing.
  • test signal line 32 After the connection between the recently tested test signal line 32 and the drive signal line 33 is disconnected, as shown in FIG. 4, another test signal line 32 is connected to another drive signal line 33 (CK2), and then an external The jig probe 35 inputs a signal to the test terminal 31 for testing.
  • CK2 drive signal line 33
  • Step 24 Return to the step of disconnecting the recently-tested test signal line 32 from the drive signal line 33 until the test is completed.
  • step 22 and step 23 are repeatedly performed until the test is completed.
  • this embodiment provides a test method for an array substrate driving circuit.
  • the test terminal 31 of the array substrate is connected to a plurality of test signal lines 32.
  • the plurality of test signal lines 32 connected to the test terminal 31 are connected.
  • One of them is connected to a driving signal line 33, and an external test probe 35 is used to input a signal to the test terminal 31 for testing; then it is repeatedly executed: the connection between the recently tested test signal line 32 and the driving signal line 33 is disconnected And connect another test signal line 32 to another drive signal line 33, and input a signal to the test terminal 31 to perform a test operation until the test is completed; the drive circuit is completed by using fewer test terminals 31 than the number of the drive signal lines 33 Test, saving test terminal 31 and production cost.
  • FIG. 5 is a schematic flowchart of a second embodiment of a test method for an array substrate driving circuit provided by the present application. The method includes:
  • Step 51 One of the plurality of test signal lines 62 drawn from the test terminal 61 of the array substrate is connected to a driving signal line 63, and a signal is input to the test terminal 61 for testing.
  • Step 52 Disconnect the test signal line 62 and the drive signal line 63 that have been recently tested.
  • Step 53 Connect another test signal line 62 to another drive signal line 63, and input a signal to the test terminal 61 for testing.
  • Step 54 Return to the step of disconnecting the recently-tested test signal line 62 from the drive signal line 63 until the test is completed.
  • Steps 51-54 are similar to steps 11-14 in the first embodiment, and details are not described herein again.
  • the number of test terminals 61 is at least two, and the number of test signal lines 62 is equal to the number of drive signal lines 63.
  • Circuit breakpoints are set on the test signal lines 62, and solder point 64 is preset on the circuit breakpoints, as shown in Figure 6.
  • the test signal line 62 and the driving signal line 63 are connected by the welding point 64 on the breaking point of the welding circuit; the welding point 64 on the breaking point of the laser welding circuit can be used to make the driving signal line 63 and the testing signal line 62 are connected to form a path.
  • Step 55 After the test is completed, one of the plurality of test signal lines 62 drawn from the test terminals 61 of the array substrate is connected to all the drive signal lines 63 to perform a high vertical alignment curing process.
  • one of the plurality of test signal lines 62 drawn from the test terminals 61 of the array substrate is connected to all the drive signal lines 63 to perform high vertical alignment curing (High Vertical Alignment Curing (HVA) process; as shown in FIG. 6, the fourth test signal line 62 is connected to all driving signal lines 63, and the remaining test signal lines 62 are disconnected from the driving signal line 63.
  • HVA High Vertical Alignment Curing
  • Step 56 After the high vertical alignment curing process is completed, the test signal line 62 and the driving signal line 63 are disconnected.
  • the connection between the test signal line 62 and the driving signal line 63 is disconnected, so that the driving signal line can work normally after the display panel is sold.
  • this embodiment provides a method for testing an array substrate driving circuit.
  • a plurality of test signal lines 62 are provided on the test terminal 61 of the array substrate, and a soldering point 64 is provided on the test signal line 62.
  • the test signal line 62 is connected to the driving signal line 63 by welding different welding point positions 64, which improves the utilization rate of the test terminal 61 and saves the test terminal. 61 and production costs.
  • FIG. 8 is a schematic flowchart of a third embodiment of a method for testing an array substrate driving circuit provided by the present application.
  • the method includes:
  • Step 81 Connect the first test signal line from the first test terminal 91 to the first drive signal line, and connect the fourth test signal line from the second test terminal 92 to the fourth drive signal line.
  • the test terminal 91 and the second test terminal 92 input signals for testing.
  • the signal S1 input to the first test terminal 91 and the signal S2 input to the second test terminal 92 have opposite potentials, as shown in FIG. 10.
  • the first test signal line drawn from the first test terminal 91 is connected to the first driving signal line.
  • the fourth test signal line from the two test terminals 92 is connected to the fourth drive signal line.
  • the external fixture probe 93 is used to input signals to the first test terminal 91 and the second test terminal 92 for testing, as shown in FIG. 9. Show.
  • Step 82 Disconnect the first test signal line and the first drive signal line after the test, and disconnect the fourth test signal line and the fourth drive signal line after the test.
  • Step 83 Connect the second test signal line from the first test terminal 91 to the second drive signal line, and connect the fifth test signal line from the second test terminal 92 to the fifth drive signal line.
  • the test terminal 91 and the second test terminal 92 input signals for testing.
  • Step 84 Disconnect the second test signal line and the second drive signal line after the test, and disconnect the fifth test signal line and the fifth drive signal line after the test.
  • Step 85 Repeat the above steps until all the driving signal lines are tested.
  • this embodiment provides a test method for an array substrate driving circuit.
  • the test connected to each test terminal is first performed during the test.
  • One of the signal lines is connected to a driving signal line, and after the test is completed, the connection between the test signal line and the driving signal line is cut off, the test terminals are reused, the utilization rate of the test terminals is improved, and fewer tests are used.
  • the terminal completed the test of the GOA circuit, saving test terminals and production costs.
  • FIG. 12 is a schematic flowchart of a fourth embodiment of a method for testing an array substrate driving circuit provided by the present application. The method includes:
  • Step 121 Connect the first test signal line from the test terminal 131 to the first drive signal line, and connect the first test signal line from the test terminal 131 to the fourth drive signal line through the inverter 132 to the test terminal 131 input signals for testing.
  • the first test signal line drawn from the test terminal 131 is connected to the first drive signal line, and the first test signal line is connected to the fourth drive signal line through the inverter 132, and then the test terminal is connected to the test terminal using an external jig probe 133 131 input signals for testing, as shown in Figure 13.
  • Step 122 Disconnect the tested first test signal line from the first drive signal line, and disconnect the tested first test signal line from the fourth drive signal line.
  • Step 123 Connect the second test signal line from the test terminal 131 to the second drive signal line, and connect the second test signal line from the test terminal 131 to the fifth drive signal line through the inverter 132 to the test terminal. 131 input signals for testing.
  • Step 124 Disconnect the tested second test signal line from the second driving signal line, and disconnect the tested second test signal line from the fifth driving signal line.
  • Step 125 Repeat the above steps until all the driving signal lines are tested.
  • step 121 -124 After completing the GOA circuit test on the second driving signal line and the fifth driving signal line, disconnect the second test signal line from the second driving signal line and the fifth driving signal line respectively; then repeat step 121 -124 until all drive signal lines are tested.
  • this embodiment provides a method for testing an array substrate driving circuit.
  • testing a driving circuit first connect one of the test signal lines connected to the test terminal 131 to a driving signal line.
  • another drive signal line is connected through the inverter, and after the test is completed, the connection between the test signal line and the drive signal line is cut, and the test terminal 131 is reused, which improves the utilization of the test terminal 131 and saves the test. Terminals 131 and production costs.
  • FIG. 15 is a schematic structural diagram of an embodiment of a display panel provided in the present application.
  • the display panel includes a substrate 151, a pixel circuit 152, a plurality of driving signal lines 153, and a plurality of test signal lines 154.
  • the substrate 151 is an array substrate, and the pixel circuit 152 is located on the display area 1511 on the side of the substrate 151; the driving signal line 153 is located on the substrate 151 on the same side as the pixel circuit 151, and extends from the non-display area 1512 to the display area 1511 on the periphery of the substrate 151 The driving signal line 153 is connected to the pixel circuit 152.
  • test signal line 154 is located on the substrate 151 on the same side as the pixel circuit 152, and each test signal line 154 is designed to be connected to a driving signal line 153 to test the pixel circuit 152.
  • connection structure between at least one test signal line 154 and the drive signal line 153 is a welding structure, and / or at least one test signal line 154 and the drive signal line 153 have a blown or cut structure.
  • the display panel also includes two test terminals 155, each test terminal 155 is connected to a plurality of test signal lines 154, each test signal line 154 is connected to a drive signal line 153, and each test terminal 155 is connected to an external fixture (figure (Not shown) is connected to input a signal into the test signal line 154 as shown in FIG. 15.
  • the display panel may also include only one test terminal 155.
  • the test terminal 155 is connected to a plurality of test signal lines 154, and each test signal line 154 is connected to two drive signal lines 153.
  • the test terminal 155 is connected to an external fixture to input signals. Into the test signal line 154, as shown in FIG.
  • At least one test signal line 154 and all the drive signal lines 153 have a blown or cut structure to prevent the test signal lines 154 from connecting all the drive signal lines 153 and short-circuit the drive signal lines 153.
  • the display panel provided in this embodiment can test the pixel circuit 152 by using fewer test 155 terminals, reducing the space occupied by the test terminal 155 on the display panel, and reducing the size of the non-display area 1512.
  • the area is conducive to improving the screen-to-screen ratio of the display panel and can also save the cost of manufacturing the test terminal 155.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention porte sur un procédé de test d'un circuit d'attaque de substrat matriciel et sur un panneau d'affichage. Le procédé consiste : à connecter une ligne d'une pluralité de lignes de signal de test tirées de bornes de test d'un substrat matriciel à une ligne de signal d'attaque, et entrer des signaux dans les bornes de test pour effectuer un test ; à déconnecter la ligne de signal de test récemment testée de la ligne de signal d'attaque ; à connecter une autre ligne de signal de test à une autre ligne de signal de commande, et entrer des signaux dans les bornes de test pour effectuer un test ; et à retourner à l'étape de déconnexion de la ligne de signal de test récemment testé à partir de la ligne de signal d'attaque jusqu'à ce que le test soit terminé. Au moyen du procédé, le test d'un circuit d'attaque peut être réalisé à l'aide de bornes de test moins nombreuses que les lignes de signal d'attaque, de telle sorte que les bornes de test et les coûts de production sont économisés.
PCT/CN2018/122615 2018-08-16 2018-12-21 Procédé de test pour circuit d'attaque de substrat matriciel, et panneau d'affichage Ceased WO2020034525A1 (fr)

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Application Number Priority Date Filing Date Title
CN201810933627.0 2018-08-16
CN201810933627.0A CN108877616B (zh) 2018-08-16 2018-08-16 一种阵列基板驱动电路的测试方法及显示面板

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CN108877616B (zh) * 2018-08-16 2019-09-20 深圳市华星光电半导体显示技术有限公司 一种阵列基板驱动电路的测试方法及显示面板
CN109637405B (zh) 2018-12-05 2021-04-06 惠科股份有限公司 阵列基板的测试方法、装置及存储介质
CN114974049A (zh) * 2021-02-26 2022-08-30 京东方科技集团股份有限公司 检测电路、阵列基板及显示装置

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CN108877616A (zh) * 2018-08-16 2018-11-23 深圳市华星光电半导体显示技术有限公司 一种阵列基板驱动电路的测试方法及显示面板

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US20150160276A1 (en) * 2013-12-11 2015-06-11 Samsung Display Co., Ltd. System for inspecting display panel
CN103995407A (zh) * 2014-05-08 2014-08-20 京东方科技集团股份有限公司 阵列基板和显示面板
CN104282248A (zh) * 2014-09-28 2015-01-14 京东方科技集团股份有限公司 阵列基板及其测试方法、显示面板、显示装置
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