WO2020113402A1 - Circuit de démarrage progressif combiné, puce de démarrage progressif combinée et dispositif électronique - Google Patents

Circuit de démarrage progressif combiné, puce de démarrage progressif combinée et dispositif électronique Download PDF

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Publication number
WO2020113402A1
WO2020113402A1 PCT/CN2018/119067 CN2018119067W WO2020113402A1 WO 2020113402 A1 WO2020113402 A1 WO 2020113402A1 CN 2018119067 W CN2018119067 W CN 2018119067W WO 2020113402 A1 WO2020113402 A1 WO 2020113402A1
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Prior art keywords
mos tube
output voltage
gate
terminal
input
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Ceased
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PCT/CN2018/119067
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English (en)
Chinese (zh)
Inventor
王丁丁
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to PCT/CN2018/119067 priority Critical patent/WO2020113402A1/fr
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Definitions

  • the present application relates to the field of circuits, in particular to a combined slow-start circuit, combined slow-start chip and electronic equipment.
  • the combined slow start circuit is a very common circuit in electronic equipment that needs to be hot swapped.
  • the combined slow start circuit includes multiple functions. The first is to combine the input multiple power supplies into one output; the second is to perform hot plug When pulling out, slowly control the starting process of the output power voltage to reduce the impact on the input power bus; the third is the current limit, through the current detection channel, if the current exceeds the threshold for a certain period of time, the control is turned off, so as to protect the superior power supply and the current The purpose of the board circuit.
  • the combined slow start circuit of the existing solution is shown in FIG. 1, the combined slow start circuit includes at least two power sources V1 and V2, a combined slow start chip IC1, and three metal oxide semiconductors semiconductor (MOS) transistors N1, N2 and N3, output Vout and so on.
  • MOS metal oxide semiconductors semiconductor
  • V1 is connected to the source of N1, the gate of N1 is connected to the OG1 pin of IC1, V2 is connected to the source of N2, the gate of N1 is connected to the OG2 pin of IC1, and the drain of N1 is connected to the drain of N2 ,
  • the combined circuit is connected to the drain of N3, the gate of N3 is connected to the GATE pin of IC1, the GATE pin can be understood as the control terminal of IC1 controlling N3, and the source of N3 is connected to the output terminal Vout.
  • the rate of rise of the output voltage Vout is controlled by controlling the rate of rise of the gate voltage of N3, thereby controlling the impact on the input bus and reducing the impact on the input power bus.
  • the existing implementation is basically a transparent transmission of the input voltage, and the input voltage will be transmitted to the next level within the design range of the chip. Therefore, if there is a surge shock at the upper stage, that is, an impulse voltage that exceeds the stable voltage instantaneously, the impulse voltage is transmitted to the next stage, and all power supply designs of the latter stage must meet the requirements of the highest voltage of the upper stage and adopt a relatively high voltage process . For example, if the power supply is output to multiple devices, the multiple devices need to withstand high voltage.
  • the chip with high voltage process has the disadvantages of higher cost and lower efficiency.
  • the embodiments of the present application provide a combined slow-start circuit, a combined slow-start chip and electronic equipment, which are used to improve the surge resistance of the combined slow-start circuit and reduce the cost of subsequent equipment using the combined slow-start circuit .
  • a combined slow start circuit of the first aspect of the present application includes: at least one input power supply, a first metal oxide semiconductor mos tube, a combined slow start chip and an output voltage terminal; wherein, the combined slow start chip Also includes a feedback circuit;
  • the output terminal of the at least one input power source is connected to the drain of the first mos tube, the gate of the first mos tube is connected to the first control pin of the combined slow-start chip, and the source of the first mos tube outputs the output voltage
  • the input terminal of the feedback circuit is connected to the output voltage terminal, and the output terminal of the feedback circuit is connected to the first control pin;
  • the output voltage of the output voltage terminal is input to the feedback circuit, and the feedback circuit obtains a control voltage according to the output voltage, and outputs it to the gate of the first mos tube through the first control pin;
  • the control voltage output by the feedback circuit is reduced, and the gate input voltage of the first mos tube is reduced, so that the first mos tube is not fully turned on.
  • the control voltage output by the feedback circuit decreases, thereby reducing the voltage input to the grid of the first mos tube to control the incomplete first mos tube Turn on or off. Therefore, the voltage output from the output voltage terminal also decreases. Therefore, when there is a surge in the input voltage, the feedback circuit controls the incomplete conduction or cut-off of the first mos tube, so that the output voltage of the source of the first mos tube is reduced, so the output voltage is reduced, and the surge impact can be suppressed.
  • the feedback circuit may include an operational amplifier and a second mos tube
  • the non-inverting input terminal of the operational amplifier is connected to the output voltage terminal, the inverting input of the operational amplifier is connected to a reference power source, the output terminal of the operational amplifier is connected to the gate of the second mos tube, and the drain of the second mos tube The grid of the first mos tube is connected, and the source of the second mos tube is grounded.
  • the output voltage when the output voltage is too high, it is fed back to the gate of the second mos tube through the operational amplifier, thereby controlling the conduction of the second mos tube, and the source of the second mos tube is grounded. Therefore, it is equivalent to Ground the grid of the first mos tube.
  • the voltage of the grid of the first mos tube is reduced, so that the first mos tube is not fully turned on or off, thereby reducing the voltage output from the source of the first mos tube. Therefore, the output voltage is reduced, and surge surge can be suppressed.
  • the combined slow start circuit may further include: a first resistor and a second resistor;
  • the output voltage terminal is connected to one end of the first resistor, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier and one end of the second resistor, and the other end of the second resistor is grounded.
  • the specific value of the voltage clamping in the embodiment of the present application can be determined by configuring the values of the first resistor and the second resistor, and the divided voltage can be input to the operational amplifier through the two resistors In it, the input of the feedback circuit is realized, so as to control the on and off of the first mos tube, and then the output voltage of the output voltage terminal.
  • the at least one input power supply includes a first input power supply and a second input power supply
  • the combined slow-start circuit further includes a third mos tube and a fourth mos tube
  • the output end of the first input power supply is connected to the source of the third mos tube, the gate of the third mos tube is connected to the second control pin of the combined slow-start chip, and the drain of the third mos tube is connected to the The drain of the first mos tube;
  • the output end of the second input power source is connected to the source of the fourth mos tube, the gate of the fourth mos tube is connected to the third control pin of the combined slow-start chip, and the drain of the fourth mos tube is connected to the The drain of the first mos tube.
  • the second control pin and the third control pin may be used to control the conduction or cut-off of the second mos tube and the third mos tube. Therefore, it is avoided that the output voltage of the first input power supply or the second input power supply is too large, which may cause component loss in the circuit.
  • the combined slow-start circuit further includes a first capacitor, one end of the first capacitor is connected to the output voltage terminal, and the other end of the capacitor is grounded.
  • the combined slow start circuit further includes a second capacitor and a third resistor
  • One end of the second capacitor is connected to the gate of the first mos tube, the other end of the second capacitor is connected to one end of the third resistor, and the other end of the third resistor is grounded.
  • the delay control of the first mos tube is realized to achieve the effect of slow start.
  • the combined slow start circuit further includes a fourth resistor
  • One end of the fourth resistor is connected to the drain of the first mos tube, and the other end of the fourth resistor is connected to the drain of the second mos tube and the drain of the third mos tube.
  • the second aspect of the present application provides a combined slow-start chip applied to a combined slow-start circuit.
  • the combined slow-start circuit includes at least one input power supply, a first metal oxide semiconductor mos tube, a combined slow-start chip and an output At the voltage end, the combined slow-start chip includes a feedback circuit and a first control pin;
  • the output terminal of the at least one input power source is connected to the drain of the first mos tube, the gate of the first mos tube is connected to the first control pin, and the source of the first mos tube is the output voltage terminal;
  • the input terminal of the feedback circuit is connected to the output voltage terminal, and the output terminal of the feedback circuit is connected to the first control pin;
  • the output voltage of the output voltage terminal is input to the feedback circuit, and the feedback circuit obtains a control voltage according to the output voltage, and outputs it to the gate of the first mos tube through the first control pin;
  • the control voltage is reduced, and the gate input voltage of the first mos tube is reduced, so that the first mos tube is turned off.
  • the feedback circuit includes an operational amplifier and a second mos tube
  • the non-inverting input terminal of the operational amplifier is connected to the output voltage terminal, the inverting input of the operational amplifier is connected to a reference power source, the output terminal of the operational amplifier is connected to the gate of the second mos tube, and the drain of the second mos tube The grid of the first mos tube is connected, and the source of the fourth mos tube is grounded.
  • the combined slow start circuit further includes: a first resistor and a second resistor;
  • the output voltage terminal is connected to one end of the first resistor, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier and one end of the second resistor, and the other end of the second resistor is grounded.
  • the at least one input power supply includes a first input power supply and a second input power supply
  • the combined slow-start circuit may further include a third mos tube and a fourth mos tube.
  • the slow start chip also includes a second control pin and a third control pin;
  • the output end of the first input power source is connected to the source of the third mos tube, the gate of the third mos tube is connected to the second control pin, and the drain of the third mos tube is connected to the drain of the first mos tube pole;
  • the output end of the second input power source is connected to the source of the fourth mos tube, the gate of the fourth mos tube is connected to the third control pin, and the drain of the fourth mos tube is connected to the drain of the first mos tube pole.
  • a third aspect of the present application provides an electronic device.
  • the electronic device includes the combined slow-start circuit as in any one of the foregoing embodiments of the first aspect.
  • a fourth aspect of the present application provides an electronic device, characterized in that the electronic device includes the combined slow-start chip in any embodiment of the foregoing second aspect.
  • the embodiment of the present application when the input voltage higher than the threshold value is input, the control voltage output by the feedback circuit is used to control the input voltage of the gate of the first mos tube to decrease, thereby making the first A MOS tube is not fully turned on or off to avoid outputting the input voltage above the threshold to the output voltage. Therefore, the embodiment of the present application controls the output voltage within a certain range by adding a feedback circuit to suppress the surge impact, and the equipment receiving the output voltage terminal at the subsequent stage reduces the voltage of the high-voltage resistant process, without the need for excessive high-voltage resistant process manufacturing, which reduces The cost of post-stage equipment improves manufacturing efficiency.
  • FIG. 1 is a schematic diagram of an embodiment of a combined slow start circuit in an existing solution
  • FIG. 2 is a schematic diagram of an embodiment of a combined slow start circuit provided in an embodiment of the present application
  • FIG. 3 is a schematic diagram of another embodiment of a combined slow start circuit provided in an embodiment of the present application
  • 5 is a schematic diagram of the control voltage of the combined slow start circuit provided in the embodiment of the present application.
  • the application provides a combined slow-start circuit, a combined slow-start chip and electronic equipment, which are used to improve the surge resistance of the combined slow-start circuit and reduce the cost of using the combined slow-start circuit.
  • the combined slow-start chip provided in the embodiments of the present application can be applied to a combined slow-start circuit, and the combined slow-start circuit or the combined slow-start chip can also be applied to various electronic devices, such as mobile phones, routers, etc. .
  • the combined slow-start circuit and the combined slow-start chip provided in the embodiments of the present application will be described below, please refer to FIG. 2, the combined slow-start circuit provided in the embodiments of the present application.
  • the combined slow-start circuit includes at least one input power supply, a first mos tube N1, a combined slow-start chip IC, and an output voltage terminal Vout; wherein, the combined slow-start chip further includes a feedback circuit.
  • the at least one input power supply may include one or more input power supplies, and the plurality of input power supplies are two or more.
  • the following uses two input power sources V1 and V2 as an example for description.
  • the first mos tube N1 is described by taking an N-Metal-Oxide-Semiconductor (NMOS) as an example, and the first mos tube may also be a P-Metal-Oxide-Semiconductor , PMOS), which can be adjusted according to the actual application scenario.
  • NMOS N-Metal-Oxide-Semiconductor
  • PMOS P-Metal-Oxide-Semiconductor
  • the output terminal of the input power supply V1 After the output terminal of the input power supply V1 is combined with the output terminal of V2, it is connected to the drain of N1, and the source of N1 is connected to the output voltage terminal.
  • the output voltage terminal outputs the output voltage of the combined slow-start circuit.
  • the gate of N1 is connected to the first control pin of the combined slow start chip, the first control pin is connected to the output terminal of the feedback circuit, and the input terminal of the feedback circuit is connected to the output voltage terminal.
  • the integrated slow start chip adds a pin, namely the SPE pin, the input terminal of the feedback circuit is the SPE pin of the combined slow start chip, and the output end of the feedback circuit is connected to the first of the combined slow start chip
  • the control pin is the GATE pin in Figure 2.
  • the output voltage at the output voltage terminal passes through the input value feedback circuit of the SPE pin.
  • the feedback circuit obtains a control voltage according to the voltage output from the output voltage terminal, and inputs it to the gate of N1 through the GATE pin to control the turning on or off of N1.
  • the control voltage output by the feedback circuit decreases, thereby reducing the voltage input to the gate of N1, thereby controlling N1 to not be fully turned on or off To reduce the output voltage at the output voltage end.
  • the combined slow-start chip in the embodiment of the present application may include other pins (not shown in the figure) in addition to the aforementioned GATE pins and SPE pins, for example, power pins and ground pins Wait, it can be adjusted according to the actual application scenario.
  • the control voltage output by the feedback circuit controls the input voltage of the gate of the first mos tube to decrease, so that the first mos tube is not fully turned on or Cut off to avoid outputting the input voltage above the threshold to the output voltage. Therefore, in the embodiment of the present application, by adding a feedback circuit, the output voltage is controlled within a certain range to suppress the surge impact, and the equipment receiving the output voltage terminal at the subsequent stage reduces the voltage of the high-pressure-resistant process, without the need for excessive high-pressure-resistant process manufacturing, which reduces The cost of post-stage equipment improves manufacturing efficiency.
  • the two power sources V1 and V2 are still used as an example for description.
  • the feedback circuit includes an operational amplifier F1 and a second mos tube N2.
  • N2 may be NMOS or PMOS. Here, only NMOS will be used as an example for description. When N2 is a PMOS, the connection structure is similar to NMOS, and will not be repeated here.
  • the non-inverting input end of F1 is connected to the SPE pin, the SPE pin is connected to the output voltage end, the inverting input end of F1 inputs the reference voltage Vi, and the output end of F1 is connected to the gate of N2.
  • the source of N2 is grounded, and the drain of N2 is connected to the GATE terminal, which is the first control terminal.
  • the non-inverting input terminal of F1 When the non-inverting input terminal of F1 receives the voltage input from the output voltage terminal, the voltage is compared with the reference voltage Vi, and an amplification operation is performed to output to the gate of N2, thereby controlling the cut-off or conduction of N2.
  • the output voltage at the output voltage terminal increases and is fed back to the non-inverting input terminal of the operational amplifier F1 through the SPE pin. If the output voltage is too high, the output voltage of the operational amplifier F1 also increases after amplification, and then the output voltage of F1 Feedback to the gate of N2, when higher than the turn-on voltage of N2, N2 is turned on.
  • N1 is turned off, the output voltage at the output voltage terminal is lowered, which is fed back to the operational amplifier F1 to reduce the output voltage of F1.
  • F1 is fed back to the operational amplifier F1 to reduce the output voltage of F1.
  • N2 is turned off and the current source inside the chip slowly turns on to output current to N1 Of the gate, thereby controlling N1 to turn on. Therefore, in the embodiment of the present application, a feedback circuit is used to feedback the output voltage at the output voltage terminal in real time to control the on or off of N1, so that the output voltage at the output voltage terminal is controlled within a preset range.
  • a current source Is is also provided inside the combined slow-start chip, and one end of the Is is connected to the GATE pin.
  • N2 When N2 is turned off, the output current of Is is turned on to the gate of N1, and the voltage input to the gate of N1 is higher than the turn-on voltage of N1, thereby turning on N1. Therefore, when the output voltage at the output voltage terminal is within the normal voltage range, N2 is turned off and N1 is turned on. Thus, the output voltage is stably output.
  • the combined slow start circuit further includes a first resistor R1 and a second resistor R2.
  • the specific value of the voltage clamping in the embodiment of the present application can be determined by configuring the values of R1 and R2, and the divided voltage is input to the SPE pin through two resistors to implement a feedback circuit To control the turn-on and turn-off of N1, and then the output voltage at the output voltage terminal.
  • the combined slow start circuit may further include a first capacitor C1.
  • One end of the first capacitor C1 is connected to the source of N1, and the other end of C2 is grounded. To filter the output voltage to make the output voltage more stable.
  • the combined slow start circuit may further include a second capacitor C2 and a third resistor R3.
  • One end of C2 is connected to the gate of N1, the other end of C2 is connected to one end of R3, and the other end of R3 is grounded.
  • the delay between the charging and discharging of C2 may be used to realize the delay of controlling N1, and thus the slow start.
  • a third mos tube N3 and a fourth mos tube N4 may also be included between V1, V2, and N1.
  • the input of V1 is connected to the source of N3, the gate of N3 is connected to the second control pin IN2 of the combined slow-start chip, and the drain of N3 is connected to the drain of N1.
  • the input of V2 is connected to the source of N4, the gate of N4 is connected to the third control pin IN3 of the combined slow-start chip, and the drain of N4 is connected to the drain of N1.
  • N1, N2, N3, and N4 may be NMOS, or one or more of them may be PMOS, and the connection structure thereof is combined with the foregoing combination of FIG. 2 or FIG. 3.
  • the start circuit is similar, and the embodiments of the present application will not repeat them here.
  • the ON2 and IN3 pins of the slow-start chip can be combined to control the turn-on or turn-off of N3 and N4. Therefore, the output voltage of V1 or V2 is too large, which may cause the loss of components in the circuit.
  • the combined slow start circuit may further include a fourth resistor R4.
  • One end of R4 is connected to the drain of N1, and the other end of R3 is connected to the drains of N3 and N4.
  • the comparison between the input voltage and the output voltage may be as shown in FIG. 4.
  • the amplitude of the voltage output by N1 is significantly lower, and the output voltage can be controlled within a preset range.
  • the voltage input to the gate of N1 can be as shown in FIG. 5.
  • the output voltage is divided by two resistors R1 and R2, and the divided voltage is input to the operational amplifier.
  • the feedback circuit processes the input voltage and outputs it to N2, thereby controlling the turn-on and turn-off of N2.
  • N2 When N2 is turned on, the gate of N1 is equivalent to ground. Therefore, the voltage value input to the gate of N1 is pulled down, so that N1 is not completely turned on or off.
  • N1 receives the voltage input from the integrated slow-start chip, and the voltage is greater than the turn-on voltage of N1, and N1 is turned on. Therefore, the feedback circuit can be used to control the turn-on and turn-off of N1.
  • the output voltage is too high, N1 is turned off.
  • the voltage input to the feedback circuit can be configured by configuring the values of the two resistors R1 and R2, thereby controlling the output voltage at the output voltage terminal.
  • An embodiment of the present application further provides an electronic device.
  • the electronic device may include the combined slow-start circuit in any of the foregoing embodiments in FIG. 2 or FIG. 3.
  • the electronic device may be a mobile phone, tablet computer, router, etc.
  • the electronic device may further include a processor, a memory, a display, etc., which is not specifically limited in the embodiments of the present application.
  • An embodiment of the present application further provides another electronic device.
  • the electronic device may include the combined slow-start chip in any of the foregoing embodiments in FIG. 2 or FIG. 3.
  • the electronic device may be a mobile phone, tablet computer, router, etc.
  • the electronic device may further include a processor, a memory, a display, etc., which is not specifically limited in the embodiments of the present application.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
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Abstract

La présente invention concerne un circuit de démarrage progressif combiné, une puce de démarrage progressif combinée (IC) et un dispositif électronique, qui sont utilisés pour améliorer la capacité de gestion de surtension. Le circuit de démarrage progressif combiné comprend au moins une alimentation électrique d'entrée (V1, V2), un premier transistor à semi-conducteur à oxyde métallique (mos) (N1), une puce de démarrage progressif combinée (IC) et une borne de tension de sortie (Vout); la puce de démarrage progressif combinée (IC) comprend un circuit de rétroaction; une borne de sortie de ladite alimentation électrique d'entrée (V1, V2) est connectée à un drain du premier transistor mos (N1), une grille du premier transistor mos (N1) est connectée à une première broche de commande (GATE) de la puce de démarrage progressif combinée (IC), et une source du premier transistor mos (N1) est la borne de tension de sortie (Vout); une borne d'entrée (SPE) du circuit de rétroaction est connectée à la borne de tension de sortie (Vout), et une borne de sortie du circuit de rétroaction est connectée à la première broche de commande (GATE); une tension de sortie de la borne de tension de sortie (Vout) est entrée dans le circuit de rétroaction, et le circuit de rétroaction génère une tension de commande, et la fournit à la grille du premier transistor mos (N1) au moyen de la première broche de commande (GATE); et lorsque la ou les alimentations électriques d'entrée (V1, V2) entrent une tension supérieure à un seuil, la tension de commande fournie par le circuit de rétroaction diminue, et une tension d'entrée de grille du premier transistor mos (N1) diminue, de telle sorte que le premier transistor mos (N1) n'est pas complètement allumé.
PCT/CN2018/119067 2018-12-04 2018-12-04 Circuit de démarrage progressif combiné, puce de démarrage progressif combinée et dispositif électronique Ceased WO2020113402A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218003A (zh) * 2013-04-26 2013-07-24 无锡中星微电子有限公司 一种多电源输入的低压差稳压器
CN103324233A (zh) * 2013-05-29 2013-09-25 中科院微电子研究所昆山分所 一种低通滤波器及低压差线性稳压器
CN104699153A (zh) * 2013-12-10 2015-06-10 展讯通信（上海）有限公司 低压差线性稳压器
CN105446404A (zh) * 2014-08-19 2016-03-30 无锡华润上华半导体有限公司 低压差线性稳压器电路、芯片和电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218003A (zh) * 2013-04-26 2013-07-24 无锡中星微电子有限公司 一种多电源输入的低压差稳压器
CN103324233A (zh) * 2013-05-29 2013-09-25 中科院微电子研究所昆山分所 一种低通滤波器及低压差线性稳压器
CN104699153A (zh) * 2013-12-10 2015-06-10 展讯通信（上海）有限公司 低压差线性稳压器
CN105446404A (zh) * 2014-08-19 2016-03-30 无锡华润上华半导体有限公司 低压差线性稳压器电路、芯片和电子设备

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