WO2020120735A1 - Procédé de dépôt d'une hétérostructure et hétérostructure déposée selon le procédé - Google Patents

Procédé de dépôt d'une hétérostructure et hétérostructure déposée selon le procédé Download PDF

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WO2020120735A1
WO2020120735A1 PCT/EP2019/085073 EP2019085073W WO2020120735A1 WO 2020120735 A1 WO2020120735 A1 WO 2020120735A1 EP 2019085073 W EP2019085073 W EP 2019085073W WO 2020120735 A1 WO2020120735 A1 WO 2020120735A1
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layer
lattice constant
heterostructure
layers
deposited
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Dirk Fahle
Matthias Marx
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Aixtron SE
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3216—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3251—Layer structure consisting of three or more layers
    • H10P14/3252—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/854—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs further characterised by the dopants

Definitions

  • the invention relates to a method for depositing a heterostructure from single-crystal layers with different lattice constants, a nucleation layer on a substrate, a buffer layer consisting of a layer sequence on the nucleation layer and at least one active layer on the buffer layer be deposited.
  • the layer sequence here has a multiplicity of pairs of layers which are clamped to one another, consisting of a first layer which has a first lattice constant in an unstressed crisis and which exerts a lateral tensile stress on the substrate as a layer of the layer sequence, and a second layer which has a second lattice constant in an unstrained crystal, which is greater than the first lattice constant, and as the layer of the layer sequence exerts a lateral compressive stress on the substrate.
  • the invention further relates to a heterostructure of monocrystalline layers with different lattice constants, with a nucleation layer on a substrate, a buffer layer consisting of a coherent layer sequence on the nucleation layer and at least one active layer being deposited on the buffer layer.
  • the layer sequence results from a multiplicity of mutually strained pairs of layers, in particular consisting of a first layer which has a first lattice constant in an unstrained crystal, and a second layer which has a second lattice constant in an unstrained crystal which is greater than the first Lattice constant, where a local lattice constant is the second Layer with formation of lattice defects increases with increasing distance from the underlying first layer.
  • the invention also relates to an electronic component, in particular HEMT with a heterostructure.
  • the first of the publications described above describes a layer system which is deposited on a silicon substrate or silicon carbide substrate.
  • a nucleation layer is first deposited on the silicon substrate.
  • the nucleation layer is particularly important because the lattice constant of the buffer layer deposited on the nucleation layer differs from the lattice constant of the substrate.
  • the aim of depositing a nucleation layer is to achieve an essentially single-crystalline surface, so that a coherent surface is formed on this surface
  • the super lattice essentially contains layers of A1N or AlGaN. It is important that the aluminum content is as high as possible, since an active layer system for a high electron mobility transistor (HEMT) is to be deposited on the buffer layer and a high aluminum concentration is a prerequisite for a high electrical breakdown voltage.
  • the buffer layer which is made up of several pairs of layers arranged one above the other, also has the task of increasing the stress conditions resulting from the deposition of the remaining layers and from the difference in the thermal expansion coefficients of the materials used compensate so that the substrate extends in one plane after coating.
  • the two layers of the pair of layers from which the super lattice of the buffer layer is constructed have different lattice constants.
  • the layers are deposited in a coherent crystal structure, as is clearly shown in FIGS. 2A to 2C of US Pat. No. 9,090,993 B2.
  • the first layer the AIN layer
  • the AlGaN layer stresses arise in both directions on both sides of the boundary layer between the two layers. In the area of the first layer a tensile stress builds up and in the area of the second layer an opposing compressive stress.
  • the layer sequence tends to bend.
  • the nucleation layer (AIN layer) deposited directly on the substrate, for example on a silicon substrate, exerts a tensile stress on the substrate. These tensions have to be balanced in such a way that they are averaged out at room temperature in such a way that the substrate is not arched, i.e. in one plane.
  • AIN layer a variety of alternating tensile stress and a are on the nucleation layer
  • Layers of compressive stress are deposited on the substrate, the layer thickness and the layer composition being designed, if possible, in such a way that the stresses in the entire structure are balanced, in particular also those resulting from the difference in the coefficients of thermal expansion.
  • the invention is based on the finding that the second layer (AlGaN layer) exerting a lateral compressive stress on the substrate relaxes with increasing distance from the underlying layer.
  • the second layer has a lattice constant that is greater than the lattice constant of the layer below, so that the monolayers of the second layer deposited directly on the first layer are under compressive stress. This compressive stress leads to lattice defects forming with increasing distance from the boundary layer to the first layer, which result in a local increase in the lattice constant.
  • the local lattice constant thus increases with increasing distance between the layers of the layer, with the result that the lateral stress within the crystal is reduced. As a result, the compressive stress drops, which otherwise compensates for the tensile stress of the underlying layer.
  • the observed crack-free relaxation of the second layer causes an increased tensile stress in the first layer of a further layer pair deposited on the second layer, since the lattice constant of the second layer is much smaller than the lattice constant of the relaxed first layer. Since the first layer is considerably thinner than the second layer, it has only a small relaxation and thus a smaller number of lattice defects, despite an internal tension.
  • a method of the generic type is described in DE 11 2014 003 533 T5.
  • a buffer layer made of A1N with a thickness of 150 nm is deposited on a silicon substrate.
  • This AIN layer Layer pairs deposited from A1N and AlGaN.
  • the AIN layer should be 5 nm and the AlGaN layer 16 nm thick. 75 such pairs are deposited on top of each other.
  • a 70 nm thick A1N intermediate layer is then deposited.
  • the AlGaN layer is only about three times as thick as the AIN layer.
  • the invention has for its object to provide measures with which a buffer layer consisting of a large number of layers, in particular layer pairs, can be built up stress-free and in particular enables the aluminum content of the buffer layer to be as high as possible.
  • the second layer which can be an AlGaN layer
  • the first layer which can be an AIN layer.
  • a more strained first layer in particular an AIN layer, is formed since the second layer relaxes more due to its greater layer thickness.
  • the distance between two intermediate layers that is the sum of the layer thicknesses of the pairs of layers arranged between two intermediate layers or the nucleation layer and a first intermediate layer, each consisting of a first and a second layer, is preferably in a range between 150 nm and 1 ⁇ m.
  • the preferred method for separating the heterostructure according to the invention is a MOCVD method in which gaseous starting materials, which contain aluminum, gallium and nitrogen, are fed into a process chamber of a CVD reactor.
  • the deposition of the layer sequence existing on the first layer and the second layer is preferably carried out with a constant flow of a process gas containing aluminum and a process gas containing nitrogen.
  • this layer sequence is separated, only the inflow of the gas containing gallium is periodically switched on or off.
  • an intermediate layer be deposited between a first number of pairs of layers.
  • Each pair of layers consists of a layer that has a small, first equilibrium lattice constant in an unstrained crystal and a second layer that has a second, larger equilibrium lattice constant in an unstrained crystal. Due to the epitaxial correlation to the nucleation layer or the previously deposited layers, the first layer is tensile and the second compressive. The mutual bracing has the consequence that the actual lattice spacing in the two layers deviates from the respective equilibrium lattice constants. It is referred to below as the local grid constant.
  • an intermediate layer is deposited at the latest when the second layer is almost completely relaxed, that is to say particularly preferably after the deposition of at least five identical pairs of layers, preferably after at least eight identical pairs of layers.
  • the intermediate layer consists of a crystal which has a small equilibrium lattice constant in the untensioned state and in particular that of the first layer.
  • the intermediate layer can be identical to the material of the first layer.
  • the intermediate layer is applied to the layer pair system with such a deposited layer thickness that the intermediate layer exerting a strong tensile stress in the interface relaxes with increasing distance from the underlying layer.
  • the relaxation also takes place here with the formation of imperfections, but without cracks, whereby - unlike the relaxation of the second layer - the local lattice constant does not increase, but decreases. This has the consequence that the tensile stress built up by the intermediate layer within the intermediate layer decreases with increasing distance from the layer below.
  • a crystal layer which preferably has the same local lattice constant as the surface of the nucleation layer before the deposition of the first layer.
  • At least one further layer sequence is then deposited on the intermediate layer, which has essentially the same properties as the layer sequence described above and deposited directly on the nucleus layer.
  • at least five, preferably at least eight, identical pairs of layers can be deposited.
  • the active layers can then be deposited on this further layer sequence.
  • the at least one active layer can have a doped or undoped GaN layer.
  • a multiplicity of layer sequences, each separated from an intermediate layer can be deposited one above the other, the layer sequences consisting of identical, directly deposited layer pairs consisting of exactly two layers.
  • the first layer preferably consists of A1N
  • the second layer preferably consists of AlGaN, the aluminum nitride component being at least 25, preferably at least 27 percent.
  • the layer thickness of the first layer is in the range between 2 and 10 nm and preferably in the range between 3 and 5 nm.
  • the layer thickness of the second layer is at least a factor 5 greater than the layer thickness of the first layer. Their layer thickness can be in the range between 20 and 40 nm.
  • the layer thickness of the intermediate layer is by a factor of 5, preferably a factor of 8 and particularly preferably a factor 10 greater than the layer thickness of the first layer. It is preferably also greater than the layer thickness of the second layer.
  • the intermediate layer preferably consists of A1N.
  • the entire layer sequence consisting of identical pairs can have a layer thickness in the range between 150 nm and 1 gm. But it can also have a layer thickness of 2 to 3 gm.
  • a HEMT structure which consists of an undoped GaN, an A1N and an AlGaN layer, can be deposited on preferably eight layer sequences, which are each separated from one another by an intermediate layer and each preferably have eight layer pairs.
  • a component produced with a heterostructure according to the invention additionally has electrical contacts.
  • the number of pairs of layers arranged between two intermediate layers is not the same in each case, but rather increases with increasing distance from the substrate.
  • the increase in the number of interlayers can be linear.
  • the increase in the intermediate layers can also be sublinear or superlinear and, in particular, exponential.
  • a relevant factor can be between 1.1 and 2 and preferably 1.5, so that, for example, eight layer pairs are arranged between the nucleation layer and the first intermediate layer, twelve layer pairs between the first intermediate layer and the second intermediate layer, and eighteen layer pairs are arranged between the second intermediate layer and the third intermediate layer.
  • Such a gradual increase in the number of pairs of layers improves the quality of the surface of the top layer.
  • FIG. 1 shows a first exemplary embodiment of a layer sequence which is deposited using the method according to the invention
  • Fig. 2 shows a second embodiment of the layer sequence
  • Fig. 3 explains the technical effect of the layer structure according to the invention.
  • Fig. 4 shows schematically an electronic component.
  • FIG. 1 shows a layer sequence deposited in a MOCVD reactor on a p-Si (1 1 1) substrate with a substrate thickness of 725 gm.
  • a 150 nm thick AIN nucleation layer N is first removed from the substrate been divorced.
  • a layer sequence in the form of eight pairs of layers has been deposited on this nucleation layer N and consists of a first layer A and a second layer B, the first layer A being a 4 nm thick A1N and the second layer B being a 30 nm thick AlGaN 27 layer is.
  • An intermediate layer C of 40 nm A1N was then deposited on this first layer sequence.
  • This layer system comprising eight pairs of layers of the same design and an intermediate layer C deposited thereon was deposited eight times one above the other.
  • This buffer layer is complemented by a further layer sequence AB, a 300 nm GaN layer D and a 700 nm GaN: C layer E.
  • the layers A, B, C are selected with regard to their layer thicknesses in such a way that, in total, they do not exert any lateral tension on the substrate at room temperature, so that the substrate extends in one plane.
  • Figure 2 shows somewhat more generally the layer structure according to the invention, in which a nucleation layer N is first deposited on a substrate. A pair of layers is then deposited on the nucleation layer N in n-fold order, the layer pair consisting of a first layer A with a first equilibrium lattice constant and a second layer B with a second, different lattice constant. An intermediate layer C, which has a different equilibrium lattice constant than the second layer B, is deposited onto this n-fold layer sequence. This layer system consisting of the intermediate layer C and the n-layer pairs is deposited several times one above the other. Two sequence layer systems are deposited in FIG. 2, onto which a system of active layers D, E, F is then deposited.
  • the equilibrium lattice constant of the intermediate layer C can correspond to the first equilibrium lattice constant. Since the second layer B is thicker than the first layer A, its local lattice constant approaches the equilibrium lattice constant with increasing distance from the underlying layer. The local lattice constant of the first layer A changes only slightly.
  • the intermediate layer C which is deposited on the second layer B with a local lattice constant of the underlying second layer B, changes its local lattice constant with increasing distance from the underlying layer in the direction of the equilibrium lattice constant of the intermediate layer C.
  • FIG. 3 illustrates under III the layer structure shown in FIGS. 1 and 2.
  • a plurality of first and second layers A, B are separated in the form of pairs of layers.
  • the lines pointing obliquely upwards illustrate the decrease in tensile stresses or compressive stresses in the layers.
  • the tensile stresses are illustrated by two arrows pointing towards each other and the compressive stresses by two arrows pointing away from each other.
  • I illustrates the magnitude of the tensile stress S (left -) or the compressive stresses (right +) similar to the lines pointing upward in III.
  • the nucleation layer N deposited on the substrate has a first equilibrium lattice constant in a relaxed crystal which corresponds to that of A1N. This differs from the equilibrium lattice constant of the substrate S, so that the nucleation layer N exerts a tensile stress on the substrate which, as a result of the relaxation of the nucleation layer N, decreases with increasing distance from the substrate.
  • a first layer A is deposited on the nucleation layer N, which in the exemplary embodiment likewise consists of A1N and which exerts a tensile stress.
  • the second layer B is an AlGaN layer which has a second equilibrium lattice constant which is greater than the first equilibrium lattice constant.
  • the second layer B applies a compressive stress to the substrate S.
  • the local lattice constant in the second layer B increases with increasing distance from the substrate. This relaxation has the consequence that the tensile stress shown in I decreases with increasing distance from the first layer A.
  • III and II show that the local lattice constant increases increasingly due to the several layers pairs deposited one above the other, with the result that the tensile stresses applied by layers A become greater with increasing distance from the substrate, which are exerted by layers B. Compressive forces decrease with increasing distance.
  • the compressively stressed layers B are designed to be considerably thicker than the tensile stress layers A and thus compensating compressive stresses are introduced.
  • an intermediate layer C made of A1N or AlGaN is deposited on the layer sequence.
  • the material of the intermediate layer C has an equilibrium lattice constant that is considerably smaller than the local lattice constant of the uppermost second layer B at the interface with the intermediate layer C.
  • FIG. 3 shows that the nucleation layer N is followed directly by a first layer A. However, it can also be provided that the nucleat The second layer B follows immediately if the first layer A is identical to the nucleation layer N.
  • the number of pairs of layers, which are located between the nucleation layer and the first intermediate layer C or between the subsequent intermediate layers C increases successively, for example by a factor of 1.2 or 1.5.
  • the interface of the intermediate layer C with the next first layer A deposited thereon of a further layer sequence has approximately the value that the local lattice constant of the nucleation layer N has at the interface with the first layer A. It is thus possible to deposit virtually any number of layer sequences, each consisting of several pairs of layers and an intermediate layer C, in order to form a buffer layer for an HEMT structure that is as rich in aluminum as possible.
  • the invention also has the following advantages: by the possibility that strain engineering can be used even at high temperatures, it is possible to reduce the intrinsic carbon level in the super lattice and the carbon incorporation by a dopant, for example Ethene and propane can be specifically adjusted, which can improve both the breakdown voltage and the dynamic behavior of the buffer.
  • a dopant for example Ethene and propane
  • a relatively large compressive stress builds up in the layer system. Due to the thickness and the position of the intermediate layer C, which is composed in particular of A1N, in the buffer layer, the tension can be set in a very targeted manner and thus also the bending of the substrate during and after a deposition process of the layers.
  • This "interlayer approach” enables a super lattice buffer to be deposited at temperatures below 1,000 ° C, for example 940 ° C, but also above 1,000 ° C, for example at 1,050 ° C.
  • the structure of the intermediate layer C corresponds to the growth temperature of the su per lattice buffer.
  • a crack-free relaxed intermediate layer C can be deposited with the specified process parameters.
  • FIG. 4 schematically shows a HEMT with two electrical contacts K on the active layer sequence D, E, F.
  • a method which is characterized in that after at least five pairs of layers, an intermediate layer C which is tensioned counter to the second layer B and which is at least five times as thick as the first layer A and whose tension decreases with increasing layer thickness as a result of relaxation is deposited .
  • a method which is characterized in that the crystalline connection of the first layer A in an unstrained crystal has a first equilibrium lattice constant which is smaller than a second equilibrium lattice constant which the crystalline connection of the second layer B in one has unstressed crystal, so that the first layer A exerts a lateral tensile stress and the second layer exerts a lateral compressive stress.
  • a heterostructure which is characterized in that one or more layers on at least five identical, in particular identical layers ten pairs follows an intermediate layer C, which has a different, in particular smaller, equilibrium lattice constant than the second equilibrium lattice constant in an unstrained crystal and whose layer thickness is at least five times the first layer thickness.
  • a method or a hetero structure which are characterized in that a local lattice constant of the second layer B changes with the formation of lattice defects with increasing distance from the underlying layer A to the second equilibrium lattice constant and the layer thickness of the intermediate layer C is so large that a local lattice constant of the intermediate layer C changes with the formation of lattice defects with increasing distance from the layer below to the first equilibrium lattice constant.
  • a method or a heterostructure which are characterized in that the substrate S consists of silicon, the nucleation layer made of A1N, the first layer A made of A1N, the second layer B made of AlGaN and the intermediate layer C made of A1N.
  • a method or a heterostructure which are characterized in that at least one active layer or layers of D, E, F is deposited on the buffer layer, in particular a doped or undoped GaN layer, AlGaN- Layer and / or AIN layer comprises.
  • a method or a hetero structure which are characterized in that the distance between two intermediate layers C is 250 nm to 1 gm.
  • a method or a hetero structure which are characterized in that the second layer B is at least six times as thick as the first layer A.
  • a method or a heterostructure which are characterized in that the heterostructure is the basic structure for a HEMT transistor.
  • a method or a hetero structure which are characterized in that the aluminum nitride content of the AlGaN layer is at least 25 percent, preferably at least 27 percent.
  • a method or a heterostructure which are characterized in that the number of particularly identical pairs of layers A, B between the nucleation layer N and the first intermediate layer C and between further intermediate layers increases with increasing distance from the substrate S, where the increase is preferably in accordance with a fixed factor.
  • a method which is characterized in that the first layer A using TMA1, NH 3 at a total pressure in a range from 25 to 100 mbar, in particular at 50 mbar and / or at a temperature in a range from 900 up to 1,000 C, in particular at 1,050 C and / or with a growth rate in a range from 2 to 12 nm / min, in particular at 8 nm / min; and / or that the second layer B using TMA1, TMGa, NH 3 at a total pressure in a range from 25 to 100 mbar, in particular at 50 mbar and / or at a temperature in a is deposited in a range from 900 to 1,100 C, in particular at 1,050 C and / or with a growth rate in a range from 10 to 40 nm / min, in particular at 28 nm / min; and / or that the intermediate layer C using TMA1, TMGa, NH 3 at a total pressure in a range from 25 to 100 mbar,
  • a component which is characterized in that the heterostructure is designed according to one of claims 3 to 10.

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Abstract

L'invention concerne un procédé de dépôt d'une hétérostructure composée de couches en particulier monocristallines, une pluralité de paires de couches constituées d'une première couche (A) et d'une seconde couche (B) en particulier plus épaisse, et soumises à une contrainte de traction ou de compression latéralement en raison de la différence des constantes de réseau entre les première et seconde couches (A, B), étant déposées sur une couche de nucléation (N) appliquée sur un substrat (S) en tant que couche tampon, de façon à ce que la contrainte de la seconde couche (B) diminue proportionnellement à l'augmentation du nombre des paires de couches à la suite d'une relaxation. Selon l'invention, afin de contrecarrer les effets de la relaxation de la seconde couche (B), une couche intermédiaire (C) soumise à une contrainte opposée par rapport à la seconde couche (B) est déposée après au moins cinq paires de couches, la couche intermédiaire étant au moins cinq fois plus épaisse que la première couche (A), et sa contrainte diminuant proportionnellement à l'augmentation de l'épaisseur de couche à la suite d'une relaxation.
PCT/EP2019/085073 2018-12-14 2019-12-13 Procédé de dépôt d'une hétérostructure et hétérostructure déposée selon le procédé Ceased WO2020120735A1 (fr)

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DE102018132263.1 2018-12-14

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10206750A1 (de) 2001-12-21 2003-07-03 Aixtron Ag Verfahren zum Herstellen von III-V-Laserbauelementen
US20040232440A1 (en) * 2003-05-21 2004-11-25 Sanken Electric Co., Ltd. Compound semiconductor substrates and method of fabrication
JP2009188252A (ja) * 2008-02-07 2009-08-20 Furukawa Electric Co Ltd:The 半導体電子デバイス
US20110272665A1 (en) * 2010-05-07 2011-11-10 Rohm Co., Ltd. Nitride semiconductor device
US20130026486A1 (en) * 2010-04-28 2013-01-31 Ngk Insulators, Ltd. Epitaxial substrate and method for manufacturing epitaxial substrate
US20130075786A1 (en) * 2011-09-28 2013-03-28 Fujitsu Limited Semiconductor device
US9090993B2 (en) 2010-02-16 2015-07-28 Ngk Insulators, Ltd. Epitaxial substrate comprising a superlattice group and method for manufacturing the epitaxial substrate
DE102014109335A1 (de) 2014-07-03 2016-01-07 Aixtron Se Verfahren zum Abscheiden säulenförmiger Strukturen
DE112014003533T5 (de) 2013-07-30 2016-04-14 Sumitomo Chemical Company, Limited Halbleiterwafer und Verfahren zur Herstellung des Halbleiterwafers
US20160190387A1 (en) 2014-12-30 2016-06-30 Sensor Electronic Technology, Inc. Strain-Control Heterostructure Growth

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10206750A1 (de) 2001-12-21 2003-07-03 Aixtron Ag Verfahren zum Herstellen von III-V-Laserbauelementen
US20040232440A1 (en) * 2003-05-21 2004-11-25 Sanken Electric Co., Ltd. Compound semiconductor substrates and method of fabrication
JP2009188252A (ja) * 2008-02-07 2009-08-20 Furukawa Electric Co Ltd:The 半導体電子デバイス
US9090993B2 (en) 2010-02-16 2015-07-28 Ngk Insulators, Ltd. Epitaxial substrate comprising a superlattice group and method for manufacturing the epitaxial substrate
US20130026486A1 (en) * 2010-04-28 2013-01-31 Ngk Insulators, Ltd. Epitaxial substrate and method for manufacturing epitaxial substrate
US20110272665A1 (en) * 2010-05-07 2011-11-10 Rohm Co., Ltd. Nitride semiconductor device
US20130075786A1 (en) * 2011-09-28 2013-03-28 Fujitsu Limited Semiconductor device
DE112014003533T5 (de) 2013-07-30 2016-04-14 Sumitomo Chemical Company, Limited Halbleiterwafer und Verfahren zur Herstellung des Halbleiterwafers
DE102014109335A1 (de) 2014-07-03 2016-01-07 Aixtron Se Verfahren zum Abscheiden säulenförmiger Strukturen
US20160190387A1 (en) 2014-12-30 2016-06-30 Sensor Electronic Technology, Inc. Strain-Control Heterostructure Growth

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